From b5d52b205285df826dea709933b4a20cd192242f Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Thu, 23 Nov 2017 19:17:11 +0100 Subject: sunxi: remove support for kernel 4.4 Kernel 4.9 is working good on this target, remove support for kernel 4.4 now. Signed-off-by: Hauke Mehrtens --- .../110-clk-sunxi-add-ve-for-sun457i.patch | 226 --------------------- 1 file changed, 226 deletions(-) delete mode 100644 target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch (limited to 'target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch') diff --git a/target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch b/target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch deleted file mode 100644 index f929753d77..0000000000 --- a/target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch +++ /dev/null @@ -1,226 +0,0 @@ -From 3cdd9f5c4953465abb87ec757159cc0576ae6b0a Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Sat, 5 Dec 2015 21:16:43 +0800 -Subject: [PATCH] clk: sunxi: Add VE (Video Engine) module clock driver for - sun[457]i - -The video engine has its own special module clock, consisting of a clock -gate, configurable dividers, and a reset control. - -On later (sun[68]i) families, the reset control is moved out of this -piece of hardware and grouped with reset controls of other peripherals. - -Signed-off-by: Chen-Yu Tsai -Tested-by: Jens Kuske -Signed-off-by: Maxime Ripard ---- - Documentation/devicetree/bindings/clock/sunxi.txt | 4 + - drivers/clk/sunxi/Makefile | 1 + - drivers/clk/sunxi/clk-a10-ve.c | 171 ++++++++++++++++++++++ - 3 files changed, 176 insertions(+) - create mode 100644 drivers/clk/sunxi/clk-a10-ve.c - ---- a/Documentation/devicetree/bindings/clock/sunxi.txt -+++ b/Documentation/devicetree/bindings/clock/sunxi.txt -@@ -73,6 +73,7 @@ Required properties: - "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 - "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 - "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 -+ "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock - - Required properties for all clocks: - - reg : shall be the control register address for the clock. -@@ -92,6 +93,9 @@ Required properties for all clocks: - And "allwinner,*-usb-clk" clocks also require: - - reset-cells : shall be set to 1 - -+The "allwinner,sun4i-a10-ve-clk" clock also requires: -+- reset-cells : shall be set to 0 -+ - The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: - - #reset-cells : shall be set to 1 - - resets : shall be the reset control phandle for the mmc block. ---- a/drivers/clk/sunxi/Makefile -+++ b/drivers/clk/sunxi/Makefile -@@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o - obj-y += clk-a10-hosc.o - obj-y += clk-a10-mod1.o - obj-y += clk-a10-pll2.o -+obj-y += clk-a10-ve.o - obj-y += clk-a20-gmac.o - obj-y += clk-mod0.o - obj-y += clk-simple-gates.o ---- /dev/null -+++ b/drivers/clk/sunxi/clk-a10-ve.c -@@ -0,0 +1,171 @@ -+/* -+ * Copyright 2015 Chen-Yu Tsai -+ * -+ * Chen-Yu Tsai -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static DEFINE_SPINLOCK(ve_lock); -+ -+#define SUN4I_VE_ENABLE 31 -+#define SUN4I_VE_DIVIDER_SHIFT 16 -+#define SUN4I_VE_DIVIDER_WIDTH 3 -+#define SUN4I_VE_RESET 0 -+ -+/** -+ * sunxi_ve_reset... - reset bit in ve clk registers handling -+ */ -+ -+struct ve_reset_data { -+ void __iomem *reg; -+ spinlock_t *lock; -+ struct reset_controller_dev rcdev; -+}; -+ -+static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct ve_reset_data *data = container_of(rcdev, -+ struct ve_reset_data, -+ rcdev); -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(data->lock, flags); -+ -+ reg = readl(data->reg); -+ writel(reg & ~BIT(SUN4I_VE_RESET), data->reg); -+ -+ spin_unlock_irqrestore(data->lock, flags); -+ -+ return 0; -+} -+ -+static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct ve_reset_data *data = container_of(rcdev, -+ struct ve_reset_data, -+ rcdev); -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(data->lock, flags); -+ -+ reg = readl(data->reg); -+ writel(reg | BIT(SUN4I_VE_RESET), data->reg); -+ -+ spin_unlock_irqrestore(data->lock, flags); -+ -+ return 0; -+} -+ -+static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec) -+{ -+ if (WARN_ON(reset_spec->args_count != 0)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static struct reset_control_ops sunxi_ve_reset_ops = { -+ .assert = sunxi_ve_reset_assert, -+ .deassert = sunxi_ve_reset_deassert, -+}; -+ -+static void __init sun4i_ve_clk_setup(struct device_node *node) -+{ -+ struct clk *clk; -+ struct clk_divider *div; -+ struct clk_gate *gate; -+ struct ve_reset_data *reset_data; -+ const char *parent; -+ const char *clk_name = node->name; -+ void __iomem *reg; -+ int err; -+ -+ reg = of_io_request_and_map(node, 0, of_node_full_name(node)); -+ if (IS_ERR(reg)) -+ return; -+ -+ div = kzalloc(sizeof(*div), GFP_KERNEL); -+ if (!div) -+ goto err_unmap; -+ -+ gate = kzalloc(sizeof(*gate), GFP_KERNEL); -+ if (!gate) -+ goto err_free_div; -+ -+ of_property_read_string(node, "clock-output-names", &clk_name); -+ parent = of_clk_get_parent_name(node, 0); -+ -+ gate->reg = reg; -+ gate->bit_idx = SUN4I_VE_ENABLE; -+ gate->lock = &ve_lock; -+ -+ div->reg = reg; -+ div->shift = SUN4I_VE_DIVIDER_SHIFT; -+ div->width = SUN4I_VE_DIVIDER_WIDTH; -+ div->lock = &ve_lock; -+ -+ clk = clk_register_composite(NULL, clk_name, &parent, 1, -+ NULL, NULL, -+ &div->hw, &clk_divider_ops, -+ &gate->hw, &clk_gate_ops, -+ CLK_SET_RATE_PARENT); -+ if (IS_ERR(clk)) -+ goto err_free_gate; -+ -+ err = of_clk_add_provider(node, of_clk_src_simple_get, clk); -+ if (err) -+ goto err_unregister_clk; -+ -+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); -+ if (!reset_data) -+ goto err_del_provider; -+ -+ reset_data->reg = reg; -+ reset_data->lock = &ve_lock; -+ reset_data->rcdev.nr_resets = 1; -+ reset_data->rcdev.ops = &sunxi_ve_reset_ops; -+ reset_data->rcdev.of_node = node; -+ reset_data->rcdev.of_xlate = sunxi_ve_of_xlate; -+ reset_data->rcdev.of_reset_n_cells = 0; -+ err = reset_controller_register(&reset_data->rcdev); -+ if (err) -+ goto err_free_reset; -+ -+ return; -+ -+err_free_reset: -+ kfree(reset_data); -+err_del_provider: -+ of_clk_del_provider(node); -+err_unregister_clk: -+ clk_unregister(clk); -+err_free_gate: -+ kfree(gate); -+err_free_div: -+ kfree(div); -+err_unmap: -+ iounmap(reg); -+} -+CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk", -+ sun4i_ve_clk_setup); -- cgit v1.2.3