From a87272ebfbcce8fd76329a8121486ae46af03a87 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 11 Dec 2015 15:03:27 +0000 Subject: ramips: enable CPS for mt7621 Enables CPS multiprocessing instead ob obsoleted CMP for mt7621. This patch fixes a few issues currently existing on 4.3 kernel with at least ubnt-erx: * iperf shows only 50Mbits on direct gigabit connection to desktop, * ping times jump to 5-6ms to dorectly connected desktop * /proc/interrupts shows spurious interrups (ERR) Signed-off-by: Nikolay Martynov SVN-Revision: 47842 --- .../0001-arch-mips-ralink-add-mt7621-support.patch | 134 +++------------------ 1 file changed, 14 insertions(+), 120 deletions(-) (limited to 'target/linux/ramips/patches-4.3') diff --git a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch index 67d816caf9..153dd9ed51 100644 --- a/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch +++ b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch @@ -120,7 +120,7 @@ Signed-off-by: John Crispin choice prompt "Ralink SoC selection" default SOC_RT305X -@@ -34,6 +39,15 @@ choice +@@ -34,6 +39,14 @@ choice config SOC_MT7620 bool "MT7620/8" @@ -129,14 +129,13 @@ Signed-off-by: John Crispin + select MIPS_CPU_SCACHE + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMP -+ select SYS_SUPPORTS_MIPS_CMP ++ select SYS_SUPPORTS_MIPS_CPS + select MIPS_GIC -+ select IRQ_GIC + select HW_HAS_PCI endchoice choice -@@ -65,6 +79,10 @@ choice +@@ -65,6 +78,10 @@ choice depends on SOC_MT7620 select BUILTIN_DTB @@ -149,7 +148,7 @@ Signed-off-by: John Crispin endif --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile -@@ -6,16 +6,21 @@ +@@ -6,16 +6,20 @@ # Copyright (C) 2009-2011 Gabor Juhos # Copyright (C) 2013 John Crispin @@ -161,8 +160,7 @@ Signed-off-by: John Crispin obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o +obj-$(CONFIG_IRQ_INTC) += irq.o -+obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o -+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o ++obj-$(CONFIG_MIPS_GIC) += irq-gic.o + obj-$(CONFIG_SOC_RT288X) += rt288x.o obj-$(CONFIG_SOC_RT305X) += rt305x.o @@ -185,136 +183,28 @@ Signed-off-by: John Crispin +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621 --- /dev/null +++ b/arch/mips/ralink/irq-gic.c -@@ -0,0 +1,42 @@ +@@ -0,0 +1,18 @@ +#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include + -+#include -+#include ++#include ++#include + -+#include +#include + -+#include -+ -+extern int __init gic_of_init(struct device_node *node, -+ struct device_node *parent); -+ +unsigned int get_c0_compare_int(void) +{ + return gic_get_c0_compare_int(); +} + -+static struct of_device_id __initdata of_irq_ids[] = { -+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, -+ { .compatible = "mti,gic", .data = gic_of_init }, -+ {}, -+}; -+ +void __init +arch_init_irq(void) +{ -+ of_irq_init(of_irq_ids); ++ irqchip_init(); +} ---- /dev/null -+++ b/arch/mips/ralink/malta-amon.c -@@ -0,0 +1,81 @@ -+/* -+ * Copyright (C) 2007 MIPS Technologies, Inc. -+ * All rights reserved. -+ -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * Arbitrary Monitor interface -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+int amon_cpu_avail(int cpu) -+{ -+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + -+ if (cpu < 0 || cpu >= NCPULAUNCH) { -+ pr_debug("avail: cpu%d is out of range\n", cpu); -+ return 0; -+ } -+ -+ launch += cpu; -+ if (!(launch->flags & LAUNCH_FREADY)) { -+ pr_debug("avail: cpu%d is not ready\n", cpu); -+ return 0; -+ } -+ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { -+ pr_debug("avail: too late.. cpu%d is already gone\n", cpu); -+ return 0; -+ } -+ -+ return 1; -+} -+ -+void amon_cpu_start(int cpu, -+ unsigned long pc, unsigned long sp, -+ unsigned long gp, unsigned long a0) -+{ -+ volatile struct cpulaunch *launch = -+ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); -+ -+ if (!amon_cpu_avail(cpu)) -+ return; -+ if (cpu == smp_processor_id()) { -+ pr_debug("launch: I am cpu%d!\n", cpu); -+ return; -+ } -+ launch += cpu; -+ -+ pr_debug("launch: starting cpu%d\n", cpu); -+ -+ launch->pc = pc; -+ launch->gp = gp; -+ launch->sp = sp; -+ launch->a0 = a0; -+ -+ smp_wmb(); /* Target must see parameters before go */ -+ launch->flags |= LAUNCH_FGO; -+ smp_wmb(); /* Target must see go before we poll */ -+ -+ while ((launch->flags & LAUNCH_FGONE) == 0) -+ ; -+ smp_rmb(); /* Target will be updating flags soon */ -+ pr_debug("launch: cpu%d gone!\n", cpu); -+} --- /dev/null +++ b/arch/mips/ralink/mt7621.c -@@ -0,0 +1,209 @@ +@@ -0,0 +1,213 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published @@ -432,6 +322,10 @@ Signed-off-by: John Crispin + { 0 } +}; + ++phys_addr_t mips_cpc_default_phys_base() { ++ panic("Cannot detect cpc address"); ++} ++ +void __init ralink_clk_init(void) +{ + int cpu_fdiv = 0; -- cgit v1.2.3