From b021642cacd1b88836e5906bb2d3397b1de16da9 Mon Sep 17 00:00:00 2001 From: Ilya Lipnitskiy Date: Sat, 27 Feb 2021 23:17:47 -0800 Subject: ramips: 5.10: refresh configs Run-tested on Ubiquiti EdgeRouter X. Compile tested on all other subtargets. Signed-off-by: Ilya Lipnitskiy --- target/linux/ramips/mt76x8/config-5.10 | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'target/linux/ramips/mt76x8') diff --git a/target/linux/ramips/mt76x8/config-5.10 b/target/linux/ramips/mt76x8/config-5.10 index b85d9fc9df..7829174319 100644 --- a/target/linux/ramips/mt76x8/config-5.10 +++ b/target/linux/ramips/mt76x8/config-5.10 @@ -1,5 +1,4 @@ CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MMAP_RND_BITS_MAX=15 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 @@ -17,11 +16,10 @@ CONFIG_CMDLINE_BOOL=y # CONFIG_CMDLINE_OVERRIDE is not set CONFIG_COMPAT_32BIT_TIME=y CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_DIEI=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_HAS_RIXI=y CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y @@ -37,7 +35,6 @@ CONFIG_CRYPTO_RNG2=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_PINCTRL=y CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y # CONFIG_DTB_MT7620A_EVAL is not set # CONFIG_DTB_OMEGA2P is not set CONFIG_DTB_RT_NONE=y @@ -87,7 +84,9 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_INTC=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y +# CONFIG_KERNEL_ZSTD is not set CONFIG_LIBFDT=y +CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y @@ -105,6 +104,7 @@ CONFIG_MIPS_CLOCK_VSYSCALL=y CONFIG_MIPS_CMDLINE_FROM_DTB=y # CONFIG_MIPS_ELF_APPENDED_DTB is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_LD_CAN_LINK_VDSO=y # CONFIG_MIPS_NO_APPENDED_DTB is not set CONFIG_MIPS_RAW_APPENDED_DTB=y CONFIG_MIPS_SPRAM=y -- cgit v1.2.3