From 7af3296c76f4e3f7f564a4b195f283841e0978d9 Mon Sep 17 00:00:00 2001
From: John Crispin <john@openwrt.org>
Date: Sat, 22 Dec 2007 00:17:22 +0000
Subject: change danube 2 ifxmips
SVN-Revision: 9821
---
target/linux/ifxmips/config-2.6.23 | 23 +-
.../linux/ifxmips/files/arch/mips/danube/Kconfig | 14 +-
.../linux/ifxmips/files/arch/mips/danube/Makefile | 2 +-
.../ifxmips/files/arch/mips/danube/dma-core.c | 206 +-
.../ifxmips/files/arch/mips/danube/interrupt.c | 24 +-
target/linux/ifxmips/files/arch/mips/danube/pci.c | 78 +-
target/linux/ifxmips/files/arch/mips/danube/pmu.c | 6 +-
target/linux/ifxmips/files/arch/mips/danube/prom.c | 10 +-
.../linux/ifxmips/files/arch/mips/danube/reset.c | 2 +-
.../linux/ifxmips/files/arch/mips/danube/setup.c | 22 +-
.../linux/ifxmips/files/drivers/char/danube_gpio.c | 130 +-
.../linux/ifxmips/files/drivers/char/danube_led.c | 52 +-
.../linux/ifxmips/files/drivers/char/danube_ssc.c | 26 +-
.../files/drivers/char/watchdog/danube_wdt.c | 96 +-
.../linux/ifxmips/files/drivers/mtd/maps/danube.c | 18 +-
.../linux/ifxmips/files/drivers/net/danube_mii0.c | 32 +-
.../ifxmips/files/drivers/serial/danube_asc.c | 126 +-
.../ifxmips/files/include/asm-mips/danube/danube.h | 236 +-
.../files/include/asm-mips/danube/danube_dma.h | 16 +-
.../files/include/asm-mips/danube/danube_gpio.h | 4 +-
.../files/include/asm-mips/danube/danube_ioctl.h | 24 +-
.../files/include/asm-mips/danube/danube_irq.h | 58 +-
.../files/include/asm-mips/danube/danube_mii0.h | 8 +-
.../files/include/asm-mips/danube/danube_orig.h | 2364 ++++++++++----------
.../files/include/asm-mips/danube/danube_pmu.h | 14 +-
.../files/include/asm-mips/danube/danube_serial.h | 36 +-
.../files/include/asm-mips/danube/danube_wdt.h | 42 +-
.../files/include/asm-mips/mach-danube/irq.h | 4 +-
target/linux/ifxmips/patches/100-board.patch | 14 +-
target/linux/ifxmips/patches/110-drivers.patch | 28 +-
target/linux/ifxmips/patches/160-cfi-swap.patch | 2 +-
31 files changed, 1859 insertions(+), 1858 deletions(-)
(limited to 'target/linux/ifxmips')
diff --git a/target/linux/ifxmips/config-2.6.23 b/target/linux/ifxmips/config-2.6.23
index 887519324f..b0e0bb8af5 100644
--- a/target/linux/ifxmips/config-2.6.23
+++ b/target/linux/ifxmips/config-2.6.23
@@ -39,15 +39,6 @@ CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CRYPTO_HW is not set
-CONFIG_DANUBE=y
-CONFIG_DANUBE_ASC_UART=y
-CONFIG_DANUBE_EEPROM=y
-CONFIG_DANUBE_GPIO=y
-CONFIG_DANUBE_LED=y
-CONFIG_DANUBE_MII0=y
-CONFIG_DANUBE_MII1=y
-CONFIG_DANUBE_SSC=y
-CONFIG_DANUBE_WDT=y
CONFIG_DEVPORT=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
@@ -65,9 +56,19 @@ CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
# CONFIG_I2C is not set
# CONFIG_IDE is not set
+CONFIG_IFXMIPS=y
+CONFIG_IFXMIPS_ASC_UART=y
+CONFIG_IFXMIPS_EEPROM=y
+CONFIG_IFXMIPS_GPIO=y
+CONFIG_IFXMIPS_LED=y
+# CONFIG_IFXMIPS_MII0 is not set
+# CONFIG_IFXMIPS_MII1 is not set
+CONFIG_IFXMIPS_SSC=y
+CONFIG_IFXMIPS_WDT=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
CONFIG_KALLSYMS=y
+# CONFIG_LEDS_ALIX is not set
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
@@ -106,12 +107,12 @@ CONFIG_MTD_CHAR=y
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_DANUBE=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_IFXMIPS=y
# CONFIG_MTD_JEDECPROBE is not set
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
@@ -153,7 +154,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_DANUBE=y
+# CONFIG_SERIAL_IFXMIPS is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Kconfig b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
index 1c5ad72ca5..03b53b8e44 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Kconfig
+++ b/target/linux/ifxmips/files/arch/mips/danube/Kconfig
@@ -2,33 +2,33 @@
menu "Danube built-in"
-config DANUBE_ASC_UART
+config IFXMIPS_ASC_UART
bool "Danube asc uart"
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
default y
-config MTD_DANUBE
+config MTD_IFXMIPS
bool "Danube flash map"
default y
-config DANUBE_WDT
+config IFXMIPS_WDT
bool "Danube watchdog"
default y
-config DANUBE_LED
+config IFXMIPS_LED
bool "Danube led"
default y
-config DANUBE_GPIO
+config IFXMIPS_GPIO
bool "Danube gpio"
default y
-config DANUBE_SSC
+config IFXMIPS_SSC
bool "Danube ssc"
default y
-config DANUBE_EEPROM
+config IFXMIPS_EEPROM
bool "Danube eeprom"
default y
diff --git a/target/linux/ifxmips/files/arch/mips/danube/Makefile b/target/linux/ifxmips/files/arch/mips/danube/Makefile
index fed8f2f45e..0fc94ce117 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/Makefile
+++ b/target/linux/ifxmips/files/arch/mips/danube/Makefile
@@ -4,7 +4,7 @@
#
# Makefile for Infineon Danube
#
-obj-y := reset.o prom.o setup.o interrupt.o dma-core.o
+obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_KGDB) += kgdb_serial.o
diff --git a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
index 7d29dbdc02..11bc4be63f 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/dma-core.c
@@ -25,7 +25,7 @@
#include <asm/danube/danube_pmu.h>
/*25 descriptors for each dma channel,4096/8/20=25.xx*/
-#define DANUBE_DMA_DESCRIPTOR_OFFSET 25
+#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
@@ -44,26 +44,26 @@ char global_device_name[MAX_DMA_DEVICE_NUM][20] =
{ {"PPE"}, {"DEU"}, {"SPI"}, {"SDIO"}, {"MCTRL0"}, {"MCTRL1"} };
_dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
- {"PPE", DANUBE_DMA_RX, 0, DANUBE_DMA_CH0_INT, 0},
- {"PPE", DANUBE_DMA_TX, 0, DANUBE_DMA_CH1_INT, 0},
- {"PPE", DANUBE_DMA_RX, 1, DANUBE_DMA_CH2_INT, 1},
- {"PPE", DANUBE_DMA_TX, 1, DANUBE_DMA_CH3_INT, 1},
- {"PPE", DANUBE_DMA_RX, 2, DANUBE_DMA_CH4_INT, 2},
- {"PPE", DANUBE_DMA_TX, 2, DANUBE_DMA_CH5_INT, 2},
- {"PPE", DANUBE_DMA_RX, 3, DANUBE_DMA_CH6_INT, 3},
- {"PPE", DANUBE_DMA_TX, 3, DANUBE_DMA_CH7_INT, 3},
- {"DEU", DANUBE_DMA_RX, 0, DANUBE_DMA_CH8_INT, 0},
- {"DEU", DANUBE_DMA_TX, 0, DANUBE_DMA_CH9_INT, 0},
- {"DEU", DANUBE_DMA_RX, 1, DANUBE_DMA_CH10_INT, 1},
- {"DEU", DANUBE_DMA_TX, 1, DANUBE_DMA_CH11_INT, 1},
- {"SPI", DANUBE_DMA_RX, 0, DANUBE_DMA_CH12_INT, 0},
- {"SPI", DANUBE_DMA_TX, 0, DANUBE_DMA_CH13_INT, 0},
- {"SDIO", DANUBE_DMA_RX, 0, DANUBE_DMA_CH14_INT, 0},
- {"SDIO", DANUBE_DMA_TX, 0, DANUBE_DMA_CH15_INT, 0},
- {"MCTRL0", DANUBE_DMA_RX, 0, DANUBE_DMA_CH16_INT, 0},
- {"MCTRL0", DANUBE_DMA_TX, 0, DANUBE_DMA_CH17_INT, 0},
- {"MCTRL1", DANUBE_DMA_RX, 1, DANUBE_DMA_CH18_INT, 1},
- {"MCTRL1", DANUBE_DMA_TX, 1, DANUBE_DMA_CH19_INT, 1}
+ {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0},
+ {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0},
+ {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1},
+ {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1},
+ {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2},
+ {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2},
+ {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3},
+ {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3},
+ {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0},
+ {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0},
+ {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1},
+ {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1},
+ {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0},
+ {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0},
+ {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0},
+ {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0},
+ {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0},
+ {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0},
+ {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1},
+ {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1}
};
_dma_chan_map *chan_map = default_dma_map;
@@ -97,9 +97,9 @@ enable_ch_irq (_dma_channel_info *pCh)
int flag;
local_irq_save(flag);
- writel(chan_no, DANUBE_DMA_CS);
- writel(0x4a, DANUBE_DMA_CIE);
- writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(0x4a, IFXMIPS_DMA_CIE);
+ writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
enable_danube_irq(pCh->irq);
}
@@ -112,9 +112,9 @@ disable_ch_irq (_dma_channel_info *pCh)
local_irq_save(flag);
g_danube_dma_int_status &= ~(1 << chan_no);
- writel(chan_no, DANUBE_DMA_CS);
- writel(0, DANUBE_DMA_CIE);
- writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(0, IFXMIPS_DMA_CIE);
+ writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
local_irq_restore(flag);
mask_and_ack_danube_irq(pCh->irq);
}
@@ -126,9 +126,9 @@ open_chan (_dma_channel_info *pCh)
int chan_no = (int)(pCh - dma_chan);
local_irq_save(flag);
- writel(chan_no, DANUBE_DMA_CS);
- writel(readl(DANUBE_DMA_CCTRL) | 1, DANUBE_DMA_CCTRL);
- if(pCh->dir == DANUBE_DMA_RX)
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(readl(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
+ if(pCh->dir == IFXMIPS_DMA_RX)
enable_ch_irq(pCh);
local_irq_restore(flag);
}
@@ -140,8 +140,8 @@ close_chan(_dma_channel_info *pCh)
int chan_no = (int) (pCh - dma_chan);
local_irq_save(flag);
- writel(chan_no, DANUBE_DMA_CS);
- writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
disable_ch_irq(pCh);
local_irq_restore(flag);
}
@@ -151,8 +151,8 @@ reset_chan (_dma_channel_info *pCh)
{
int chan_no = (int) (pCh - dma_chan);
- writel(chan_no, DANUBE_DMA_CS);
- writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
}
void
@@ -176,10 +176,10 @@ rx_chan_intr_handler (int chan_no)
pCh->weight--;
} else {
local_irq_save(flag);
- tmp = readl(DANUBE_DMA_CS);
- writel(chan_no, DANUBE_DMA_CS);
- writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
- writel(tmp, DANUBE_DMA_CS);
+ tmp = readl(IFXMIPS_DMA_CS);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+ writel(tmp, IFXMIPS_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
@@ -195,10 +195,10 @@ tx_chan_intr_handler (int chan_no)
int flag;
local_irq_save(flag);
- tmp = readl(DANUBE_DMA_CS);
- writel(chan_no, DANUBE_DMA_CS);
- writel(readl(DANUBE_DMA_CIS) | 0x7e, DANUBE_DMA_CIS);
- writel(tmp, DANUBE_DMA_CS);
+ tmp = readl(IFXMIPS_DMA_CS);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+ writel(tmp, IFXMIPS_DMA_CS);
g_danube_dma_int_status &= ~(1 << chan_no);
local_irq_restore(flag);
pDev->current_tx_chan = pCh->rel_chan_no;
@@ -238,7 +238,7 @@ do_dma_tasklet (unsigned long unused)
if (chan_no >= 0)
{
- if (chan_map[chan_no].dir == DANUBE_DMA_RX)
+ if (chan_map[chan_no].dir == IFXMIPS_DMA_RX)
rx_chan_intr_handler(chan_no);
else
tx_chan_intr_handler(chan_no);
@@ -272,10 +272,10 @@ dma_interrupt (int irq, void *dev_id)
if (chan_no < 0 || chan_no > 19)
BUG();
- tmp = readl(DANUBE_DMA_IRNEN);
- writel(0, DANUBE_DMA_IRNEN);
+ tmp = readl(IFXMIPS_DMA_IRNEN);
+ writel(0, IFXMIPS_DMA_IRNEN);
g_danube_dma_int_status |= 1 << chan_no;
- writel(tmp, DANUBE_DMA_IRNEN);
+ writel(tmp, IFXMIPS_DMA_IRNEN);
mask_and_ack_danube_irq(irq);
if (!g_danube_dma_in_process)
@@ -328,7 +328,7 @@ dma_device_register(_dma_device_info *dev)
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
- if (pCh->control == DANUBE_DMA_CH_ON)
+ if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
for (j = 0; j < pCh->desc_len; j++)
@@ -337,16 +337,16 @@ dma_device_register(_dma_device_info *dev)
memset(tx_desc_p, 0, sizeof(struct tx_desc));
}
local_irq_save(flag);
- writel(chan_no, DANUBE_DMA_CS);
+ writel(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
- if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
- writel(pCh->desc_len, DANUBE_DMA_CDLEN);
-
- writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
- writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
- while (readl(DANUBE_DMA_CCTRL) & 2){};
- writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
- writel(0x30100, DANUBE_DMA_CCTRL); /*reset and enable channel,enable channel later */
+ if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+ writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+ writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+ while (readl(IFXMIPS_DMA_CCTRL) & 2){};
+ writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+ writel(0x30100, IFXMIPS_DMA_CCTRL); /*reset and enable channel,enable channel later */
local_irq_restore(flag);
}
}
@@ -354,7 +354,7 @@ dma_device_register(_dma_device_info *dev)
for (i = 0; i < dev->max_rx_chan_num; i++)
{
pCh = dev->rx_chan[i];
- if (pCh->control == DANUBE_DMA_CH_ON)
+ if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(pCh - dma_chan);
@@ -376,16 +376,16 @@ dma_device_register(_dma_device_info *dev)
}
local_irq_save(flag);
- writel(chan_no, DANUBE_DMA_CS);
+ writel(chan_no, IFXMIPS_DMA_CS);
/*check if the descriptor length is changed */
- if (readl(DANUBE_DMA_CDLEN) != pCh->desc_len)
- writel(pCh->desc_len, DANUBE_DMA_CDLEN);
- writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
- writel(readl(DANUBE_DMA_CCTRL) | 2, DANUBE_DMA_CCTRL);
- while (readl(DANUBE_DMA_CCTRL) & 2){};
- writel(0x0a, DANUBE_DMA_CIE); /*fix me, should enable all the interrupts here? */
- writel(readl(DANUBE_DMA_IRNEN) | (1 << chan_no), DANUBE_DMA_IRNEN);
- writel(0x30000, DANUBE_DMA_CCTRL);
+ if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+ writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+ writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+ while (readl(IFXMIPS_DMA_CCTRL) & 2){};
+ writel(0x0a, IFXMIPS_DMA_CIE); /*fix me, should enable all the interrupts here? */
+ writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+ writel(0x30000, IFXMIPS_DMA_CCTRL);
local_irq_restore(flag);
enable_danube_irq(dma_chan[chan_no].irq);
}
@@ -405,18 +405,18 @@ dma_device_unregister (_dma_device_info *dev)
for (i = 0; i < dev->max_tx_chan_num; i++)
{
pCh = dev->tx_chan[i];
- if (pCh->control == DANUBE_DMA_CH_ON)
+ if (pCh->control == IFXMIPS_DMA_CH_ON)
{
chan_no = (int)(dev->tx_chan[i] - dma_chan);
local_irq_save (flag);
- writel(chan_no, DANUBE_DMA_CS);
+ writel(chan_no, IFXMIPS_DMA_CS);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
- pCh->control = DANUBE_DMA_CH_OFF;
- writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
- writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
- writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
- while (readl(DANUBE_DMA_CCTRL) & 1) {};
+ pCh->control = IFXMIPS_DMA_CH_OFF;
+ writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
+ writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+ while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@@ -444,13 +444,13 @@ dma_device_unregister (_dma_device_info *dev)
g_danube_dma_int_status &= ~(1 << chan_no);
pCh->curr_desc = 0;
pCh->prev_desc = 0;
- pCh->control = DANUBE_DMA_CH_OFF;
+ pCh->control = IFXMIPS_DMA_CH_OFF;
- writel(chan_no, DANUBE_DMA_CS);
- writel(0, DANUBE_DMA_CIE); /*fix me, should disable all the interrupts here? */
- writel(readl(DANUBE_DMA_IRNEN) & ~(1 << chan_no), DANUBE_DMA_IRNEN); /*disable interrupts */
- writel(readl(DANUBE_DMA_CCTRL) & ~1, DANUBE_DMA_CCTRL);
- while (readl(DANUBE_DMA_CCTRL) & 1) {};
+ writel(chan_no, IFXMIPS_DMA_CS);
+ writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
+ writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /*disable interrupts */
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+ while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
local_irq_restore (flag);
for (j = 0; j < pCh->desc_len; j++)
@@ -577,8 +577,8 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *
dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
}
- writel(chan_no, DANUBE_DMA_CS);
- tmp = readl(DANUBE_DMA_CCTRL);
+ writel(chan_no, IFXMIPS_DMA_CS);
+ tmp = readl(IFXMIPS_DMA_CCTRL);
if (!(tmp & 1))
pCh->open (pCh);
@@ -625,14 +625,14 @@ map_dma_chan(_dma_chan_map *map)
dma_devs[i].rx_burst_len = 4;
if (i == 0)
{
- writel(0, DANUBE_DMA_PS);
- writel(readl(DANUBE_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), DANUBE_DMA_PCTRL); /*enable dma drop */
+ writel(0, IFXMIPS_DMA_PS);
+ writel(readl(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */
}
if (i == 1)
{
- writel(1, DANUBE_DMA_PS);
- writel(0x14, DANUBE_DMA_PCTRL); /*deu port setting */
+ writel(1, IFXMIPS_DMA_PS);
+ writel(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */
}
for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
@@ -644,8 +644,8 @@ map_dma_chan(_dma_chan_map *map)
dma_chan[j].enable_irq = &enable_ch_irq;
dma_chan[j].disable_irq = &disable_ch_irq;
dma_chan[j].rel_chan_no = map[j].rel_chan_no;
- dma_chan[j].control = DANUBE_DMA_CH_OFF;
- dma_chan[j].default_weight = DANUBE_DMA_CH_DEFAULT_WEIGHT;
+ dma_chan[j].control = IFXMIPS_DMA_CH_OFF;
+ dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT;
dma_chan[j].weight = dma_chan[j].default_weight;
dma_chan[j].curr_desc = 0;
dma_chan[j].prev_desc = 0;
@@ -655,16 +655,16 @@ map_dma_chan(_dma_chan_map *map)
{
if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0)
{
- if (map[j].dir == DANUBE_DMA_RX)
+ if (map[j].dir == IFXMIPS_DMA_RX)
{
- dma_chan[j].dir = DANUBE_DMA_RX;
+ dma_chan[j].dir = IFXMIPS_DMA_RX;
dma_devs[i].max_rx_chan_num++;
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
dma_chan[j].dma_dev = (void*)&dma_devs[i];
- } else if(map[j].dir == DANUBE_DMA_TX)
+ } else if(map[j].dir == IFXMIPS_DMA_TX)
{ /*TX direction */
- dma_chan[j].dir = DANUBE_DMA_TX;
+ dma_chan[j].dir = IFXMIPS_DMA_TX;
dma_devs[i].max_tx_chan_num++;
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
@@ -685,20 +685,20 @@ dma_chip_init(void)
int i;
// enable DMA from PMU
- danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
// reset DMA
- writel(readl(DANUBE_DMA_CTRL) | 1, DANUBE_DMA_CTRL);
+ writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
// diable all interrupts
- writel(0, DANUBE_DMA_IRNEN);
+ writel(0, IFXMIPS_DMA_IRNEN);
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
- writel(i, DANUBE_DMA_CS);
- writel(0x2, DANUBE_DMA_CCTRL);
- writel(0x80000040, DANUBE_DMA_CPOLL);
- writel(readl(DANUBE_DMA_CCTRL) & ~0x1, DANUBE_DMA_CCTRL);
+ writel(i, IFXMIPS_DMA_CS);
+ writel(0x2, IFXMIPS_DMA_CCTRL);
+ writel(0x80000040, IFXMIPS_DMA_CPOLL);
+ writel(readl(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
}
}
@@ -724,13 +724,13 @@ danube_dma_init (void)
for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
{
- dma_chan[i].desc_base = (u32)g_desc_list + i * DANUBE_DMA_DESCRIPTOR_OFFSET * 8;
+ dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8;
dma_chan[i].curr_desc = 0;
- dma_chan[i].desc_len = DANUBE_DMA_DESCRIPTOR_OFFSET;
+ dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
- writel(i, DANUBE_DMA_CS);
- writel((u32)CPHYSADDR(dma_chan[i].desc_base), DANUBE_DMA_CDBA);
- writel(dma_chan[i].desc_len, DANUBE_DMA_CDLEN);
+ writel(i, IFXMIPS_DMA_CS);
+ writel((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
+ writel(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
}
return 0;
diff --git a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
index c266608ea2..1639800498 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/interrupt.c
@@ -42,7 +42,7 @@ void
disable_danube_irq (unsigned int irq_nr)
{
int i;
- u32 *danube_ier = DANUBE_ICU_IM0_IER;
+ u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@@ -51,7 +51,7 @@ disable_danube_irq (unsigned int irq_nr)
writel(readl(danube_ier) & ~(1 << irq_nr ), danube_ier);
return;
}
- danube_ier += DANUBE_ICU_OFFSET;
+ danube_ier += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@@ -61,8 +61,8 @@ void
mask_and_ack_danube_irq (unsigned int irq_nr)
{
int i;
- u32 *danube_ier = DANUBE_ICU_IM0_IER;
- u32 *danube_isr = DANUBE_ICU_IM0_ISR;
+ u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
+ u32 *danube_isr = IFXMIPS_ICU_IM0_ISR;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@@ -73,8 +73,8 @@ mask_and_ack_danube_irq (unsigned int irq_nr)
writel((1 << irq_nr ), danube_isr);
return;
}
- danube_ier += DANUBE_ICU_OFFSET;
- danube_isr += DANUBE_ICU_OFFSET;
+ danube_ier += IFXMIPS_ICU_OFFSET;
+ danube_isr += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@@ -84,7 +84,7 @@ void
enable_danube_irq (unsigned int irq_nr)
{
int i;
- u32 *danube_ier = DANUBE_ICU_IM0_IER;
+ u32 *danube_ier = IFXMIPS_ICU_IM0_IER;
irq_nr -= INT_NUM_IRQ0;
for (i = 0; i <= 4; i++)
@@ -94,7 +94,7 @@ enable_danube_irq (unsigned int irq_nr)
writel(readl(danube_ier) | (1 << irq_nr ), danube_ier);
return;
}
- danube_ier += DANUBE_ICU_OFFSET;
+ danube_ier += IFXMIPS_ICU_OFFSET;
irq_nr -= INT_NUM_IM_OFFSET;
}
}
@@ -115,7 +115,7 @@ end_danube_irq (unsigned int irq)
}
static struct hw_interrupt_type danube_irq_type = {
- "DANUBE",
+ "IFXMIPS",
.startup = startup_danube_irq,
.enable = enable_danube_irq,
.disable = disable_danube_irq,
@@ -145,7 +145,7 @@ danube_hw_irqdispatch (int module)
{
u32 irq;
- irq = readl(DANUBE_ICU_IM0_IOSR + (module * DANUBE_ICU_OFFSET));
+ irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
if (irq == 0)
return;
@@ -153,7 +153,7 @@ danube_hw_irqdispatch (int module)
do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
if ((irq == 22) && (module == 0)){
- writel(readl(DANUBE_EBU_PCC_ISTAT) | 0x10, DANUBE_EBU_PCC_ISTAT);
+ writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
}
}
@@ -195,7 +195,7 @@ arch_init_irq(void)
for (i = 0; i < 5; i++)
{
- writel(0, DANUBE_ICU_IM0_IER + (i * DANUBE_ICU_OFFSET));
+ writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
}
mips_cpu_irq_init();
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pci.c b/target/linux/ifxmips/files/arch/mips/danube/pci.c
index 1896336d81..81727805a4 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pci.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pci.c
@@ -9,14 +9,14 @@
#include <asm/addrspace.h>
#include <linux/vmalloc.h>
-#define DANUBE_PCI_MEM_BASE 0x18000000
-#define DANUBE_PCI_MEM_SIZE 0x02000000
-#define DANUBE_PCI_IO_BASE 0x1AE00000
-#define DANUBE_PCI_IO_SIZE 0x00200000
+#define IFXMIPS_PCI_MEM_BASE 0x18000000
+#define IFXMIPS_PCI_MEM_SIZE 0x02000000
+#define IFXMIPS_PCI_IO_BASE 0x1AE00000
+#define IFXMIPS_PCI_IO_SIZE 0x00200000
-#define DANUBE_PCI_CFG_BUSNUM_SHF 16
-#define DANUBE_PCI_CFG_DEVNUM_SHF 11
-#define DANUBE_PCI_CFG_FUNNUM_SHF 8
+#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
+#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
+#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
@@ -31,15 +31,15 @@ struct pci_ops danube_pci_ops = {
static struct resource pci_io_resource = {
.name = "io pci IO space",
- .start = DANUBE_PCI_IO_BASE,
- .end = DANUBE_PCI_IO_BASE + DANUBE_PCI_IO_SIZE - 1,
+ .start = IFXMIPS_PCI_IO_BASE,
+ .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource pci_mem_resource = {
.name = "ext pci memory space",
- .start = DANUBE_PCI_MEM_BASE,
- .end = DANUBE_PCI_MEM_BASE + DANUBE_PCI_MEM_SIZE - 1,
+ .start = IFXMIPS_PCI_MEM_BASE,
+ .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
@@ -71,32 +71,32 @@ danube_pci_config_access(unsigned char access_type,
local_irq_save(flags);
cfg_base = danube_pci_mapped_cfg;
- cfg_base |= (bus->number << DANUBE_PCI_CFG_BUSNUM_SHF) | (devfn <<
- DANUBE_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
+ cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
+ IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
/* Perform access */
if (access_type == PCI_ACCESS_WRITE)
{
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
writel(swab32(*data), ((u32*)cfg_base));
#else
writel(*data, ((u32*)cfg_base));
#endif
} else {
*data = readl(((u32*)(cfg_base)));
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
*data = swab32(*data);
#endif
}
wmb();
/* clean possible Master abort */
- cfg_base = (danube_pci_mapped_cfg | (0x0 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+ cfg_base = (danube_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
temp = readl(((u32*)(cfg_base)));
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
temp = swab32 (temp);
#endif
- cfg_base = (danube_pci_mapped_cfg | (0x68 << DANUBE_PCI_CFG_FUNNUM_SHF)) + 4;
+ cfg_base = (danube_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
writel(temp, ((u32*)cfg_base));
local_irq_restore(flags);
@@ -163,8 +163,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
case 1:
//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
- writel(readl(DANUBE_EBU_PCC_CON) | 0xc, DANUBE_EBU_PCC_CON);
- writel(readl(DANUBE_EBU_PCC_IEN) | 0x10, DANUBE_EBU_PCC_IEN);
+ writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
+ writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
break;
case 2:
case 3:
@@ -182,31 +182,31 @@ static void __init danube_pci_startup (void){
/*initialize the first PCI device--danube itself */
u32 temp_buffer;
/*TODO: trigger reset */
- writel(readl(DANUBE_CGU_IFCCR) & ~0xf00000, DANUBE_CGU_IFCCR);
- writel(readl(DANUBE_CGU_IFCCR) | 0x800000, DANUBE_CGU_IFCCR);
+ writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
+ writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
0 =>clock input
PADsel of PCI_CR of CGU : 1 =>From CGU
: 0 =>From pad
*/
- writel(readl(DANUBE_CGU_IFCCR) | (1 << 16), DANUBE_CGU_IFCCR);
- writel((1 << 31) | (1 << 30), DANUBE_CGU_PCICR);
+ writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
+ writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
/* prepare GPIO */
/* PCI_RST: P1.5 ALT 01 */
//pliu20060613: start
- writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
- writel(readl(DANUBE_GPIO_P1_OD) | (1 << 5), DANUBE_GPIO_P1_OD);
- writel(readl(DANUBE_GPIO_P1_DIR) | (1 << 5), DANUBE_GPIO_P1_DIR);
- writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL1);
- writel(readl(DANUBE_GPIO_P1_ALTSEL0) & ~(1 << 5), DANUBE_GPIO_P1_ALTSEL0);
+ writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+ writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
+ writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
+ writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
+ writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
//pliu20060613: end
/* PCI_REQ1: P1.13 ALT 01 */
/* PCI_GNT1: P1.14 ALT 01 */
- writel(readl(DANUBE_GPIO_P1_DIR) & ~0x2000, DANUBE_GPIO_P1_DIR);
- writel(readl(DANUBE_GPIO_P1_DIR) | 0x4000, DANUBE_GPIO_P1_DIR);
- writel(readl(DANUBE_GPIO_P1_ALTSEL1) & ~0x6000, DANUBE_GPIO_P1_ALTSEL1);
- writel(readl(DANUBE_GPIO_P1_ALTSEL0) | 0x6000, DANUBE_GPIO_P1_ALTSEL0);
+ writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
+ writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
+ writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
+ writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
/* PCI_REQ2: P1.15 ALT 10 */
/* PCI_GNT2: P1.7 ALT 10 */
@@ -260,9 +260,9 @@ static void __init danube_pci_startup (void){
writel(0x0e000008, PCI_CR_BAR11MASK);
writel(0, PCI_CR_PCI_ADDR_MAP11);
writel(0, PCI_CS_BASE_ADDR1);
-#ifdef CONFIG_DANUBE_PCI_HW_SWAP
+#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
/* both TX and RX endian swap are enabled */
- DANUBE_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
+ IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
wmb ();
#endif
/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
@@ -273,10 +273,10 @@ static void __init danube_pci_startup (void){
writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
wmb();
- writel(readl(DANUBE_GPIO_P1_OUT) & ~(1 << 5), DANUBE_GPIO_P1_OUT);
+ writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
wmb();
mdelay (1);
- writel(readl(DANUBE_GPIO_P1_OUT) | (1 << 5), DANUBE_GPIO_P1_OUT);
+ writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
@@ -303,11 +303,11 @@ int pcibios_init(void){
danube_pci_startup ();
- // DANUBE_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
+ // IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
- danube_pci_controller.io_map_base = (unsigned long)ioremap(DANUBE_PCI_IO_BASE, DANUBE_PCI_IO_SIZE - 1);
+ danube_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/pmu.c b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
index 5bb66dbe5b..b96cfdc570 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/pmu.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/pmu.c
@@ -29,8 +29,8 @@ danube_pmu_enable (unsigned int module)
{
int err = 1000000;
- writel(readl(DANUBE_PMU_PWDCR) & ~module, DANUBE_PMU_PWDCR);
- while (--err && (readl(DANUBE_PMU_PWDSR) & module)) {}
+ writel(readl(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
+ while (--err && (readl(IFXMIPS_PMU_PWDSR) & module)) {}
if (!err)
panic("activating PMU module failed!");
@@ -40,6 +40,6 @@ EXPORT_SYMBOL(danube_pmu_enable);
void
danube_pmu_disable (unsigned int module)
{
- writel(readl(DANUBE_PMU_PWDCR) | module, DANUBE_PMU_PWDCR);
+ writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
}
EXPORT_SYMBOL(danube_pmu_disable);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/prom.c b/target/linux/ifxmips/files/arch/mips/danube/prom.c
index efb06120ef..9933d419c7 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/prom.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/prom.c
@@ -45,11 +45,11 @@ get_system_type (void)
void
prom_putchar (char c)
{
- while ((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+ while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n')
- writel('\r', DANUBE_ASC1_TBUF);
- writel(c, DANUBE_ASC1_TBUF);
+ writel('\r', IFXMIPS_ASC1_TBUF);
+ writel(c, IFXMIPS_ASC1_TBUF);
}
void
@@ -73,8 +73,8 @@ prom_printf (const char * fmt, ...)
void __init
prom_init(void)
{
- mips_machgroup = MACH_GROUP_DANUBE;
- mips_machtype = MACH_INFINEON_DANUBE;
+ mips_machgroup = MACH_GROUP_IFXMIPS;
+ mips_machtype = MACH_INFINEON_IFXMIPS;
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
diff --git a/target/linux/ifxmips/files/arch/mips/danube/reset.c b/target/linux/ifxmips/files/arch/mips/danube/reset.c
index cb1793ca77..333c29d46e 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/reset.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/reset.c
@@ -37,7 +37,7 @@ danube_machine_restart (char *command)
printk (KERN_NOTICE "System restart\n");
local_irq_disable ();
- writel(readl(DANUBE_RCU_REQ) | DANUBE_RST_ALL, DANUBE_RCU_REQ);
+ writel(readl(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
for (;;);
}
diff --git a/target/linux/ifxmips/files/arch/mips/danube/setup.c b/target/linux/ifxmips/files/arch/mips/danube/setup.c
index 60b0ce28e7..0abc5d3eca 100644
--- a/target/linux/ifxmips/files/arch/mips/danube/setup.c
+++ b/target/linux/ifxmips/files/arch/mips/danube/setup.c
@@ -49,7 +49,7 @@ __init bus_error_init (void)
unsigned int
danube_get_ddr_hz (void)
{
- switch (readl(DANUBE_CGU_SYS) & 0x3)
+ switch (readl(IFXMIPS_CGU_SYS) & 0x3)
{
case 0:
return CLOCK_167M;
@@ -66,7 +66,7 @@ unsigned int
danube_get_cpu_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
- switch (readl(DANUBE_CGU_SYS) & 0xc)
+ switch (readl(IFXMIPS_CGU_SYS) & 0xc)
{
case 0:
return CLOCK_333M;
@@ -81,7 +81,7 @@ unsigned int
danube_get_fpi_hz (void)
{
unsigned int ddr_clock = danube_get_ddr_hz();
- if (readl(DANUBE_CGU_SYS) & 0x40)
+ if (readl(IFXMIPS_CGU_SYS) & 0x40)
{
return ddr_clock >> 1;
}
@@ -92,7 +92,7 @@ EXPORT_SYMBOL(danube_get_fpi_hz);
unsigned int
danube_get_cpu_ver (void)
{
- return readl(DANUBE_MCD_CHIPID) & 0xFFFFF000;
+ return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
}
EXPORT_SYMBOL(danube_get_cpu_ver);
@@ -118,7 +118,7 @@ danube_be_handler(struct pt_regs *regs, int is_fixup)
static irqreturn_t
danube_timer6_interrupt(int irq, void *dev_id)
{
- timer_interrupt(DANUBE_TIMER6_INT, NULL);
+ timer_interrupt(IFXMIPS_TIMER6_INT, NULL);
return IRQ_HANDLED;
}
@@ -139,18 +139,18 @@ plat_timer_setup (struct irqaction *irq)
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
- danube_pmu_enable(DANUBE_PMU_PWDCR_GPT | DANUBE_PMU_PWDCR_FPI);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
- writel(0x100, DANUBE_GPTU_GPT_CLC);
+ writel(0x100, IFXMIPS_GPTU_GPT_CLC);
- writel(0xffff, DANUBE_GPTU_GPT_CAPREL);
- writel(0x80C0, DANUBE_GPTU_GPT_T6CON);
+ writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
+ writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
- retval = setup_irq(DANUBE_TIMER6_INT, &hrt_irqaction);
+ retval = setup_irq(IFXMIPS_TIMER6_INT, &hrt_irqaction);
if (retval)
{
- prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", DANUBE_TIMER6_INT);
+ prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n", IFXMIPS_TIMER6_INT);
}
}
diff --git a/target/linux/ifxmips/files/drivers/char/danube_gpio.c b/target/linux/ifxmips/files/drivers/char/danube_gpio.c
index dbdb71e8fb..2a42665868 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_gpio.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_gpio.c
@@ -38,12 +38,12 @@ static unsigned int danube_gpio_major = 0;
static struct semaphore port_sem;
/* TODO do we really need this ? return in a define is forbidden by coding style */
-#define DANUBE_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
+#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; }
int
danube_port_reserve_pin (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@@ -53,7 +53,7 @@ EXPORT_SYMBOL(danube_port_reserve_pin);
int
danube_port_free_pin (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
printk("%s : call to obseleted function\n", __func__);
return 0;
@@ -63,8 +63,8 @@ EXPORT_SYMBOL(danube_port_free_pin);
int
danube_port_set_open_drain (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OD);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@@ -73,8 +73,8 @@ EXPORT_SYMBOL(danube_port_set_open_drain);
int
danube_port_clear_open_drain (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OD);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD);
return 0;
}
@@ -83,8 +83,8 @@ EXPORT_SYMBOL(danube_port_clear_open_drain);
int
danube_port_set_pudsel (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDSEL);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@@ -93,8 +93,8 @@ EXPORT_SYMBOL(danube_port_set_pudsel);
int
danube_port_clear_pudsel (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDSEL);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL);
return 0;
}
@@ -103,8 +103,8 @@ EXPORT_SYMBOL(danube_port_clear_pudsel);
int
danube_port_set_puden (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_PUDEN);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@@ -113,8 +113,8 @@ EXPORT_SYMBOL(danube_port_set_puden);
int
danube_port_clear_puden (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_PUDEN);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN);
return 0;
}
@@ -123,8 +123,8 @@ EXPORT_SYMBOL(danube_port_clear_puden);
int
danube_port_set_stoff (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_STOFF);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@@ -133,8 +133,8 @@ EXPORT_SYMBOL(danube_port_set_stoff);
int
danube_port_clear_stoff (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_STOFF);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF);
return 0;
}
@@ -143,8 +143,8 @@ EXPORT_SYMBOL(danube_port_clear_stoff);
int
danube_port_set_dir_out (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_DIR);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@@ -153,8 +153,8 @@ EXPORT_SYMBOL(danube_port_set_dir_out);
int
danube_port_set_dir_in (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_DIR);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR);
return 0;
}
@@ -163,8 +163,8 @@ EXPORT_SYMBOL(danube_port_set_dir_in);
int
danube_port_set_output (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_OUT);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@@ -173,8 +173,8 @@ EXPORT_SYMBOL(danube_port_set_output);
int
danube_port_clear_output (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_OUT);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT);
return 0;
}
@@ -183,9 +183,9 @@ EXPORT_SYMBOL(danube_port_clear_output);
int
danube_port_get_input (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
+ IFXMIPS_GPIO_SANITY;
- if (readl(DANUBE_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
+ if (readl(IFXMIPS_GPIO_P0_IN + (port * 0x30)) & (1 << pin))
return 0;
else
return 1;
@@ -195,8 +195,8 @@ EXPORT_SYMBOL(danube_port_get_input);
int
danube_port_set_altsel0 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@@ -205,8 +205,8 @@ EXPORT_SYMBOL(danube_port_set_altsel0);
int
danube_port_clear_altsel0 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL0);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0);
return 0;
}
@@ -215,8 +215,8 @@ EXPORT_SYMBOL(danube_port_clear_altsel0);
int
danube_port_set_altsel1 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@@ -225,8 +225,8 @@ EXPORT_SYMBOL(danube_port_set_altsel1);
int
danube_port_clear_altsel1 (unsigned int port, unsigned int pin)
{
- DANUBE_GPIO_SANITY;
- writel(readl(DANUBE_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), DANUBE_GPIO_P0_ALTSEL1);
+ IFXMIPS_GPIO_SANITY;
+ writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0x30)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1);
return 0;
}
@@ -264,24 +264,24 @@ danube_port_read_procmem (char *buf, char **start, off_t offset, int count,
len += sprintf (buf + len,
"----------------------------------------\n");
- len += danube_port_read_procmem_helper("P0-OUT", DANUBE_GPIO_P0_OUT, &buf[len]);
- len += danube_port_read_procmem_helper("P1-OUT", DANUBE_GPIO_P1_OUT, &buf[len]);
- len += danube_port_read_procmem_helper("P0-IN ", DANUBE_GPIO_P0_IN, &buf[len]);
- len += danube_port_read_procmem_helper("P1-IN ", DANUBE_GPIO_P1_IN, &buf[len]);
- len += danube_port_read_procmem_helper("P0-DIR", DANUBE_GPIO_P0_DIR, &buf[len]);
- len += danube_port_read_procmem_helper("P1-DIR", DANUBE_GPIO_P1_DIR, &buf[len]);
- len += danube_port_read_procmem_helper("P0-STO ", DANUBE_GPIO_P0_STOFF, &buf[len]);
- len += danube_port_read_procmem_helper("P1-STO ", DANUBE_GPIO_P1_STOFF, &buf[len]);
- len += danube_port_read_procmem_helper("P0-PUDE", DANUBE_GPIO_P0_PUDEN, &buf[len]);
- len += danube_port_read_procmem_helper("P1-PUDE", DANUBE_GPIO_P1_PUDEN, &buf[len]);
- len += danube_port_read_procmem_helper("P0-OD ", DANUBE_GPIO_P0_OD, &buf[len]);
- len += danube_port_read_procmem_helper("P1-OD ", DANUBE_GPIO_P1_OD, &buf[len]);
- len += danube_port_read_procmem_helper("P0-PUDS", DANUBE_GPIO_P0_PUDSEL, &buf[len]);
- len += danube_port_read_procmem_helper("P1-PUDS", DANUBE_GPIO_P1_PUDSEL, &buf[len]);
- len += danube_port_read_procmem_helper("P0-ALT0", DANUBE_GPIO_P0_ALTSEL0, &buf[len]);
- len += danube_port_read_procmem_helper("P1-ALT0", DANUBE_GPIO_P1_ALTSEL0, &buf[len]);
- len += danube_port_read_procmem_helper("P0-ALT1", DANUBE_GPIO_P0_ALTSEL1, &buf[len]);
- len += danube_port_read_procmem_helper("P1-ALT1", DANUBE_GPIO_P1_ALTSEL1, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-OUT", IFXMIPS_GPIO_P0_OUT, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-OUT", IFXMIPS_GPIO_P1_OUT, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-IN ", IFXMIPS_GPIO_P0_IN, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-IN ", IFXMIPS_GPIO_P1_IN, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-DIR", IFXMIPS_GPIO_P0_DIR, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-DIR", IFXMIPS_GPIO_P1_DIR, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-STO ", IFXMIPS_GPIO_P0_STOFF, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-STO ", IFXMIPS_GPIO_P1_STOFF, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-PUDE", IFXMIPS_GPIO_P0_PUDEN, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-PUDE", IFXMIPS_GPIO_P1_PUDEN, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-OD ", IFXMIPS_GPIO_P0_OD, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-OD ", IFXMIPS_GPIO_P1_OD, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-PUDS", IFXMIPS_GPIO_P0_PUDSEL, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-PUDS", IFXMIPS_GPIO_P1_PUDSEL, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-ALT0", IFXMIPS_GPIO_P0_ALTSEL0, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-ALT0", IFXMIPS_GPIO_P1_ALTSEL0, &buf[len]);
+ len += danube_port_read_procmem_helper("P0-ALT1", IFXMIPS_GPIO_P0_ALTSEL1, &buf[len]);
+ len += danube_port_read_procmem_helper("P1-ALT1", IFXMIPS_GPIO_P1_ALTSEL1, &buf[len]);
len = len + sprintf (buf + len, "\n\n");
*eof = 1;
@@ -308,7 +308,7 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
int ret = 0;
volatile struct danube_port_ioctl_parm parm;
- if (_IOC_TYPE (cmd) != DANUBE_PORT_IOC_MAGIC)
+ if (_IOC_TYPE (cmd) != IFXMIPS_PORT_IOC_MAGIC)
return -EINVAL;
if (_IOC_DIR (cmd) & _IOC_WRITE) {
@@ -330,63 +330,63 @@ danube_port_ioctl (struct inode *inode, struct file *filp,
return -EBUSY;
switch (cmd) {
- case DANUBE_PORT_IOCOD:
+ case IFXMIPS_PORT_IOCOD:
if (parm.value == 0x00)
danube_port_clear_open_drain(parm.port, parm.pin);
else
danube_port_set_open_drain(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCPUDSEL:
+ case IFXMIPS_PORT_IOCPUDSEL:
if (parm.value == 0x00)
danube_port_clear_pudsel(parm.port, parm.pin);
else
danube_port_set_pudsel(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCPUDEN:
+ case IFXMIPS_PORT_IOCPUDEN:
if (parm.value == 0x00)
danube_port_clear_puden(parm.port, parm.pin);
else
danube_port_set_puden(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCSTOFF:
+ case IFXMIPS_PORT_IOCSTOFF:
if (parm.value == 0x00)
danube_port_clear_stoff(parm.port, parm.pin);
else
danube_port_set_stoff(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCDIR:
+ case IFXMIPS_PORT_IOCDIR:
if (parm.value == 0x00)
danube_port_set_dir_in(parm.port, parm.pin);
else
danube_port_set_dir_out(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCOUTPUT:
+ case IFXMIPS_PORT_IOCOUTPUT:
if (parm.value == 0x00)
danube_port_clear_output(parm.port, parm.pin);
else
danube_port_set_output(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCALTSEL0:
+ case IFXMIPS_PORT_IOCALTSEL0:
if (parm.value == 0x00)
danube_port_clear_altsel0(parm.port, parm.pin);
else
danube_port_set_altsel0(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCALTSEL1:
+ case IFXMIPS_PORT_IOCALTSEL1:
if (parm.value == 0x00)
danube_port_clear_altsel1(parm.port, parm.pin);
else
danube_port_set_altsel1(parm.port, parm.pin);
break;
- case DANUBE_PORT_IOCINPUT:
+ case IFXMIPS_PORT_IOCINPUT:
parm.value = danube_port_get_input(parm.port, parm.pin);
copy_to_user((void*)arg, (void*)&parm,
sizeof(struct danube_port_ioctl_parm));
diff --git a/target/linux/ifxmips/files/drivers/char/danube_led.c b/target/linux/ifxmips/files/drivers/char/danube_led.c
index 86a92d5999..f1483cc108 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_led.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_led.c
@@ -31,12 +31,12 @@
#include <asm/danube/danube_gpio.h>
#include <asm/danube/danube_pmu.h>
-#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
-//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
+#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
+//#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING
-#define DANUBE_LED_SPEED DANUBE_LED_8HZ
+#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ
-#define DANUBE_LED_GPIO_PORT 0
+#define IFXMIPS_LED_GPIO_PORT 0
static int danube_led_major;
@@ -44,7 +44,7 @@ void
danube_led_set (unsigned int led)
{
led &= 0xffffff;
- writel(readl(DANUBE_LED_CPU0) | led, DANUBE_LED_CPU0);
+ writel(readl(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_set);
@@ -52,7 +52,7 @@ void
danube_led_clear (unsigned int led)
{
led = ~(led & 0xffffff);
- writel(readl(DANUBE_LED_CPU0) & led, DANUBE_LED_CPU0);
+ writel(readl(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
}
EXPORT_SYMBOL(danube_led_clear);
@@ -60,7 +60,7 @@ void
danube_led_blink_set (unsigned int led)
{
led &= 0xffffff;
- writel(readl(DANUBE_LED_CON0) | led, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_set);
@@ -68,7 +68,7 @@ void
danube_led_blink_clear (unsigned int led)
{
led = ~(led & 0xffffff);
- writel(readl(DANUBE_LED_CON0) & led, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
}
EXPORT_SYMBOL(danube_led_blink_clear);
@@ -80,10 +80,10 @@ danube_led_setup_gpio (void)
/* we need to setup pins SH,D,ST (4,5,6) */
for (i = 4; i < 7; i++)
{
- danube_port_set_altsel0(DANUBE_LED_GPIO_PORT, i);
- danube_port_clear_altsel1(DANUBE_LED_GPIO_PORT, i);
- danube_port_set_dir_out(DANUBE_LED_GPIO_PORT, i);
- danube_port_set_open_drain(DANUBE_LED_GPIO_PORT, i);
+ danube_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i);
+ danube_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i);
}
}
@@ -144,32 +144,32 @@ danube_led_init (void)
danube_led_setup_gpio();
- writel(0, DANUBE_LED_AR);
- writel(0, DANUBE_LED_CPU0);
- writel(0, DANUBE_LED_CPU1);
- writel(LED_CON0_SWU, DANUBE_LED_CON0);
- writel(0, DANUBE_LED_CON1);
+ writel(0, IFXMIPS_LED_AR);
+ writel(0, IFXMIPS_LED_CPU0);
+ writel(0, IFXMIPS_LED_CPU1);
+ writel(LED_CON0_SWU, IFXMIPS_LED_CON0);
+ writel(0, IFXMIPS_LED_CON1);
/* setup the clock edge that the shift register is triggered on */
- writel(readl(DANUBE_LED_CON0) & ~DANUBE_LED_EDGE_MASK, DANUBE_LED_CON0);
- writel(readl(DANUBE_LED_CON0) | DANUBE_LED_CLK_EDGE, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
/* per default leds 15-0 are set */
- writel(DANUBE_LED_GROUP1 | DANUBE_LED_GROUP0, DANUBE_LED_CON1);
+ writel(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
/* leds are update periodically by the FPID */
- writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_UPD_MASK, DANUBE_LED_CON1);
- writel(readl(DANUBE_LED_CON1) | DANUBE_LED_UPD_SRC_FPI, DANUBE_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
/* set led update speed */
- writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_MASK, DANUBE_LED_CON1);
- writel(readl(DANUBE_LED_CON1) | DANUBE_LED_SPEED, DANUBE_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
+ writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
/* adsl 0 and 1 leds are updated by the arc */
- writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
+ writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
/* per default, the leds are turned on */
- danube_pmu_enable(DANUBE_PMU_PWDCR_LED);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
diff --git a/target/linux/ifxmips/files/drivers/char/danube_ssc.c b/target/linux/ifxmips/files/drivers/char/danube_ssc.c
index 1f90dac595..c26b7bbaff 100644
--- a/target/linux/ifxmips/files/drivers/char/danube_ssc.c
+++ b/target/linux/ifxmips/files/drivers/char/danube_ssc.c
@@ -872,20 +872,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
/* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
/* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
/* Set p0.15 to alternative 01, others to 00 (In/OUT) */
- *(DANUBE_GPIO_P0_DIR) = (*DANUBE_GPIO_P0_DIR) | (0xA000);
- *(DANUBE_GPIO_P0_ALTSEL0) = (((*DANUBE_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
- *(DANUBE_GPIO_P0_ALTSEL1) = (((*DANUBE_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
- *(DANUBE_GPIO_P0_OD) = (*DANUBE_GPIO_P0_OD) | 0xA000;
+ *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
+ *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
+ *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
+ *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
/* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
- *(DANUBE_GPIO_P1_DIR) = ((*DANUBE_GPIO_P1_DIR) | (0x46)) & (~1);
- *(DANUBE_GPIO_P1_ALTSEL0) = ((*DANUBE_GPIO_P1_ALTSEL0) | (0x47));
- *(DANUBE_GPIO_P1_ALTSEL1) = (*DANUBE_GPIO_P1_ALTSEL1) & (~0x47);
- *(DANUBE_GPIO_P1_OD) = (*DANUBE_GPIO_P1_OD) | 0x0046;
+ *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
+ *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
+ *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
+ *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
/*CS3 */
/*TODO: CS4 CS5 CS6 */
- *DANUBE_GPIO_P0_OUT = ((*DANUBE_GPIO_P0_OUT) | 0x2000);
+ *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
local_irq_restore (flags);
@@ -1273,10 +1273,10 @@ ifx_ssc_init (void)
info->txbuf = NULL;
/* values specific to SSC1 */
if (i == 0) {
- info->mapbase = DANUBE_SSC1_BASE_ADDR;
- info->txirq = DANUBE_SSC_TIR;
- info->rxirq = DANUBE_SSC_RIR;
- info->errirq = DANUBE_SSC_EIR;
+ info->mapbase = IFXMIPS_SSC1_BASE_ADDR;
+ info->txirq = IFXMIPS_SSC_TIR;
+ info->rxirq = IFXMIPS_SSC_RIR;
+ info->errirq = IFXMIPS_SSC_EIR;
}
WRITE_PERIPHERAL_REGISTER (IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, info->mapbase + IFX_SSC_CLC);
diff --git a/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c b/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
index be2b339381..54885c1615 100644
--- a/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
+++ b/target/linux/ifxmips/files/drivers/char/watchdog/danube_wdt.c
@@ -43,8 +43,8 @@ danube_wdt_enable (unsigned int timeout)
int retval = 0;
/* clock divider & prewarning limit */
- wdt_clkdiv = 1 << (7 * DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR)));
- wdt_pwl = 0x8000 >> DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR));
+ wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR)));
+ wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR));
//TODO
printk("WARNING FUNCTION CALL MISSING!!!");
@@ -65,21 +65,21 @@ danube_wdt_enable (unsigned int timeout)
}
/* Write first part of password access */
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- wdt_cr &= (!DANUBE_BIU_WDT_CR_PW_SET(0xff) &
- !DANUBE_BIU_WDT_CR_PWL_SET(0x3) &
- !DANUBE_BIU_WDT_CR_CLKDIV_SET(0x3) &
- !DANUBE_BIU_WDT_CR_RELOAD_SET(0xffff));
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ wdt_cr &= (!IFXMIPS_BIU_WDT_CR_PW_SET(0xff) &
+ !IFXMIPS_BIU_WDT_CR_PWL_SET(0x3) &
+ !IFXMIPS_BIU_WDT_CR_CLKDIV_SET(0x3) &
+ !IFXMIPS_BIU_WDT_CR_RELOAD_SET(0xffff));
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) |
- DANUBE_BIU_WDT_CR_PWL_SET(DANUBE_BIU_WDT_CR_PWL_GET(readl(DANUBE_BIU_WDT_CR))) |
- DANUBE_BIU_WDT_CR_CLKDIV_SET(DANUBE_BIU_WDT_CR_CLKDIV_GET(readl(DANUBE_BIU_WDT_CR))) |
- DANUBE_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
- DANUBE_BIU_WDT_CR_GEN);
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) |
+ IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR))) |
+ IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR))) |
+ IFXMIPS_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
+ IFXMIPS_BIU_WDT_CR_GEN);
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
printk("watchdog enabled\n");
@@ -90,8 +90,8 @@ out:
void
danube_wdt_disable (void)
{
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
printk("watchdog disabled\n");
}
@@ -102,20 +102,20 @@ danube_wdt_enable_feature (int en, int type)
{
unsigned int wdt_cr = 0;
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
if (en)
{
- wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff));
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | type);
+ wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | type);
} else {
- wdt_cr &= (~DANUBE_BIU_WDT_CR_PW_SET(0xff) & ~type);
- wdt_cr |= DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2);
+ wdt_cr &= (~IFXMIPS_BIU_WDT_CR_PW_SET(0xff) & ~type);
+ wdt_cr |= IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2);
}
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -123,14 +123,14 @@ danube_wdt_prewarning_limit (int pwl)
{
unsigned int wdt_cr = 0;
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xf300ffff;
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_PWL_SET(pwl));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_PWL_SET(pwl));
/* Set reload value in second password access */
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
void
@@ -138,14 +138,14 @@ danube_wdt_set_clkdiv (int clkdiv)
{
unsigned int wdt_cr = 0;
- wdt_cr = readl(DANUBE_BIU_WDT_CR);
- writel(DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW1), DANUBE_BIU_WDT_CR);
+ wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+ writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
wdt_cr &= 0xfc00ffff;
- wdt_cr |= (DANUBE_BIU_WDT_CR_PW_SET(DANUBE_WDT_PW2) | DANUBE_BIU_WDT_CR_CLKDIV_SET(clkdiv));
+ wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_CLKDIV_SET(clkdiv));
/* Set reload value in second password access */
- writel(wdt_cr, DANUBE_BIU_WDT_CR);
+ writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
}
static int
@@ -156,7 +156,7 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
static int timeout = -1;
unsigned int user_arg;
- if ((cmd != DANUBE_WDT_IOC_STOP) && (cmd != DANUBE_WDT_IOC_PING) && (cmd != DANUBE_WDT_IOC_GET_STATUS))
+ if ((cmd != IFXMIPS_WDT_IOC_STOP) && (cmd != IFXMIPS_WDT_IOC_PING) && (cmd != IFXMIPS_WDT_IOC_GET_STATUS))
{
if (copy_from_user((void *) &user_arg, (void *) arg, sizeof (int))){
result = -EINVAL;
@@ -166,43 +166,43 @@ danube_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
switch (cmd)
{
- case DANUBE_WDT_IOC_START:
+ case IFXMIPS_WDT_IOC_START:
if ((result = danube_wdt_enable(user_arg)) < 0)
timeout = -1;
else
timeout = user_arg;
break;
- case DANUBE_WDT_IOC_STOP:
+ case IFXMIPS_WDT_IOC_STOP:
printk("disable watch dog timer\n");
danube_wdt_disable();
break;
- case DANUBE_WDT_IOC_PING:
+ case IFXMIPS_WDT_IOC_PING:
if (timeout < 0)
result = -EIO;
else
result = danube_wdt_enable(timeout);
break;
- case DANUBE_WDT_IOC_GET_STATUS:
- user_arg = readl(DANUBE_BIU_WDT_SR);
+ case IFXMIPS_WDT_IOC_GET_STATUS:
+ user_arg = readl(IFXMIPS_BIU_WDT_SR);
copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
break;
- case DANUBE_WDT_IOC_SET_PWL:
+ case IFXMIPS_WDT_IOC_SET_PWL:
danube_wdt_prewarning_limit(user_arg);
break;
- case DANUBE_WDT_IOC_SET_DSEN:
- danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_DSEN);
+ case IFXMIPS_WDT_IOC_SET_DSEN:
+ danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_DSEN);
break;
- case DANUBE_WDT_IOC_SET_LPEN:
- danube_wdt_enable_feature(user_arg, DANUBE_BIU_WDT_CR_LPEN);
+ case IFXMIPS_WDT_IOC_SET_LPEN:
+ danube_wdt_enable_feature(user_arg, IFXMIPS_BIU_WDT_CR_LPEN);
break;
- case DANUBE_WDT_IOC_SET_CLKDIV:
+ case IFXMIPS_WDT_IOC_SET_CLKDIV:
danube_wdt_set_clkdiv(user_arg);
break;
@@ -239,11 +239,11 @@ danube_wdt_register_proc_read (char *buf, char **start, off_t offset, int count,
{
int len = 0;
- len += sprintf (buf + len, "DANUBE_BIU_WDT_PROC_READ\n");
- len += sprintf (buf + len, "DANUBE_BIU_WDT_CR(0x%08x) : 0x%08x\n",
- (unsigned int)DANUBE_BIU_WDT_CR, readl(DANUBE_BIU_WDT_CR));
- len += sprintf (buf + len, "DANUBE_BIU_WDT_SR(0x%08x) : 0x%08x\n",
- (unsigned int)DANUBE_BIU_WDT_SR, readl(DANUBE_BIU_WDT_SR));
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_PROC_READ\n");
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_CR(0x%08x) : 0x%08x\n",
+ (unsigned int)IFXMIPS_BIU_WDT_CR, readl(IFXMIPS_BIU_WDT_CR));
+ len += sprintf (buf + len, "IFXMIPS_BIU_WDT_SR(0x%08x) : 0x%08x\n",
+ (unsigned int)IFXMIPS_BIU_WDT_SR, readl(IFXMIPS_BIU_WDT_SR));
*eof = 1;
diff --git a/target/linux/ifxmips/files/drivers/mtd/maps/danube.c b/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
index 25e9df3de8..46ab528948 100644
--- a/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
+++ b/target/linux/ifxmips/files/drivers/mtd/maps/danube.c
@@ -1,5 +1,5 @@
/*
- * Driver for DANUBE flashmap
+ * Driver for IFXMIPS flashmap
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
static struct map_info
danube_map = {
- .name = "DANUBE_FLASH",
+ .name = "IFXMIPS_FLASH",
.bankwidth = 2,
.size = 0x400000,
};
@@ -108,8 +108,8 @@ danube_partitions[4] = {
},
};
-#define DANUBE_FLASH_START 0x10000000
-#define DANUBE_FLASH_MAX 0x2000000
+#define IFXMIPS_FLASH_START 0x10000000
+#define IFXMIPS_FLASH_MAX 0x2000000
int
find_uImage_size (unsigned long start_offset){
@@ -136,16 +136,16 @@ init_danube_mtd (void)
struct mtd_partition *parts = NULL;
unsigned long uimage_size;
- writel(0x1d7ff, DANUBE_EBU_BUSCON0);
+ writel(0x1d7ff, IFXMIPS_EBU_BUSCON0);
danube_map.read = danube_read16;
danube_map.write = danube_write16;
danube_map.copy_from = danube_copy_from;
danube_map.copy_to = danube_copy_to;
- danube_map.phys = DANUBE_FLASH_START;
- danube_map.virt = ioremap_nocache(DANUBE_FLASH_START, DANUBE_FLASH_MAX);
- danube_map.size = DANUBE_FLASH_MAX;
+ danube_map.phys = IFXMIPS_FLASH_START;
+ danube_map.virt = ioremap_nocache(IFXMIPS_FLASH_START, IFXMIPS_FLASH_MAX);
+ danube_map.size = IFXMIPS_FLASH_MAX;
if (!danube_map.virt) {
printk(KERN_WARNING "Failed to ioremap!\n");
return -EIO;
@@ -191,4 +191,4 @@ module_exit (cleanup_danube_mtd);
MODULE_LICENSE ("GPL");
MODULE_AUTHOR ("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION ("MTD map driver for DANUBE boards");
+MODULE_DESCRIPTION ("MTD map driver for IFXMIPS boards");
diff --git a/target/linux/ifxmips/files/drivers/net/danube_mii0.c b/target/linux/ifxmips/files/drivers/net/danube_mii0.c
index 354ccc36d1..861ff810c2 100644
--- a/target/linux/ifxmips/files/drivers/net/danube_mii0.c
+++ b/target/linux/ifxmips/files/drivers/net/danube_mii0.c
@@ -57,8 +57,8 @@ danube_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
phy_data;
- while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
- writel(val, DANUBE_PPE32_MDIO_ACC);
+ while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+ writel(val, IFXMIPS_PPE32_MDIO_ACC);
}
unsigned short
@@ -68,9 +68,9 @@ danube_read_mdio (u32 phy_addr, u32 phy_reg)
((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
- writel(val, DANUBE_PPE32_MDIO_ACC);
- while (readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
- val = readl(DANUBE_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+ writel(val, IFXMIPS_PPE32_MDIO_ACC);
+ while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+ val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
return val;
}
@@ -84,7 +84,7 @@ danube_switch_open (struct net_device *dev)
for (i = 0; i < dma_dev->max_rx_chan_num; i++)
{
- if ((dma_dev->rx_chan[i])->control == DANUBE_DMA_CH_ON)
+ if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
(dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
}
@@ -238,7 +238,7 @@ dma_intr_handler (struct dma_device_info* dma_dev, int status)
netif_stop_queue(&danube_mii0_dev);
for (i = 0; i < dma_dev->max_tx_chan_num; i++)
{
- if ((dma_dev->tx_chan[i])->control==DANUBE_DMA_CH_ON)
+ if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
}
break;
@@ -332,15 +332,15 @@ switch_init (struct net_device *dev)
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
{
priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
- priv->dma_device->rx_chan[i]->control = DANUBE_DMA_CH_ON;
+ priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
}
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
{
if(i == 0)
- priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
else
- priv->dma_device->tx_chan[i]->control = DANUBE_DMA_CH_OFF;
+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
}
dma_device_register(priv->dma_device);
@@ -373,17 +373,17 @@ switch_init (struct net_device *dev)
static void
danube_sw_chip_init (int mode)
{
- danube_pmu_enable(DANUBE_PMU_PWDCR_DMA);
- danube_pmu_enable(DANUBE_PMU_PWDCR_PPE);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
+ danube_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
if(mode == REV_MII_MODE)
- writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, DANUBE_PPE32_CFG);
+ writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
else if(mode == MII_MODE)
- writel((readl(DANUBE_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, DANUBE_PPE32_CFG);
+ writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
- writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, DANUBE_PPE32_IG_PLEN_CTRL);
+ writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
- writel(PPE32_CGEN, DANUBE_PPE32_ENET_MAC_CFG);
+ writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
wmb();
}
diff --git a/target/linux/ifxmips/files/drivers/serial/danube_asc.c b/target/linux/ifxmips/files/drivers/serial/danube_asc.c
index b50b1e7bee..90f569c223 100644
--- a/target/linux/ifxmips/files/drivers/serial/danube_asc.c
+++ b/target/linux/ifxmips/files/drivers/serial/danube_asc.c
@@ -1,5 +1,5 @@
/*
- * Driver for DANUBEASC serial ports
+ * Driver for IFXMIPSASC serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
@@ -52,7 +52,7 @@
#include <asm/danube/danube_irq.h>
#include <asm/danube/danube_serial.h>
-#define PORT_DANUBEASC 111
+#define PORT_IFXMIPSASC 111
#include <linux/serial_core.h>
@@ -88,7 +88,7 @@ static void
danubeasc_stop_rx (struct uart_port *port)
{
/* clear the RX enable bit */
- writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
+ writel(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
}
static void
@@ -104,12 +104,12 @@ danubeasc_rx_chars (struct uart_port *port)
struct tty_struct *tty = port->info->tty;
unsigned int ch = 0, rsr = 0, fifocnt;
- fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
+ fifocnt = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
while (fifocnt--)
{
u8 flag = TTY_NORMAL;
- ch = readl(DANUBE_ASC1_RBUF);
- rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+ ch = readl(IFXMIPS_ASC1_RBUF);
+ rsr = (readl(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tty);
port->icount.rx++;
@@ -120,14 +120,14 @@ danubeasc_rx_chars (struct uart_port *port)
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
}
rsr &= port->read_status_mask;
@@ -166,11 +166,11 @@ danubeasc_tx_chars (struct uart_port *port)
return;
}
- while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
- >> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
+ while(((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
{
if (port->x_char) {
- writel(port->x_char, DANUBE_ASC1_TBUF);
+ writel(port->x_char, IFXMIPS_ASC1_TBUF);
port->icount.tx++;
port->x_char = 0;
continue;
@@ -179,7 +179,7 @@ danubeasc_tx_chars (struct uart_port *port)
if (uart_circ_empty(xmit))
break;
- writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
+ writel(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
@@ -191,7 +191,7 @@ danubeasc_tx_chars (struct uart_port *port)
static irqreturn_t
danubeasc_tx_int (int irq, void *port)
{
- writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
+ writel(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
danubeasc_start_tx(port);
mask_and_ack_danube_irq(irq);
@@ -202,8 +202,8 @@ static irqreturn_t
danubeasc_er_int (int irq, void *port)
{
/* clear any pending interrupts */
- writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
- ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
+ writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
+ ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
return IRQ_HANDLED;
}
@@ -211,7 +211,7 @@ danubeasc_er_int (int irq, void *port)
static irqreturn_t
danubeasc_rx_int (int irq, void *port)
{
- writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
+ writel(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
danubeasc_rx_chars((struct uart_port *) port);
mask_and_ack_danube_irq(irq);
@@ -223,7 +223,7 @@ danubeasc_tx_empty (struct uart_port *port)
{
int status;
- status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
+ status = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
@@ -251,18 +251,18 @@ danubeasc1_hw_init (void)
{
/* this setup was probably already done in ROM/u-boot but we do it again*/
/* TODO: GPIO pins are multifunction */
- writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
- writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
- writel(0, DANUBE_ASC1_PISEL);
- writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
- ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
- writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
- ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
+ writel((readl(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
+ writel(0, IFXMIPS_ASC1_PISEL);
+ writel(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
+ ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
+ writel(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
+ ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
wmb ();
/*framing, overrun, enable */
- writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
- DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
+ IFXMIPS_ASC1_CON);
}
static int
@@ -281,36 +281,36 @@ danubeasc_startup (struct uart_port *port)
local_irq_save(flags);
- retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
+ retval = request_irq(IFXMIPSASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
if (retval){
printk("failed to request danubeasc_rx_int\n");
return retval;
}
- retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
+ retval = request_irq(IFXMIPSASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
if (retval){
printk("failed to request danubeasc_tx_int\n");
goto err1;
}
- retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
+ retval = request_irq(IFXMIPSASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
if (retval){
printk("failed to request danubeasc_er_int\n");
goto err2;
}
writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
- DANUBE_ASC1_IRNREN);
+ IFXMIPS_ASC1_IRNREN);
local_irq_restore(flags);
return 0;
err2:
- free_irq(DANUBEASC1_TIR, port);
+ free_irq(IFXMIPSASC1_TIR, port);
err1:
- free_irq(DANUBEASC1_RIR, port);
+ free_irq(IFXMIPSASC1_RIR, port);
local_irq_restore(flags);
return retval;
@@ -319,19 +319,19 @@ err1:
static void
danubeasc_shutdown (struct uart_port *port)
{
- free_irq(DANUBEASC1_RIR, port);
- free_irq(DANUBEASC1_TIR, port);
- free_irq(DANUBEASC1_EIR, port);
+ free_irq(IFXMIPSASC1_RIR, port);
+ free_irq(IFXMIPSASC1_TIR, port);
+ free_irq(IFXMIPSASC1_EIR, port);
/*
* disable the baudrate generator to disable the ASC
*/
- writel(0, DANUBE_ASC1_CON);
+ writel(0, IFXMIPS_ASC1_CON);
/* flush and then disable the fifos */
- writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
- writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
- writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
- writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
+ writel(readl(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
+ writel(readl(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
+ writel(readl(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
}
static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
@@ -395,7 +395,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
local_irq_save(flags);
/* set up CON */
- writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@@ -403,22 +403,22 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
quot = quot / 2 - 1;
/* disable the baudrate generator */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
/* make sure the fractional divider is off */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
/* set up to use divisor of 2 */
- writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
/* now we can write the new baudrate into the register */
- writel(quot, DANUBE_ASC1_BG);
+ writel(quot, IFXMIPS_ASC1_BG);
/* turn the baudrate generator back on */
- writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
+ writel(readl(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
/* enable rx */
- writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
+ writel(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
local_irq_restore(flags);
}
@@ -426,7 +426,7 @@ static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new,
static const char*
danubeasc_type (struct uart_port *port)
{
- return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
+ return port->type == PORT_IFXMIPSASC ? "IFXMIPSASC" : NULL;
}
static void
@@ -445,7 +445,7 @@ static void
danubeasc_config_port (struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
- port->type = PORT_DANUBEASC;
+ port->type = PORT_IFXMIPSASC;
danubeasc_request_port(port);
}
}
@@ -454,7 +454,7 @@ static int
danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
- if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
@@ -483,14 +483,14 @@ static struct uart_ops danubeasc_pops = {
};
static struct uart_port danubeasc_port = {
- membase: (void *)DANUBE_ASC1_BASE_ADDR,
- mapbase: DANUBE_ASC1_BASE_ADDR,
+ membase: (void *)IFXMIPS_ASC1_BASE_ADDR,
+ mapbase: IFXMIPS_ASC1_BASE_ADDR,
iotype: SERIAL_IO_MEM,
- irq: DANUBEASC1_RIR,
+ irq: IFXMIPSASC1_RIR,
uartclk: 0,
fifosize: 16,
- unused: {DANUBEASC1_TIR, DANUBEASC1_EIR},
- type: PORT_DANUBEASC,
+ unused: {IFXMIPSASC1_TIR, IFXMIPSASC1_EIR},
+ type: PORT_IFXMIPSASC,
ops: &danubeasc_pops,
flags: ASYNC_BOOT_AUTOCONF,
};
@@ -507,9 +507,9 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
/* wait until the FIFO is not full */
do
{
- fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+ } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
if (s[i] == '\0')
{
@@ -518,14 +518,14 @@ danubeasc_console_write (struct console *co, const char *s, u_int count)
if (s[i] == '\n')
{
- writel('\r', DANUBE_ASC1_TBUF);
+ writel('\r', IFXMIPS_ASC1_TBUF);
do
{
- fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+ fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
>> ASCFSTAT_TXFFLOFF;
- } while (fifocnt == DANUBEASC_TXFIFO_FULL);
+ } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
}
- writel(s[i], DANUBE_ASC1_TBUF);
+ writel(s[i], IFXMIPS_ASC1_TBUF);
}
local_irq_restore(flags);
@@ -545,7 +545,7 @@ danubeasc_console_setup (struct console *co, char *options)
co->index = 0;
port = &danubeasc_port;
danubeasc_port.uartclk = uartclk;
- danubeasc_port.type = PORT_DANUBEASC;
+ danubeasc_port.type = PORT_IFXMIPSASC;
if (options){
uart_parse_options(options, &baud, &parity, &bits, &flow);
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube.h
index 5bad876e1f..64476bf29d 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube.h
@@ -17,13 +17,13 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_H__
-#define _DANUBE_H__
+#ifndef _IFXMIPS_H__
+#define _IFXMIPS_H__
/*------------ GENERAL */
-#define BOARD_SYSTEM_TYPE "DANUBE"
+#define BOARD_SYSTEM_TYPE "IFXMIPS"
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
@@ -33,15 +33,15 @@
/*------------ ASC1 */
-#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
+#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
/* FIFO status register */
-#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
+#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */
-#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
+#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */
#define ASCOPT_CSIZE 0x3
@@ -53,43 +53,43 @@
#define ASCOPT_CREAD 0x20
/* hardware modified control register */
-#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
+#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */
-#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
+#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
/* status register */
-#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
+#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */
-#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
+#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
/* clock control */
-#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
+#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
-#define DANUBE_ASC1_CLC_DISS 0x2
+#define IFXMIPS_ASC1_CLC_DISS 0x2
/* port input select register */
-#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
+#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */
-#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
+#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */
-#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
+#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */
-#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
+#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
-#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
+#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
/* int enable */
-#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
+#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4
@@ -99,54 +99,54 @@
/*------------ RCU */
-#define DANUBE_RCU_BASE_ADDR 0xBF203000
+#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */
-#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
-#define DANUBE_RST_ALL 0x40000000
+#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
+#define IFXMIPS_RST_ALL 0x40000000
/*------------ MCD */
-#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
+#define IFXMIPS_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
/* chip id */
-#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
+#define IFXMIPS_MCD_CHIPID ((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
/*------------ GPTU */
-#define DANUBE_GPTU_BASE_ADDR 0xB8000300
+#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
/* clock control register */
-#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
+#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */
-#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
+#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */
-#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
+#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */
-#define DANUBE_EBU_BASE_ADDR 0xBE105300
+#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */
-#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
-#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
-#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
-#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
+#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
+#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
+#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
+#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */
-#define DANUBE_CGU_BASE_ADDR 0xBF103000
+#define IFXMIPS_CGU_BASE_ADDR 0xBF103000
/* clock mux */
-#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
-#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
-#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
+#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
+#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
+#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
@@ -158,42 +158,42 @@
/*------------ CGU */
-#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
+#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
-#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
-#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
+#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
+#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
/*------------ ICU */
-#define DANUBE_ICU_BASE_ADDR 0xBF880200
+#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
-#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
-#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
-#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
-#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
-#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
+#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
+#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
+#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
+#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
+#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
-#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
+#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
-#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
+#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
/*------------ ETOP */
-#define DANUBE_PPE32_BASE_ADDR 0xBE180000
+#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
-#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
+#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 )
#define MII_MODE 1
#define REV_MII_MODE 2
/* mdio access */
-#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
+#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1804))
#define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000
@@ -204,38 +204,38 @@
#define MDIO_ACC_VAL_MASK 0xffff
/* configuration */
-#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
+#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe
/* packet length */
-#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
+#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000
/* enet */
-#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
+#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800
/*------------ DMA */
-#define DANUBE_DMA_BASE_ADDR 0xBE104100
+#define IFXMIPS_DMA_BASE_ADDR 0xBE104100
-#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
-#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
-#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
-#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
-#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
-#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
-#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
-#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
-#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
-#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
-#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
+#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18))
+#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
+#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
+#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
+#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28))
+#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
+#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
+#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
+#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
+#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
+#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
/*------------ PCI */
@@ -273,82 +273,82 @@
/*------------ WDT */
-#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
+#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
-#define DANUBE_BIU_WDT_CR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
-#define DANUBE_BIU_WDT_SR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
+#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
+#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
-#define DANUBE_BIU_WDT_CR_GEN (1 << 31)
-#define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
-#define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
+#define IFXMIPS_BIU_WDT_CR_GEN (1 << 31)
+#define IFXMIPS_BIU_WDT_CR_DSEN (1 << 30)
+#define IFXMIPS_BIU_WDT_CR_LPEN (1 << 29)
-#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
-#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
-#define DANUBE_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
-#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
-#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
+#define IFXMIPS_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
+#define IFXMIPS_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
+#define IFXMIPS_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
+#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
+#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/*------------ LED */
-#define DANUBE_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
-#define DANUBE_LED_CON0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000))
-#define DANUBE_LED_CON1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004))
-#define DANUBE_LED_CPU0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008))
-#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
-#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
+#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
+#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
+#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
+#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
+#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
+#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25)
#define LED_CON0_AD0 (1 << 24)
-#define DANUBE_LED_2HZ (0)
-#define DANUBE_LED_4HZ (1 << 23)
-#define DANUBE_LED_8HZ (2 << 23)
-#define DANUBE_LED_10HZ (3 << 23)
-#define DANUBE_LED_MASK (0xf << 23)
+#define IFXMIPS_LED_2HZ (0)
+#define IFXMIPS_LED_4HZ (1 << 23)
+#define IFXMIPS_LED_8HZ (2 << 23)
+#define IFXMIPS_LED_10HZ (3 << 23)
+#define IFXMIPS_LED_MASK (0xf << 23)
-#define DANUBE_LED_UPD_SRC_FPI (1 << 31)
-#define DANUBE_LED_UPD_MASK (3 << 30)
-#define DANUBE_LED_ADSL_SRC (3 << 24)
+#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
+#define IFXMIPS_LED_UPD_MASK (3 << 30)
+#define IFXMIPS_LED_ADSL_SRC (3 << 24)
-#define DANUBE_LED_GROUP0 (1 << 0)
-#define DANUBE_LED_GROUP1 (1 << 1)
-#define DANUBE_LED_GROUP2 (1 << 2)
+#define IFXMIPS_LED_GROUP0 (1 << 0)
+#define IFXMIPS_LED_GROUP1 (1 << 1)
+#define IFXMIPS_LED_GROUP2 (1 << 2)
-#define DANUBE_LED_RISING 0
-#define DANUBE_LED_FALLING (1 << 26)
-#define DANUBE_LED_EDGE_MASK (1 << 26)
+#define IFXMIPS_LED_RISING 0
+#define IFXMIPS_LED_FALLING (1 << 26)
+#define IFXMIPS_LED_EDGE_MASK (1 << 26)
/*------------ GPIO */
-#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
-
-#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
-#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
-#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
-#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
-#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
-#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
-#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
-#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
-#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
-#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
-#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
-#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
-#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
-#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
-#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
-#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
-#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
-#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
+#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
+
+#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
+#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
+#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
+#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
+#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
+#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
+#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
+#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
+#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
+#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
+#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
+#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
+#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
+#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
+#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
+#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
+#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
+#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
/*------------ SSC */
-#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
+#define IFXMIPS_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
index 219fd490ed..02c7aec539 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
@@ -17,15 +17,15 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_DMA_H__
-#define _DANUBE_DMA_H__
+#ifndef _IFXMIPS_DMA_H__
+#define _IFXMIPS_DMA_H__
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
-#define DANUBE_DMA_CH_ON 1
-#define DANUBE_DMA_CH_OFF 0
-#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
+#define IFXMIPS_DMA_CH_ON 1
+#define IFXMIPS_DMA_CH_OFF 0
+#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
enum attr_t{
TX = 0,
@@ -53,8 +53,8 @@ enum attr_t{
#define DMA_DROP_MASK (1<<31)
-#define DANUBE_DMA_RX -1
-#define DANUBE_DMA_TX 1
+#define IFXMIPS_DMA_RX -1
+#define IFXMIPS_DMA_TX 1
typedef struct dma_chan_map {
char dev_name[15];
@@ -151,7 +151,7 @@ typedef struct dma_channel_info{
/*on or off of this channel*/
int control;
/**optional information for the upper layer devices*/
-#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
+#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
void* opt[64];
#else
void* opt[25];
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
index 2ea8d9cf7d..9a264dbf9f 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
@@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_GPIO_H__
-#define _DANUBE_GPIO_H__
+#ifndef _IFXMIPS_GPIO_H__
+#define _IFXMIPS_GPIO_H__
extern int danube_port_reserve_pin (unsigned int port, unsigned int pin);
extern int danube_port_free_pin (unsigned int port, unsigned int pin);
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
index 6d14f5d060..4c4c81e5f1 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
@@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_IOCTL_H__
-#define _DANUBE_IOCTL_H__
+#ifndef _IFXMIPS_IOCTL_H__
+#define _IFXMIPS_IOCTL_H__
/*------------ LED */
@@ -28,15 +28,15 @@ struct danube_port_ioctl_parm
int value;
};
-#define DANUBE_PORT_IOC_MAGIC 0xbf
-#define DANUBE_PORT_IOCOD _IOW(DANUBE_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCPUDSEL _IOW(DANUBE_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCPUDEN _IOW(DANUBE_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCSTOFF _IOW(DANUBE_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCDIR _IOW(DANUBE_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCOUTPUT _IOW(DANUBE_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCINPUT _IOWR(DANUBE_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCALTSEL0 _IOW(DANUBE_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
-#define DANUBE_PORT_IOCALTSEL1 _IOW(DANUBE_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOC_MAGIC 0xbf
+#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
+#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
index 45796831fe..12915c120d 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
@@ -17,8 +17,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_IRQ__
-#define _DANUBE_IRQ__
+#ifndef _IFXMIPS_IRQ__
+#define _IFXMIPS_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
@@ -28,38 +28,38 @@
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
-#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
-#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
+#define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
+#define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
+#define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
-#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
-#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
-#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
+#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
+#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
+#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
-#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
+#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define MIPS_CPU_TIMER_IRQ 7
-#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
-#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
-#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
-#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
-#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
-#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
-#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
-#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
-#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
-#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
-#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
-#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
-#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
-#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
-#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
-#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
-#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
-#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
-#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
-#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
+#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
+#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
+#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
+#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
+#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
+#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
+#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
+#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
+#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
+#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
+#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
+#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
+#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
+#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
+#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
+#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
+#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
+#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
+#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
+#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_danube_irq (unsigned int irq_nr);
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
index 6f96ef6b79..20317e37a7 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
@@ -1,5 +1,5 @@
-#ifndef DANUBE_SW_H
-#define DANUBE_SW_H
+#ifndef IFXMIPS_SW_H
+#define IFXMIPS_SW_H
@@ -138,7 +138,7 @@
#define PHY1_ADDR 1
#define P1M 0
-#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
+#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
@@ -251,4 +251,4 @@ struct switch_priv {
enum duplex current_duplex;
};
-#endif //DANUBE_SW_H
+#endif //IFXMIPS_SW_H
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
index 4197933f85..0c8aa98424 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
@@ -1,5 +1,5 @@
-#ifndef DANUBE_H
-#define DANUBE_H
+#ifndef IFXMIPS_H
+#define IFXMIPS_H
/******************************************************************************
Copyright (c) 2002, Infineon Technologies. All rights reserved.
@@ -29,330 +29,330 @@
/* Module : WDT register address and bits */
/***********************************************************************/
-#define BOARD_SYSTEM_TYPE "DANUBE"
+#define BOARD_SYSTEM_TYPE "IFXMIPS"
-#define DANUBE_BIU_WDT (KSEG1+0x1F880000)
+#define IFXMIPS_BIU_WDT (KSEG1+0x1F880000)
/***Watchdog Timer Control Register ***/
-#define DANUBE_BIU_WDT_CR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F0))
-#define DANUBE_BIU_WDT_CR_GEN (1 << 31)
-#define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
-#define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
-#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
-#define DANUBE_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26)
-#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
-#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
-#define DANUBE_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1))
-#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
-#define DANUBE_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
-#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_BIU_WDT_CR ((volatile u32*)(IFXMIPS_BIU_WDT + 0x03F0))
+#define IFXMIPS_BIU_WDT_CR_GEN (1 << 31)
+#define IFXMIPS_BIU_WDT_CR_DSEN (1 << 30)
+#define IFXMIPS_BIU_WDT_CR_LPEN (1 << 29)
+#define IFXMIPS_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
+#define IFXMIPS_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26)
+#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
+#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
+#define IFXMIPS_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1))
+#define IFXMIPS_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
+#define IFXMIPS_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
+#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/***Watchdog Timer Status Register***/
-#define DANUBE_BIU_WDT_SR ((volatile u32*)(DANUBE_BIU_WDT + 0x03F8))
-#define DANUBE_BIU_WDT_SR_EN (1 << 31)
-#define DANUBE_BIU_WDT_SR_AE (1 << 30)
-#define DANUBE_BIU_WDT_SR_PRW (1 << 29)
-#define DANUBE_BIU_WDT_SR_EXP (1 << 28)
-#define DANUBE_BIU_WDT_SR_PWD (1 << 27)
-#define DANUBE_BIU_WDT_SR_DS (1 << 26)
-#define DANUBE_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1))
-#define DANUBE_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_BIU_WDT_SR ((volatile u32*)(IFXMIPS_BIU_WDT + 0x03F8))
+#define IFXMIPS_BIU_WDT_SR_EN (1 << 31)
+#define IFXMIPS_BIU_WDT_SR_AE (1 << 30)
+#define IFXMIPS_BIU_WDT_SR_PRW (1 << 29)
+#define IFXMIPS_BIU_WDT_SR_EXP (1 << 28)
+#define IFXMIPS_BIU_WDT_SR_PWD (1 << 27)
+#define IFXMIPS_BIU_WDT_SR_DS (1 << 26)
+#define IFXMIPS_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1))
+#define IFXMIPS_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : PMU register address and bits */
/***********************************************************************/
-#define DANUBE_PMU (KSEG1+0x1F102000)
+#define IFXMIPS_PMU (KSEG1+0x1F102000)
/* PMU Power down Control Register */
-#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
-#define DANUBE_PMU_PWDCR_GPT (1 << 12)
-#define DANUBE_PMU_PWDCR_FPI (1 << 14)
+#define IFXMIPS_PMU_PWDCR ((volatile u32*)(IFXMIPS_PMU+0x001C))
+#define IFXMIPS_PMU_PWDCR_GPT (1 << 12)
+#define IFXMIPS_PMU_PWDCR_FPI (1 << 14)
/* PMU Status Register */
-#define DANUBE_PMU_SR ((volatile u32*)(DANUBE_PMU+0x0020))
+#define IFXMIPS_PMU_SR ((volatile u32*)(IFXMIPS_PMU+0x0020))
-#define DANUBE_PMU_DMA_SHIFT 5
-#define DANUBE_PMU_PPE_SHIFT 13
-#define DANUBE_PMU_SDIO_SHIFT 16
-#define DANUBE_PMU_ETOP_SHIFT 22
-#define DANUBE_PMU_ENET0_SHIFT 24
-#define DANUBE_PMU_ENET1_SHIFT 25
+#define IFXMIPS_PMU_DMA_SHIFT 5
+#define IFXMIPS_PMU_PPE_SHIFT 13
+#define IFXMIPS_PMU_SDIO_SHIFT 16
+#define IFXMIPS_PMU_ETOP_SHIFT 22
+#define IFXMIPS_PMU_ENET0_SHIFT 24
+#define IFXMIPS_PMU_ENET1_SHIFT 25
/***********************************************************************/
/* Module : RCU register address and bits */
/***********************************************************************/
-#define DANUBE_RCU_BASE_ADDR (0xBF203000)
+#define IFXMIPS_RCU_BASE_ADDR (0xBF203000)
-#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) /* will remove this, pls use DANUBE_RCU_RST_REQ */
+#define IFXMIPS_RCU_REQ (0x0010 + IFXMIPS_RCU_BASE_ADDR) /* will remove this, pls use IFXMIPS_RCU_RST_REQ */
-#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
-#define DANUBE_RCU_RST_STAT ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x0014))
-#define DANUBE_RST_ALL (0x40000000)
+#define IFXMIPS_RCU_RST_REQ ((volatile u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
+#define IFXMIPS_RCU_RST_STAT ((volatile u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0014))
+#define IFXMIPS_RST_ALL (0x40000000)
/***Reset Request Register***/
-#define DANUBE_RCU_RST_REQ_CPU0 (1 << 31)
-#define DANUBE_RCU_RST_REQ_CPU1 (1 << 3)
-#define DANUBE_RCU_RST_REQ_CPUSUB (1 << 29)
-#define DANUBE_RCU_RST_REQ_HRST (1 << 28)
-#define DANUBE_RCU_RST_REQ_WDT0 (1 << 27)
-#define DANUBE_RCU_RST_REQ_WDT1 (1 << 26)
-#define DANUBE_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
-#define DANUBE_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
-#define DANUBE_RCU_RST_REQ_SWTBOOT (1 << 22)
-#define DANUBE_RCU_RST_REQ_DMA (1 << 21)
-#define DANUBE_RCU_RST_REQ_ARC_JTAG (1 << 20)
-#define DANUBE_RCU_RST_REQ_ETHPHY0 (1 << 19)
-#define DANUBE_RCU_RST_REQ_CPU0_BR (1 << 18)
+#define IFXMIPS_RCU_RST_REQ_CPU0 (1 << 31)
+#define IFXMIPS_RCU_RST_REQ_CPU1 (1 << 3)
+#define IFXMIPS_RCU_RST_REQ_CPUSUB (1 << 29)
+#define IFXMIPS_RCU_RST_REQ_HRST (1 << 28)
+#define IFXMIPS_RCU_RST_REQ_WDT0 (1 << 27)
+#define IFXMIPS_RCU_RST_REQ_WDT1 (1 << 26)
+#define IFXMIPS_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
+#define IFXMIPS_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
+#define IFXMIPS_RCU_RST_REQ_SWTBOOT (1 << 22)
+#define IFXMIPS_RCU_RST_REQ_DMA (1 << 21)
+#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)
+#define IFXMIPS_RCU_RST_REQ_ETHPHY0 (1 << 19)
+#define IFXMIPS_RCU_RST_REQ_CPU0_BR (1 << 18)
#define DANBUE_RCU_RST_REQ_AFE (1 << 11)
#define DANBUE_RCU_RST_REQ_DFE (1 << 7)
/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
-#define DANUBE_RCU_RST_REQ_ALL DANUBE_RST_ALL
+#define IFXMIPS_RCU_RST_REQ_ALL IFXMIPS_RST_ALL
-#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR)
-#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) /* will remove this, pls use DANUBE_RCU_RST_STAT */
+#define IFXMIPS_RCU_STAT (0x0014 + IFXMIPS_RCU_BASE_ADDR)
+#define IFXMIPS_RCU_RST_SR ( (volatile u32 *)(IFXMIPS_RCU_STAT)) /* will remove this, pls use IFXMIPS_RCU_RST_STAT */
-/*#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) */
+/*#define IFXMIPS_RCU_MON (0x0030 + IFXMIPS_RCU_BASE_ADDR) */
/***********************************************************************/
/* Module : BCU register address and bits */
/***********************************************************************/
-#define DANUBE_BCU_BASE_ADDR (KSEG1+0x1E100000)
+#define IFXMIPS_BCU_BASE_ADDR (KSEG1+0x1E100000)
/***BCU Control Register (0010H)***/
-#define DANUBE_BCU_CON ((volatile u32*)(0x0010 + DANUBE_BCU_BASE_ADDR))
-#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
-#define DANUBE_BCU_BCU_CON_SPE (1 << 19)
-#define DANUBE_BCU_BCU_CON_PSE (1 << 18)
-#define DANUBE_BCU_BCU_CON_DBG (1 << 16)
-#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_BCU_CON ((volatile u32*)(0x0010 + IFXMIPS_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
+#define IFXMIPS_BCU_BCU_CON_SPE (1 << 19)
+#define IFXMIPS_BCU_BCU_CON_PSE (1 << 18)
+#define IFXMIPS_BCU_BCU_CON_DBG (1 << 16)
+#define IFXMIPS_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
/***BCU Error Control Capture Register (0020H)***/
-#define DANUBE_BCU_ECON ((volatile u32*)(0x0020 + DANUBE_BCU_BASE_ADDR))
-#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define DANUBE_BCU_BCU_ECON_RDN (1 << 23)
-#define DANUBE_BCU_BCU_ECON_WRN (1 << 22)
-#define DANUBE_BCU_BCU_ECON_SVM (1 << 21)
-#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
-#define DANUBE_BCU_BCU_ECON_ABT (1 << 18)
-#define DANUBE_BCU_BCU_ECON_RDY (1 << 17)
-#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16)
-#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
-#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_BCU_ECON ((volatile u32*)(0x0020 + IFXMIPS_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
+#define IFXMIPS_BCU_BCU_ECON_RDN (1 << 23)
+#define IFXMIPS_BCU_BCU_ECON_WRN (1 << 22)
+#define IFXMIPS_BCU_BCU_ECON_SVM (1 << 21)
+#define IFXMIPS_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
+#define IFXMIPS_BCU_BCU_ECON_ABT (1 << 18)
+#define IFXMIPS_BCU_BCU_ECON_RDY (1 << 17)
+#define IFXMIPS_BCU_BCU_ECON_TOUT (1 << 16)
+#define IFXMIPS_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
/***BCU Error Address Capture Register (0024 H)***/
-#define DANUBE_BCU_EADD ((volatile u32*)(0x0024 + DANUBE_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_EADD ((volatile u32*)(0x0024 + IFXMIPS_BCU_BASE_ADDR))
/***BCU Error Data Capture Register (0028H)***/
-#define DANUBE_BCU_EDAT ((volatile u32*)(0x0028 + DANUBE_BCU_BASE_ADDR))
-#define DANUBE_BCU_IRNEN ((volatile u32*)(0x00F4 + DANUBE_BCU_BASE_ADDR))
-#define DANUBE_BCU_IRNICR ((volatile u32*)(0x00F8 + DANUBE_BCU_BASE_ADDR))
-#define DANUBE_BCU_IRNCR ((volatile u32*)(0x00FC + DANUBE_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_EDAT ((volatile u32*)(0x0028 + IFXMIPS_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_IRNEN ((volatile u32*)(0x00F4 + IFXMIPS_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_IRNICR ((volatile u32*)(0x00F8 + IFXMIPS_BCU_BASE_ADDR))
+#define IFXMIPS_BCU_IRNCR ((volatile u32*)(0x00FC + IFXMIPS_BCU_BASE_ADDR))
/***********************************************************************/
/* Module : MBC register address and bits */
/***********************************************************************/
-#define DANUBE_MBC (0xBF103000)
+#define IFXMIPS_MBC (0xBF103000)
/***********************************************************************/
/***Mailbox CPU Configuration Register***/
-#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080))
-#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define DANUBE_MBC_MBC_CFG_RES (1 << 5)
-#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
-#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0)
+#define IFXMIPS_MBC_MBC_CFG ((volatile u32*)(IFXMIPS_MBC+ 0x0080))
+#define IFXMIPS_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define IFXMIPS_MBC_MBC_CFG_RES (1 << 5)
+#define IFXMIPS_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
+#define IFXMIPS_MBC_MBC_CFG_SIZE (1 << 0)
/***Mailbox CPU Interrupt Status Register***/
-#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084))
-#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31)
-#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30)
-#define DANUBE_MBC_MBC_ISR_B1E (1 << 29)
-#define DANUBE_MBC_MBC_ISR_B0E (1 << 28)
-#define DANUBE_MBC_MBC_ISR_WDT (1 << 27)
-#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_ISR ((volatile u32*)(IFXMIPS_MBC+ 0x0084))
+#define IFXMIPS_MBC_MBC_ISR_B3DA (1 << 31)
+#define IFXMIPS_MBC_MBC_ISR_B2DA (1 << 30)
+#define IFXMIPS_MBC_MBC_ISR_B1E (1 << 29)
+#define IFXMIPS_MBC_MBC_ISR_B0E (1 << 28)
+#define IFXMIPS_MBC_MBC_ISR_WDT (1 << 27)
+#define IFXMIPS_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
/***Mailbox CPU Mask Register***/
-#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088))
-#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31)
-#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30)
-#define DANUBE_MBC_MBC_MSK_B1E (1 << 29)
-#define DANUBE_MBC_MBC_MSK_B0E (1 << 28)
-#define DANUBE_MBC_MBC_MSK_WDT (1 << 27)
-#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_MSK ((volatile u32*)(IFXMIPS_MBC+ 0x0088))
+#define IFXMIPS_MBC_MBC_MSK_B3DA (1 << 31)
+#define IFXMIPS_MBC_MBC_MSK_B2DA (1 << 30)
+#define IFXMIPS_MBC_MBC_MSK_B1E (1 << 29)
+#define IFXMIPS_MBC_MBC_MSK_B0E (1 << 28)
+#define IFXMIPS_MBC_MBC_MSK_WDT (1 << 27)
+#define IFXMIPS_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
/***Mailbox CPU Mask 01 Register***/
-#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C))
-#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31)
-#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30)
-#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29)
-#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28)
-#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27)
-#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_MSK01 ((volatile u32*)(IFXMIPS_MBC+ 0x008C))
+#define IFXMIPS_MBC_MBC_MSK01_B3DA (1 << 31)
+#define IFXMIPS_MBC_MBC_MSK01_B2DA (1 << 30)
+#define IFXMIPS_MBC_MBC_MSK01_B1E (1 << 29)
+#define IFXMIPS_MBC_MBC_MSK01_B0E (1 << 28)
+#define IFXMIPS_MBC_MBC_MSK01_WDT (1 << 27)
+#define IFXMIPS_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
/***Mailbox CPU Mask 10 Register***/
-#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090))
-#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31)
-#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30)
-#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29)
-#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28)
-#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27)
-#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_MSK10 ((volatile u32*)(IFXMIPS_MBC+ 0x0090))
+#define IFXMIPS_MBC_MBC_MSK10_B3DA (1 << 31)
+#define IFXMIPS_MBC_MBC_MSK10_B2DA (1 << 30)
+#define IFXMIPS_MBC_MBC_MSK10_B1E (1 << 29)
+#define IFXMIPS_MBC_MBC_MSK10_B0E (1 << 28)
+#define IFXMIPS_MBC_MBC_MSK10_WDT (1 << 27)
+#define IFXMIPS_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
/***Mailbox CPU Short Command Register***/
-#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094))
-#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_CMD ((volatile u32*)(IFXMIPS_MBC+ 0x0094))
+#define IFXMIPS_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
/***Mailbox CPU Input Data of Buffer 0***/
-#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000))
-#define DANUBE_MBC_MBC_ID0_INDATA
+#define IFXMIPS_MBC_MBC_ID0 ((volatile u32*)(IFXMIPS_MBC+ 0x0000))
+#define IFXMIPS_MBC_MBC_ID0_INDATA
/***Mailbox CPU Input Data of Buffer 1***/
-#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020))
-#define DANUBE_MBC_MBC_ID1_INDATA
+#define IFXMIPS_MBC_MBC_ID1 ((volatile u32*)(IFXMIPS_MBC+ 0x0020))
+#define IFXMIPS_MBC_MBC_ID1_INDATA
/***Mailbox CPU Output Data of Buffer 2***/
-#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040))
-#define DANUBE_MBC_MBC_OD2_OUTDATA
+#define IFXMIPS_MBC_MBC_OD2 ((volatile u32*)(IFXMIPS_MBC+ 0x0040))
+#define IFXMIPS_MBC_MBC_OD2_OUTDATA
/***Mailbox CPU Output Data of Buffer 3***/
-#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060))
-#define DANUBE_MBC_MBC_OD3_OUTDATA
+#define IFXMIPS_MBC_MBC_OD3 ((volatile u32*)(IFXMIPS_MBC+ 0x0060))
+#define IFXMIPS_MBC_MBC_OD3_OUTDATA
/***Mailbox CPU Control Register of Buffer 0***/
-#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004))
-#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_CR0 ((volatile u32*)(IFXMIPS_MBC+ 0x0004))
+#define IFXMIPS_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
/***Mailbox CPU Control Register of Buffer 1***/
-#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024))
-#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_CR1 ((volatile u32*)(IFXMIPS_MBC+ 0x0024))
+#define IFXMIPS_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
/***Mailbox CPU Control Register of Buffer 2***/
-#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044))
-#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_CR2 ((volatile u32*)(IFXMIPS_MBC+ 0x0044))
+#define IFXMIPS_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
/***Mailbox CPU Control Register of Buffer 3***/
-#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064))
-#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_MBC_MBC_CR3 ((volatile u32*)(IFXMIPS_MBC+ 0x0064))
+#define IFXMIPS_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
/***Mailbox CPU Free Space of Buffer 0***/
-#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008))
-#define DANUBE_MBC_MBC_FS0_FS
+#define IFXMIPS_MBC_MBC_FS0 ((volatile u32*)(IFXMIPS_MBC+ 0x0008))
+#define IFXMIPS_MBC_MBC_FS0_FS
/***Mailbox CPU Free Space of Buffer 1***/
-#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028))
-#define DANUBE_MBC_MBC_FS1_FS
+#define IFXMIPS_MBC_MBC_FS1 ((volatile u32*)(IFXMIPS_MBC+ 0x0028))
+#define IFXMIPS_MBC_MBC_FS1_FS
/***Mailbox CPU Free Space of Buffer 2***/
-#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048))
-#define DANUBE_MBC_MBC_FS2_FS
+#define IFXMIPS_MBC_MBC_FS2 ((volatile u32*)(IFXMIPS_MBC+ 0x0048))
+#define IFXMIPS_MBC_MBC_FS2_FS
/***Mailbox CPU Free Space of Buffer 3***/
-#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068))
-#define DANUBE_MBC_MBC_FS3_FS
+#define IFXMIPS_MBC_MBC_FS3 ((volatile u32*)(IFXMIPS_MBC+ 0x0068))
+#define IFXMIPS_MBC_MBC_FS3_FS
/***Mailbox CPU Data Available in Buffer 0***/
-#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C))
-#define DANUBE_MBC_MBC_DA0_DA
+#define IFXMIPS_MBC_MBC_DA0 ((volatile u32*)(IFXMIPS_MBC+ 0x000C))
+#define IFXMIPS_MBC_MBC_DA0_DA
/***Mailbox CPU Data Available in Buffer 1***/
-#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C))
-#define DANUBE_MBC_MBC_DA1_DA
+#define IFXMIPS_MBC_MBC_DA1 ((volatile u32*)(IFXMIPS_MBC+ 0x002C))
+#define IFXMIPS_MBC_MBC_DA1_DA
/***Mailbox CPU Data Available in Buffer 2***/
-#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C))
-#define DANUBE_MBC_MBC_DA2_DA
+#define IFXMIPS_MBC_MBC_DA2 ((volatile u32*)(IFXMIPS_MBC+ 0x004C))
+#define IFXMIPS_MBC_MBC_DA2_DA
/***Mailbox CPU Data Available in Buffer 3***/
-#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C))
-#define DANUBE_MBC_MBC_DA3_DA
+#define IFXMIPS_MBC_MBC_DA3 ((volatile u32*)(IFXMIPS_MBC+ 0x006C))
+#define IFXMIPS_MBC_MBC_DA3_DA
/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
-#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010))
-#define DANUBE_MBC_MBC_IABS0_IABS
+#define IFXMIPS_MBC_MBC_IABS0 ((volatile u32*)(IFXMIPS_MBC+ 0x0010))
+#define IFXMIPS_MBC_MBC_IABS0_IABS
/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
-#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030))
-#define DANUBE_MBC_MBC_IABS1_IABS
+#define IFXMIPS_MBC_MBC_IABS1 ((volatile u32*)(IFXMIPS_MBC+ 0x0030))
+#define IFXMIPS_MBC_MBC_IABS1_IABS
/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
-#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050))
-#define DANUBE_MBC_MBC_IABS2_IABS
+#define IFXMIPS_MBC_MBC_IABS2 ((volatile u32*)(IFXMIPS_MBC+ 0x0050))
+#define IFXMIPS_MBC_MBC_IABS2_IABS
/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
-#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070))
-#define DANUBE_MBC_MBC_IABS3_IABS
+#define IFXMIPS_MBC_MBC_IABS3 ((volatile u32*)(IFXMIPS_MBC+ 0x0070))
+#define IFXMIPS_MBC_MBC_IABS3_IABS
/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
-#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014))
-#define DANUBE_MBC_MBC_ITMP0_ITMP
+#define IFXMIPS_MBC_MBC_ITMP0 ((volatile u32*)(IFXMIPS_MBC+ 0x0014))
+#define IFXMIPS_MBC_MBC_ITMP0_ITMP
/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
-#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034))
-#define DANUBE_MBC_MBC_ITMP1_ITMP
+#define IFXMIPS_MBC_MBC_ITMP1 ((volatile u32*)(IFXMIPS_MBC+ 0x0034))
+#define IFXMIPS_MBC_MBC_ITMP1_ITMP
/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
-#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054))
-#define DANUBE_MBC_MBC_ITMP2_ITMP
+#define IFXMIPS_MBC_MBC_ITMP2 ((volatile u32*)(IFXMIPS_MBC+ 0x0054))
+#define IFXMIPS_MBC_MBC_ITMP2_ITMP
/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
-#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074))
-#define DANUBE_MBC_MBC_ITMP3_ITMP
+#define IFXMIPS_MBC_MBC_ITMP3 ((volatile u32*)(IFXMIPS_MBC+ 0x0074))
+#define IFXMIPS_MBC_MBC_ITMP3_ITMP
/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
-#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018))
-#define DANUBE_MBC_MBC_OABS0_OABS
+#define IFXMIPS_MBC_MBC_OABS0 ((volatile u32*)(IFXMIPS_MBC+ 0x0018))
+#define IFXMIPS_MBC_MBC_OABS0_OABS
/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
-#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038))
-#define DANUBE_MBC_MBC_OABS1_OABS
+#define IFXMIPS_MBC_MBC_OABS1 ((volatile u32*)(IFXMIPS_MBC+ 0x0038))
+#define IFXMIPS_MBC_MBC_OABS1_OABS
/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
-#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058))
-#define DANUBE_MBC_MBC_OABS2_OABS
+#define IFXMIPS_MBC_MBC_OABS2 ((volatile u32*)(IFXMIPS_MBC+ 0x0058))
+#define IFXMIPS_MBC_MBC_OABS2_OABS
/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
-#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078))
-#define DANUBE_MBC_MBC_OABS3_OABS
+#define IFXMIPS_MBC_MBC_OABS3 ((volatile u32*)(IFXMIPS_MBC+ 0x0078))
+#define IFXMIPS_MBC_MBC_OABS3_OABS
/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
-#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C))
-#define DANUBE_MBC_MBC_OTMP0_OTMP
+#define IFXMIPS_MBC_MBC_OTMP0 ((volatile u32*)(IFXMIPS_MBC+ 0x001C))
+#define IFXMIPS_MBC_MBC_OTMP0_OTMP
/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
-#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C))
-#define DANUBE_MBC_MBC_OTMP1_OTMP
+#define IFXMIPS_MBC_MBC_OTMP1 ((volatile u32*)(IFXMIPS_MBC+ 0x003C))
+#define IFXMIPS_MBC_MBC_OTMP1_OTMP
/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
-#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C))
-#define DANUBE_MBC_MBC_OTMP2_OTMP
+#define IFXMIPS_MBC_MBC_OTMP2 ((volatile u32*)(IFXMIPS_MBC+ 0x005C))
+#define IFXMIPS_MBC_MBC_OTMP2_OTMP
/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
-#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C))
-#define DANUBE_MBC_MBC_OTMP3_OTMP
+#define IFXMIPS_MBC_MBC_OTMP3 ((volatile u32*)(IFXMIPS_MBC+ 0x007C))
+#define IFXMIPS_MBC_MBC_OTMP3_OTMP
/***DSP Control Register***/
-#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0))
-#define DANUBE_MBC_DCTRL_BA (1 << 0)
-#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
-#define DANUBE_MBC_DCTRL_IDL (1 << 4)
-#define DANUBE_MBC_DCTRL_RES (1 << 15)
+#define IFXMIPS_MBC_DCTRL ((volatile u32*)(IFXMIPS_MBC+ 0x00A0))
+#define IFXMIPS_MBC_DCTRL_BA (1 << 0)
+#define IFXMIPS_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
+#define IFXMIPS_MBC_DCTRL_IDL (1 << 4)
+#define IFXMIPS_MBC_DCTRL_RES (1 << 15)
/***DSP Status Register***/
-#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4))
-#define DANUBE_MBC_DSTA_IDLE (1 << 0)
-#define DANUBE_MBC_DSTA_PD (1 << 1)
+#define IFXMIPS_MBC_DSTA ((volatile u32*)(IFXMIPS_MBC+ 0x00A4))
+#define IFXMIPS_MBC_DSTA_IDLE (1 << 0)
+#define IFXMIPS_MBC_DSTA_PD (1 << 1)
/***DSP Test 1 Register***/
-#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8))
-#define DANUBE_MBC_DTST1_ABORT (1 << 0)
-#define DANUBE_MBC_DTST1_HWF32 (1 << 1)
-#define DANUBE_MBC_DTST1_HWF4M (1 << 2)
-#define DANUBE_MBC_DTST1_HWFOP (1 << 3)
+#define IFXMIPS_MBC_DTST1 ((volatile u32*)(IFXMIPS_MBC+ 0x00A8))
+#define IFXMIPS_MBC_DTST1_ABORT (1 << 0)
+#define IFXMIPS_MBC_DTST1_HWF32 (1 << 1)
+#define IFXMIPS_MBC_DTST1_HWF4M (1 << 2)
+#define IFXMIPS_MBC_DTST1_HWFOP (1 << 3)
/***********************************************************************/
/* Module : MEI register address and bits */
@@ -404,177 +404,177 @@
/* Module : SSC1 register address and bits */
/***********************************************************************/
-#define DANUBE_SSC1 (KSEG1+0x1e100800)
+#define IFXMIPS_SSC1 (KSEG1+0x1e100800)
/***********************************************************************/
/***SSC Clock Control Register***/
-#define DANUBE_SSC_CLC (0x0000)
-#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define DANUBE_SSC_CLC_DISS (1 << 1)
-#define DANUBE_SSC_CLC_DISR (1 << 0)
+#define IFXMIPS_SSC_CLC (0x0000)
+#define IFXMIPS_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
+#define IFXMIPS_SSC_CLC_DISS (1 << 1)
+#define IFXMIPS_SSC_CLC_DISR (1 << 0)
/***SSC Port Input Selection Register***/
-#define DANUBE_SSC_PISEL (0x0004)
+#define IFXMIPS_SSC_PISEL (0x0004)
/***SSC Identification Register***/
-#define DANUBE_SSC_ID (0x0008)
+#define IFXMIPS_SSC_ID (0x0008)
/***Control Register (Programming Mode)***/
-#define DANUBE_SSC_CON (0x0010)
-#define DANUBE_SSC_CON_RUEN (1 << 12)
-#define DANUBE_SSC_CON_TUEN (1 << 11)
-#define DANUBE_SSC_CON_AEN (1 << 10)
-#define DANUBE_SSC_CON_REN (1 << 9)
-#define DANUBE_SSC_CON_TEN (1 << 8)
-#define DANUBE_SSC_CON_LB (1 << 7)
-#define DANUBE_SSC_CON_PO (1 << 6)
-#define DANUBE_SSC_CON_PH (1 << 5)
-#define DANUBE_SSC_CON_HB (1 << 4)
-#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16)
-#define DANUBE_SSC_CON_RX_OFF (1 << 1)
-#define DANUBE_SSC_CON_TX_OFF (1 << 0)
+#define IFXMIPS_SSC_CON (0x0010)
+#define IFXMIPS_SSC_CON_RUEN (1 << 12)
+#define IFXMIPS_SSC_CON_TUEN (1 << 11)
+#define IFXMIPS_SSC_CON_AEN (1 << 10)
+#define IFXMIPS_SSC_CON_REN (1 << 9)
+#define IFXMIPS_SSC_CON_TEN (1 << 8)
+#define IFXMIPS_SSC_CON_LB (1 << 7)
+#define IFXMIPS_SSC_CON_PO (1 << 6)
+#define IFXMIPS_SSC_CON_PH (1 << 5)
+#define IFXMIPS_SSC_CON_HB (1 << 4)
+#define IFXMIPS_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16)
+#define IFXMIPS_SSC_CON_RX_OFF (1 << 1)
+#define IFXMIPS_SSC_CON_TX_OFF (1 << 0)
/***SCC Status Register***/
-#define DANUBE_SSC_STATE (0x0014)
-#define DANUBE_SSC_STATE_EN (1 << 0)
-#define DANUBE_SSC_STATE_MS (1 << 1)
-#define DANUBE_SSC_STATE_BSY (1 << 13)
-#define DANUBE_SSC_STATE_RUE (1 << 12)
-#define DANUBE_SSC_STATE_TUE (1 << 11)
-#define DANUBE_SSC_STATE_AE (1 << 10)
-#define DANUBE_SSC_STATE_RE (1 << 9)
-#define DANUBE_SSC_STATE_TE (1 << 8)
-#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16)
+#define IFXMIPS_SSC_STATE (0x0014)
+#define IFXMIPS_SSC_STATE_EN (1 << 0)
+#define IFXMIPS_SSC_STATE_MS (1 << 1)
+#define IFXMIPS_SSC_STATE_BSY (1 << 13)
+#define IFXMIPS_SSC_STATE_RUE (1 << 12)
+#define IFXMIPS_SSC_STATE_TUE (1 << 11)
+#define IFXMIPS_SSC_STATE_AE (1 << 10)
+#define IFXMIPS_SSC_STATE_RE (1 << 9)
+#define IFXMIPS_SSC_STATE_TE (1 << 8)
+#define IFXMIPS_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16)
/***SSC Write Hardware Modified Control Register***/
-#define DANUBE_SSC_WHBSTATE ( 0x0018)
-#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15)
-#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14)
-#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13)
-#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12)
-#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11)
-#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10)
-#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9)
-#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8)
+#define IFXMIPS_SSC_WHBSTATE ( 0x0018)
+#define IFXMIPS_SSC_WHBSTATE_SETBE (1 << 15)
+#define IFXMIPS_SSC_WHBSTATE_SETPE (1 << 14)
+#define IFXMIPS_SSC_WHBSTATE_SETRE (1 << 13)
+#define IFXMIPS_SSC_WHBSTATE_SETTE (1 << 12)
+#define IFXMIPS_SSC_WHBSTATE_CLRBE (1 << 11)
+#define IFXMIPS_SSC_WHBSTATE_CLRPE (1 << 10)
+#define IFXMIPS_SSC_WHBSTATE_CLRRE (1 << 9)
+#define IFXMIPS_SSC_WHBSTATE_CLRTE (1 << 8)
/***SSC Transmitter Buffer Register***/
-#define DANUBE_SSC_TB (0x0020)
-#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_SSC_TB (0x0020)
+#define IFXMIPS_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
/***SSC Receiver Buffer Register***/
-#define DANUBE_SSC_RB (0x0024)
-#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_SSC_RB (0x0024)
+#define IFXMIPS_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
/***SSC Receive FIFO Control Register***/
-#define DANUBE_SSC_RXFCON (0x0030)
-#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2)
-#define DANUBE_SSC_RXFCON_RXFLU (1 << 1)
-#define DANUBE_SSC_RXFCON_RXFEN (1 << 0)
+#define IFXMIPS_SSC_RXFCON (0x0030)
+#define IFXMIPS_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_SSC_RXFCON_RXTMEN (1 << 2)
+#define IFXMIPS_SSC_RXFCON_RXFLU (1 << 1)
+#define IFXMIPS_SSC_RXFCON_RXFEN (1 << 0)
/***SSC Transmit FIFO Control Register***/
-#define DANUBE_SSC_TXFCON ( 0x0034)
-#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2)
-#define DANUBE_SSC_TXFCON_TXFLU (1 << 1)
-#define DANUBE_SSC_TXFCON_TXFEN (1 << 0)
+#define IFXMIPS_SSC_TXFCON ( 0x0034)
+#define IFXMIPS_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_SSC_TXFCON_TXTMEN (1 << 2)
+#define IFXMIPS_SSC_TXFCON_TXFLU (1 << 1)
+#define IFXMIPS_SSC_TXFCON_TXFEN (1 << 0)
/***SSC FIFO Status Register***/
-#define DANUBE_SSC_FSTAT (0x0038)
-#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
+#define IFXMIPS_SSC_FSTAT (0x0038)
+#define IFXMIPS_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
/***SSC Baudrate Timer Reload Register***/
-#define DANUBE_SSC_BR (0x0040)
-#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
-#define DANUBE_SSC_BRSTAT (0x0044)
-#define DANUBE_SSC_SFCON (0x0060)
-#define DANUBE_SSC_SFSTAT (0x0064)
-#define DANUBE_SSC_GPOCON (0x0070)
-#define DANUBE_SSC_GPOSTAT (0x0074)
-#define DANUBE_SSC_WHBGPOSTAT (0x0078)
-#define DANUBE_SSC_RXREQ (0x0080)
-#define DANUBE_SSC_RXCNT (0x0084)
+#define IFXMIPS_SSC_BR (0x0040)
+#define IFXMIPS_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_SSC_BRSTAT (0x0044)
+#define IFXMIPS_SSC_SFCON (0x0060)
+#define IFXMIPS_SSC_SFSTAT (0x0064)
+#define IFXMIPS_SSC_GPOCON (0x0070)
+#define IFXMIPS_SSC_GPOSTAT (0x0074)
+#define IFXMIPS_SSC_WHBGPOSTAT (0x0078)
+#define IFXMIPS_SSC_RXREQ (0x0080)
+#define IFXMIPS_SSC_RXCNT (0x0084)
/*DMA Registers in Bus Clock Domain*/
-#define DANUBE_SSC_DMA_CON (0x00EC)
+#define IFXMIPS_SSC_DMA_CON (0x00EC)
/*interrupt Node Registers in Bus Clock Domain*/
-#define DANUBE_SSC_IRNEN (0x00F4)
-#define DANUBE_SSC_IRNCR (0x00F8)
-#define DANUBE_SSC_IRNICR (0x00FC)
-#define DANUBE_SSC_IRN_FIR 0x8
-#define DANUBE_SSC_IRN_EIR 0x4
-#define DANUBE_SSC_IRN_RIR 0x2
-#define DANUBE_SSC_IRN_TIR 0x1
-
-#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC))
-#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID))
-#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON))
-#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE))
-#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE))
-#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB))
-#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB))
-#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT))
-#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL))
-#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON))
-#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON))
-#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR))
-#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT))
-#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON))
-#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT))
-#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON))
-#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT))
-#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT))
-#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ))
-#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT))
-#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON))
-#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN))
-#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR))
-#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR))
+#define IFXMIPS_SSC_IRNEN (0x00F4)
+#define IFXMIPS_SSC_IRNCR (0x00F8)
+#define IFXMIPS_SSC_IRNICR (0x00FC)
+#define IFXMIPS_SSC_IRN_FIR 0x8
+#define IFXMIPS_SSC_IRN_EIR 0x4
+#define IFXMIPS_SSC_IRN_RIR 0x2
+#define IFXMIPS_SSC_IRN_TIR 0x1
+
+#define IFXMIPS_SSC1_CLC ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_CLC))
+#define IFXMIPS_SSC1_ID ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_ID))
+#define IFXMIPS_SSC1_CON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_CON))
+#define IFXMIPS_SSC1_STATE ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_STATE))
+#define IFXMIPS_SSC1_WHBSTATE ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_WHBSTATE))
+#define IFXMIPS_SSC1_TB ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_TB))
+#define IFXMIPS_SSC1_RB ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RB))
+#define IFXMIPS_SSC1_FSTAT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_FSTAT))
+#define IFXMIPS_SSC1_PISEL ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_PISEL))
+#define IFXMIPS_SSC1_RXFCON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXFCON))
+#define IFXMIPS_SSC1_TXFCON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_TXFCON))
+#define IFXMIPS_SSC1_BR ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_BR))
+#define IFXMIPS_SSC1_BRSTAT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_BRSTAT))
+#define IFXMIPS_SSC1_SFCON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_SFCON))
+#define IFXMIPS_SSC1_SFSTAT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_SFSTAT))
+#define IFXMIPS_SSC1_GPOCON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_GPOCON))
+#define IFXMIPS_SSC1_GPOSTAT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_GPOSTAT))
+#define IFXMIPS_SSC1_WHBGPOSTAT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_WHBGPOSTAT))
+#define IFXMIPS_SSC1_RXREQ ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXREQ))
+#define IFXMIPS_SSC1_RXCNT ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_RXCNT))
+#define IFXMIPS_SSC1_DMA_CON ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_DMA_CON))
+#define IFXMIPS_SSC1_IRNEN ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNEN))
+#define IFXMIPS_SSC1_IRNICR ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNICR))
+#define IFXMIPS_SSC1_IRNCR ((volatile u32*)(IFXMIPS_SSC1+IFXMIPS_SSC_IRNCR))
/***********************************************************************/
/* Module : GPIO register address and bits */
/***********************************************************************/
-#define DANUBE_GPIO (0xBE100B00)
+#define IFXMIPS_GPIO (0xBE100B00)
/***Port 0 Data Output Register (0010H)***/
-#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010))
+#define IFXMIPS_GPIO_P0_OUT ((volatile u32 *)(IFXMIPS_GPIO+ 0x0010))
/***Port 1 Data Output Register (0040H)***/
-#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040))
+#define IFXMIPS_GPIO_P1_OUT ((volatile u32 *)(IFXMIPS_GPIO+ 0x0040))
/***Port 0 Data Input Register (0014H)***/
-#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014))
+#define IFXMIPS_GPIO_P0_IN ((volatile u32 *)(IFXMIPS_GPIO+ 0x0014))
/***Port 1 Data Input Register (0044H)***/
-#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044))
+#define IFXMIPS_GPIO_P1_IN ((volatile u32 *)(IFXMIPS_GPIO+ 0x0044))
/***Port 0 Direction Register (0018H)***/
-#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018))
+#define IFXMIPS_GPIO_P0_DIR ((volatile u32 *)(IFXMIPS_GPIO+ 0x0018))
/***Port 1 Direction Register (0048H)***/
-#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048))
+#define IFXMIPS_GPIO_P1_DIR ((volatile u32 *)(IFXMIPS_GPIO+ 0x0048))
/***Port 0 Alternate Function Select Register 0 (001C H) ***/
-#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C))
+#define IFXMIPS_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFXMIPS_GPIO+ 0x001C))
/***Port 1 Alternate Function Select Register 0 (004C H) ***/
-#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C))
+#define IFXMIPS_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFXMIPS_GPIO+ 0x004C))
/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
-#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020))
+#define IFXMIPS_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFXMIPS_GPIO+ 0x0020))
/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
-#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050))
+#define IFXMIPS_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFXMIPS_GPIO+ 0x0050))
/***Port 0 Open Drain Control Register (0024H)***/
-#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024))
+#define IFXMIPS_GPIO_P0_OD ((volatile u32 *)(IFXMIPS_GPIO+ 0x0024))
/***Port 1 Open Drain Control Register (0054H)***/
-#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054))
+#define IFXMIPS_GPIO_P1_OD ((volatile u32 *)(IFXMIPS_GPIO+ 0x0054))
/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
-#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028))
+#define IFXMIPS_GPIO_P0_STOFF ((volatile u32 *)(IFXMIPS_GPIO+ 0x0028))
/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
-#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058))
+#define IFXMIPS_GPIO_P1_STOFF ((volatile u32 *)(IFXMIPS_GPIO+ 0x0058))
/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
-#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C))
+#define IFXMIPS_GPIO_P0_PUDSEL ((volatile u32 *)(IFXMIPS_GPIO+ 0x002C))
/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
-#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C))
+#define IFXMIPS_GPIO_P1_PUDSEL ((volatile u32 *)(IFXMIPS_GPIO+ 0x005C))
/***Port 0 Pull Up Device Enable Register (0030 H)***/
-#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030))
+#define IFXMIPS_GPIO_P0_PUDEN ((volatile u32 *)(IFXMIPS_GPIO+ 0x0030))
/***Port 1 Pull Up Device Enable Register (0060 H)***/
-#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060))
+#define IFXMIPS_GPIO_P1_PUDEN ((volatile u32 *)(IFXMIPS_GPIO+ 0x0060))
/***********************************************************************/
/* Module : CGU register address and bits */
/***********************************************************************/
-#define DANUBE_CGU (0xBF103000)
+#define IFXMIPS_CGU (0xBF103000)
/***********************************************************************/
/***CGU Clock PLL0 ***/
-#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004))
+#define IFXMIPS_CGU_PLL0_CFG ((volatile u32*)(IFXMIPS_CGU+ 0x0004))
/***CGU Clock PLL1 ***/
-#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008))
+#define IFXMIPS_CGU_PLL1_CFG ((volatile u32*)(IFXMIPS_CGU+ 0x0008))
/***CGU Clock SYS Mux Register***/
-#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010))
+#define IFXMIPS_CGU_SYS ((volatile u32*)(IFXMIPS_CGU+ 0x0010))
/***CGU Interface Clock Control Register***/
-#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
+#define IFXMIPS_CGU_IFCCR ((volatile u32*)(IFXMIPS_CGU+ 0x0018))
/***CGU PCI Clock Control Register**/
-#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034))
+#define IFXMIPS_CGU_PCICR ((volatile u32*)(IFXMIPS_CGU+ 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
#define CLOCK_111M 111111111
@@ -585,814 +585,814 @@
/***********************************************************************/
/* Module : MCD register address and bits */
/***********************************************************************/
-#define DANUBE_MCD (KSEG1+0x1F106000)
+#define IFXMIPS_MCD (KSEG1+0x1F106000)
/***Manufacturer Identification Register***/
-#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024))
-#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
+#define IFXMIPS_MCD_MANID ((volatile u32*)(IFXMIPS_MCD+ 0x0024))
+#define IFXMIPS_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
/***Chip Identification Register***/
-#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028))
-#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
-#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
-#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
-#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
-#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
-#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
+#define IFXMIPS_MCD_CHIPID ((volatile u32*)(IFXMIPS_MCD+ 0x0028))
+#define IFXMIPS_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
+#define IFXMIPS_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
+#define IFXMIPS_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
+#define IFXMIPS_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
-#define DANUBE_CHIPID_STANDARD 0x00EB
-#define DANUBE_CHIPID_YANGTSE 0x00ED
+#define IFXMIPS_CHIPID_STANDARD 0x00EB
+#define IFXMIPS_CHIPID_YANGTSE 0x00ED
/***Redesign Tracing Identification Register***/
-#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C))
-#define DANUBE_MCD_RTID_LC (1 << 15)
-#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_MCD_RTID ((volatile u32*)(IFXMIPS_MCD+ 0x002C))
+#define IFXMIPS_MCD_RTID_LC (1 << 15)
+#define IFXMIPS_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : EBU register address and bits */
/***********************************************************************/
-#define DANUBE_EBU (0xBE105300)
+#define IFXMIPS_EBU (0xBE105300)
/***********************************************************************/
/***EBU Clock Control Register***/
-#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000))
-#define DANUBE_EBU_CLC_DISS (1 << 1)
-#define DANUBE_EBU_CLC_DISR (1 << 0)
+#define IFXMIPS_EBU_CLC ((volatile u32*)(IFXMIPS_EBU+ 0x0000))
+#define IFXMIPS_EBU_CLC_DISS (1 << 1)
+#define IFXMIPS_EBU_CLC_DISR (1 << 0)
/***EBU Global Control Register***/
-#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010))
-#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
-#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
-#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define DANUBE_EBU_CON_ARBSYNC (1 << 5)
-#define DANUBE_EBU_CON_1 (1 << 3)
+#define IFXMIPS_EBU_CON ((volatile u32*)(IFXMIPS_EBU+ 0x0010))
+#define IFXMIPS_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
+#define IFXMIPS_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
+#define IFXMIPS_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define IFXMIPS_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define IFXMIPS_EBU_CON_ARBSYNC (1 << 5)
+#define IFXMIPS_EBU_CON_1 (1 << 3)
/***EBU Address Select Register 0***/
-#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020))
-#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1)
-#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0)
+#define IFXMIPS_EBU_ADDSEL0 ((volatile u32*)(IFXMIPS_EBU+ 0x0020))
+#define IFXMIPS_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define IFXMIPS_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_ADDSEL0_MIRRORE (1 << 1)
+#define IFXMIPS_EBU_ADDSEL0_REGEN (1 << 0)
/***EBU Address Select Register 1***/
-#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024))
-#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1)
-#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0)
+#define IFXMIPS_EBU_ADDSEL1 ((volatile u32*)(IFXMIPS_EBU+ 0x0024))
+#define IFXMIPS_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define IFXMIPS_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_ADDSEL1_MIRRORE (1 << 1)
+#define IFXMIPS_EBU_ADDSEL1_REGEN (1 << 0)
/***EBU Address Select Register 2***/
-#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028))
-#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1)
-#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0)
+#define IFXMIPS_EBU_ADDSEL2 ((volatile u32*)(IFXMIPS_EBU+ 0x0028))
+#define IFXMIPS_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define IFXMIPS_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_ADDSEL2_MIRRORE (1 << 1)
+#define IFXMIPS_EBU_ADDSEL2_REGEN (1 << 0)
/***EBU Address Select Register 3***/
-#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028))
-#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
-#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1)
-#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0)
+#define IFXMIPS_EBU_ADDSEL3 ((volatile u32*)(IFXMIPS_EBU+ 0x0028))
+#define IFXMIPS_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define IFXMIPS_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_ADDSEL3_MIRRORE (1 << 1)
+#define IFXMIPS_EBU_ADDSEL3_REGEN (1 << 0)
/***EBU Bus Configuration Register 0***/
-#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060))
-#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31)
-#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19)
-#define DANUBE_EBU_BUSCON0_SETUP (1 << 18)
-#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define IFXMIPS_EBU_BUSCON0 ((volatile u32*)(IFXMIPS_EBU+ 0x0060))
+#define IFXMIPS_EBU_BUSCON0_WRDIS (1 << 31)
+#define IFXMIPS_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define IFXMIPS_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define IFXMIPS_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define IFXMIPS_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define IFXMIPS_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define IFXMIPS_EBU_BUSCON0_WAITINV (1 << 19)
+#define IFXMIPS_EBU_BUSCON0_SETUP (1 << 18)
+#define IFXMIPS_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define IFXMIPS_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define IFXMIPS_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define IFXMIPS_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define IFXMIPS_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***EBU Bus Configuration Register 1***/
-#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064))
-#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31)
-#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19)
-#define DANUBE_EBU_BUSCON1_SETUP (1 << 18)
-#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define IFXMIPS_EBU_BUSCON1 ((volatile u32*)(IFXMIPS_EBU+ 0x0064))
+#define IFXMIPS_EBU_BUSCON1_WRDIS (1 << 31)
+#define IFXMIPS_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define IFXMIPS_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define IFXMIPS_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define IFXMIPS_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define IFXMIPS_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define IFXMIPS_EBU_BUSCON1_WAITINV (1 << 19)
+#define IFXMIPS_EBU_BUSCON1_SETUP (1 << 18)
+#define IFXMIPS_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define IFXMIPS_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define IFXMIPS_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define IFXMIPS_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define IFXMIPS_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
/***EBU Bus Configuration Register 2***/
-#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068))
-#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31)
-#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
-#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
-#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
-#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
-#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
-#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19)
-#define DANUBE_EBU_BUSCON2_SETUP (1 << 18)
-#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
-#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
-#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
-#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
-
-#define DANUBE_EBU_PCC_CON ((volatile u32*)(DANUBE_EBU+ 0x0090))
-#define DANUBE_EBU_PCC_STAT ((volatile u32*)(DANUBE_EBU+ 0x0094))
-#define DANUBE_EBU_PCC_ISTAT ((volatile u32*)(DANUBE_EBU+ 0x00A0))
-#define DANUBE_EBU_PCC_IEN ((volatile u32*)(DANUBE_EBU+ 0x00A4))
+#define IFXMIPS_EBU_BUSCON2 ((volatile u32*)(IFXMIPS_EBU+ 0x0068))
+#define IFXMIPS_EBU_BUSCON2_WRDIS (1 << 31)
+#define IFXMIPS_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define IFXMIPS_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define IFXMIPS_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define IFXMIPS_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define IFXMIPS_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define IFXMIPS_EBU_BUSCON2_WAITINV (1 << 19)
+#define IFXMIPS_EBU_BUSCON2_SETUP (1 << 18)
+#define IFXMIPS_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define IFXMIPS_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define IFXMIPS_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define IFXMIPS_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define IFXMIPS_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define IFXMIPS_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+#define IFXMIPS_EBU_PCC_CON ((volatile u32*)(IFXMIPS_EBU+ 0x0090))
+#define IFXMIPS_EBU_PCC_STAT ((volatile u32*)(IFXMIPS_EBU+ 0x0094))
+#define IFXMIPS_EBU_PCC_ISTAT ((volatile u32*)(IFXMIPS_EBU+ 0x00A0))
+#define IFXMIPS_EBU_PCC_IEN ((volatile u32*)(IFXMIPS_EBU+ 0x00A4))
/***********************************************************************/
/* Module : SDRAM register address and bits */
/***********************************************************************/
-#define DANUBE_SDRAM (0xBF800000)
+#define IFXMIPS_SDRAM (0xBF800000)
/***********************************************************************/
/***MC Access Error Cause Register***/
-#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100))
-#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
-#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
-#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
+#define IFXMIPS_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFXMIPS_SDRAM+ 0x0100))
+#define IFXMIPS_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
+#define IFXMIPS_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define IFXMIPS_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
/***MC Access Error Address Register***/
-#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108))
-#define DANUBE_SDRAM_MC_ERRADDR_ADDR
+#define IFXMIPS_SDRAM_MC_ERRADDR ((volatile u32*)(IFXMIPS_SDRAM+ 0x0108))
+#define IFXMIPS_SDRAM_MC_ERRADDR_ADDR
/***MC I/O General Purpose Register***/
-#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800))
-#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
-#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
-#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
-#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11)
-#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
-#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_IOGP ((volatile u32*)(IFXMIPS_SDRAM+ 0x0800))
+#define IFXMIPS_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
+#define IFXMIPS_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
+#define IFXMIPS_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define IFXMIPS_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define IFXMIPS_SDRAM_MC_IOGP_CPS (1 << 11)
+#define IFXMIPS_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
+#define IFXMIPS_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
/***MC Self Refresh Register***/
-#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00))
-#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
-#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0)
-#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
+#define IFXMIPS_SDRAM_MC_SELFRFSH ((volatile u32*)(IFXMIPS_SDRAM+ 0x0A00))
+#define IFXMIPS_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
+#define IFXMIPS_SDRAM_MC_SELFRFSH_PWD (1 << 0)
+#define IFXMIPS_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
/***MC Enable Register***/
-#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000))
-#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0)
-#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
+#define IFXMIPS_SDRAM_MC_CTRLENA ((volatile u32*)(IFXMIPS_SDRAM+ 0x1000))
+#define IFXMIPS_SDRAM_MC_CTRLENA_ENA (1 << 0)
+#define IFXMIPS_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
/***MC Mode Register Setup Code***/
-#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008))
-#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
-#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
-#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3)
-#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_MRSCODE ((volatile u32*)(IFXMIPS_SDRAM+ 0x1008))
+#define IFXMIPS_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
+#define IFXMIPS_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
+#define IFXMIPS_SDRAM_MC_MRSCODE_WT (1 << 3)
+#define IFXMIPS_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
/***MC Configuration Data-word Width Register***/
-#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010))
-#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
+#define IFXMIPS_SDRAM_MC_CFGDW ((volatile u32*)(IFXMIPS_SDRAM+ 0x1010))
+#define IFXMIPS_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
/***MC Configuration Physical Bank 0 Register***/
-#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018))
-#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
+#define IFXMIPS_SDRAM_MC_CFGPB0 ((volatile u32*)(IFXMIPS_SDRAM+ 0x1018))
+#define IFXMIPS_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define IFXMIPS_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
+#define IFXMIPS_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
/***MC Latency Register***/
-#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038))
-#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
-#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
-#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
-#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
+#define IFXMIPS_SDRAM_MC_LATENCY ((volatile u32*)(IFXMIPS_SDRAM+ 0x1038))
+#define IFXMIPS_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define IFXMIPS_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define IFXMIPS_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
+#define IFXMIPS_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
/***MC Refresh Cycle Time Register***/
-#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040))
-#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
-#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
+#define IFXMIPS_SDRAM_MC_TREFRESH ((volatile u32*)(IFXMIPS_SDRAM+ 0x1040))
+#define IFXMIPS_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
+#define IFXMIPS_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
/***********************************************************************/
/* Module : GPTC register address and bits */
/***********************************************************************/
-#define DANUBE_GPTC (KSEG1 + 0x1E100A00)
-#define DANUBE_GPTC_CLC ((volatile u32*) (DANUBE_GPTC + 0x0000))
-#define DANUBE_GPTC_ID ((volatile u32*) (DANUBE_GPTC + 0x0008))
-#define DANUBE_GPTC_IRNEN ((volatile u32*) (DANUBE_GPTC + 0x00F4))
-#define DANUBE_GPTC_IRNICR ((volatile u32*) (DANUBE_GPTC + 0x00F8)
-#define DANUBE_GPTC_IRNCR ((volatile u32*) (DANUBE_GPTC + 0x00FC))
+#define IFXMIPS_GPTC (KSEG1 + 0x1E100A00)
+#define IFXMIPS_GPTC_CLC ((volatile u32*) (IFXMIPS_GPTC + 0x0000))
+#define IFXMIPS_GPTC_ID ((volatile u32*) (IFXMIPS_GPTC + 0x0008))
+#define IFXMIPS_GPTC_IRNEN ((volatile u32*) (IFXMIPS_GPTC + 0x00F4))
+#define IFXMIPS_GPTC_IRNICR ((volatile u32*) (IFXMIPS_GPTC + 0x00F8)
+#define IFXMIPS_GPTC_IRNCR ((volatile u32*) (IFXMIPS_GPTC + 0x00FC))
-#define DANUBE_GPTC_CON_1A ((volatile u32*) (DANUBE_GPTC + 0x0010))
-#define DANUBE_GPTC_RUN_1A ((volatile u32*) (DANUBE_GPTC + 0x0018))
-#define DANUBE_GPTC_RELOAD_1A ((volatile u32*) (DANUBE_GPTC + 0x0020))
-#define DANUBE_GPTC_COUNT_1A ((volatile u32*) (DANUBE_GPTC + 0x0028))
+#define IFXMIPS_GPTC_CON_1A ((volatile u32*) (IFXMIPS_GPTC + 0x0010))
+#define IFXMIPS_GPTC_RUN_1A ((volatile u32*) (IFXMIPS_GPTC + 0x0018))
+#define IFXMIPS_GPTC_RELOAD_1A ((volatile u32*) (IFXMIPS_GPTC + 0x0020))
+#define IFXMIPS_GPTC_COUNT_1A ((volatile u32*) (IFXMIPS_GPTC + 0x0028))
-#define DANUBE_GPTC_CON_1B ((volatile u32*) (DANUBE_GPTC + 0x0014))
-#define DANUBE_GPTC_RUN_1B ((volatile u32*) (DANUBE_GPTC + 0x001C))
-#define DANUBE_GPTC_RELOAD_1B ((volatile u32*) (DANUBE_GPTC + 0x0024))
-#define DANUBE_GPTC_COUNT_1B ((volatile u32*) (DANUBE_GPTC + 0x002C))
+#define IFXMIPS_GPTC_CON_1B ((volatile u32*) (IFXMIPS_GPTC + 0x0014))
+#define IFXMIPS_GPTC_RUN_1B ((volatile u32*) (IFXMIPS_GPTC + 0x001C))
+#define IFXMIPS_GPTC_RELOAD_1B ((volatile u32*) (IFXMIPS_GPTC + 0x0024))
+#define IFXMIPS_GPTC_COUNT_1B ((volatile u32*) (IFXMIPS_GPTC + 0x002C))
-#define DANUBE_GPTC_CON_2A ((volatile u32*) (DANUBE_GPTC + 0x0030))
-#define DANUBE_GPTC_RUN_2A ((volatile u32*) (DANUBE_GPTC + 0x0038))
-#define DANUBE_GPTC_RELOAD_2A ((volatile u32*) (DANUBE_GPTC + 0x0040))
-#define DANUBE_GPTC_COUNT_2A ((volatile u32*) (DANUBE_GPTC + 0x0048))
+#define IFXMIPS_GPTC_CON_2A ((volatile u32*) (IFXMIPS_GPTC + 0x0030))
+#define IFXMIPS_GPTC_RUN_2A ((volatile u32*) (IFXMIPS_GPTC + 0x0038))
+#define IFXMIPS_GPTC_RELOAD_2A ((volatile u32*) (IFXMIPS_GPTC + 0x0040))
+#define IFXMIPS_GPTC_COUNT_2A ((volatile u32*) (IFXMIPS_GPTC + 0x0048))
-#define DANUBE_GPTC_CON_2B ((volatile u32*) (DANUBE_GPTC + 0x0034))
-#define DANUBE_GPTC_RUN_2B ((volatile u32*) (DANUBE_GPTC + 0x003C))
-#define DANUBE_GPTC_RELOAD_2B ((volatile u32*) (DANUBE_GPTC + 0x0044))
-#define DANUBE_GPTC_COUNT_2B ((volatile u32*) (DANUBE_GPTC + 0x004C))
+#define IFXMIPS_GPTC_CON_2B ((volatile u32*) (IFXMIPS_GPTC + 0x0034))
+#define IFXMIPS_GPTC_RUN_2B ((volatile u32*) (IFXMIPS_GPTC + 0x003C))
+#define IFXMIPS_GPTC_RELOAD_2B ((volatile u32*) (IFXMIPS_GPTC + 0x0044))
+#define IFXMIPS_GPTC_COUNT_2B ((volatile u32*) (IFXMIPS_GPTC + 0x004C))
/***********************************************************************/
/* Module : GPTU register address and bits */
/***********************************************************************/
-#define DANUBE_GPTU (0xB8000300)
+#define IFXMIPS_GPTU (0xB8000300)
/***********************************************************************/
/***GPT Clock Control Register***/
-#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000))
-#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1)
-#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0)
+#define IFXMIPS_GPTU_GPT_CLC ((volatile u32*)(IFXMIPS_GPTU+ 0x0000))
+#define IFXMIPS_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define IFXMIPS_GPTU_GPT_CLC_DISS (1 << 1)
+#define IFXMIPS_GPTU_GPT_CLC_DISR (1 << 0)
/***GPT Timer 3 Control Register***/
-#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014))
-#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15)
-#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13)
-#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10)
-#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7)
-#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6)
-#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T3CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0014))
+#define IFXMIPS_GPTU_GPT_T3CON_T3RDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_T3CON_T3EDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
+#define IFXMIPS_GPTU_GPT_T3CON_T3OTL (1 << 10)
+#define IFXMIPS_GPTU_GPT_T3CON_T3UD (1 << 7)
+#define IFXMIPS_GPTU_GPT_T3CON_T3R (1 << 6)
+#define IFXMIPS_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define IFXMIPS_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
/***GPT Write Hardware Modified Timer 3 Control Register
If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C))
-#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
-#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
-#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
-#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
-#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
+#define IFXMIPS_GPTU_GPT_WHBT3CON ((volatile u32*)(IFXMIPS_GPTU+ 0x004C))
+#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
+#define IFXMIPS_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
+#define IFXMIPS_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
/***GPT Timer 2 Control Register***/
-#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010))
-#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15)
-#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13)
-#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
-#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9)
-#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7)
-#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6)
-#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T2CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0010))
+#define IFXMIPS_GPTU_GPT_T2CON_TxRDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_T2CON_TxEDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
+#define IFXMIPS_GPTU_GPT_T2CON_TxRC (1 << 9)
+#define IFXMIPS_GPTU_GPT_T2CON_TxUD (1 << 7)
+#define IFXMIPS_GPTU_GPT_T2CON_TxR (1 << 6)
+#define IFXMIPS_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define IFXMIPS_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
/***GPT Timer 4 Control Register***/
-#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018))
-#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15)
-#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13)
-#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
-#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9)
-#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7)
-#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6)
-#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T4CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0018))
+#define IFXMIPS_GPTU_GPT_T4CON_TxRDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_T4CON_TxEDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
+#define IFXMIPS_GPTU_GPT_T4CON_TxRC (1 << 9)
+#define IFXMIPS_GPTU_GPT_T4CON_TxUD (1 << 7)
+#define IFXMIPS_GPTU_GPT_T4CON_TxR (1 << 6)
+#define IFXMIPS_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define IFXMIPS_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
/***GPT Write HW Modified Timer 2 Control Register If set
and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048))
-#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
-#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
-#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
+#define IFXMIPS_GPTU_GPT_WHBT2CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0048))
+#define IFXMIPS_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
/***GPT Write HW Modified Timer 4 Control Register If set
and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050))
-#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
-#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
-#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
-#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
+#define IFXMIPS_GPTU_GPT_WHBT4CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0050))
+#define IFXMIPS_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
+#define IFXMIPS_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
+#define IFXMIPS_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
+#define IFXMIPS_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
/***GPT Capture Reload Register***/
-#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030))
-#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_CAPREL ((volatile u32*)(IFXMIPS_GPTU+ 0x0030))
+#define IFXMIPS_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 2 Register***/
-#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034))
-#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T2 ((volatile u32*)(IFXMIPS_GPTU+ 0x0034))
+#define IFXMIPS_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 3 Register***/
-#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038))
-#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T3 ((volatile u32*)(IFXMIPS_GPTU+ 0x0038))
+#define IFXMIPS_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 4 Register***/
-#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C))
-#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T4 ((volatile u32*)(IFXMIPS_GPTU+ 0x003C))
+#define IFXMIPS_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 5 Register***/
-#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040))
-#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T5 ((volatile u32*)(IFXMIPS_GPTU+ 0x0040))
+#define IFXMIPS_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 6 Register***/
-#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044))
-#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T6 ((volatile u32*)(IFXMIPS_GPTU+ 0x0044))
+#define IFXMIPS_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
/***GPT Timer 6 Control Register***/
-#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020))
-#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15)
-#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14)
-#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
-#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10)
-#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7)
-#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6)
-#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T6CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0020))
+#define IFXMIPS_GPTU_GPT_T6CON_T6SR (1 << 15)
+#define IFXMIPS_GPTU_GPT_T6CON_T6CLR (1 << 14)
+#define IFXMIPS_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
+#define IFXMIPS_GPTU_GPT_T6CON_T6OTL (1 << 10)
+#define IFXMIPS_GPTU_GPT_T6CON_T6UD (1 << 7)
+#define IFXMIPS_GPTU_GPT_T6CON_T6R (1 << 6)
+#define IFXMIPS_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define IFXMIPS_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
/***GPT Write HW Modified Timer 6 Control Register If set
and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054))
-#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
-#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
+#define IFXMIPS_GPTU_GPT_WHBT6CON ((volatile u32*)(IFXMIPS_GPTU+ 0x0054))
+#define IFXMIPS_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
+#define IFXMIPS_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
/***GPT Timer 5 Control Register***/
-#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C))
-#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15)
-#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14)
-#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
-#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11)
-#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10)
-#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9)
-#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8)
-#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7)
-#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6)
-#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
-#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_GPTU_GPT_T5CON ((volatile u32*)(IFXMIPS_GPTU+ 0x001C))
+#define IFXMIPS_GPTU_GPT_T5CON_T5SC (1 << 15)
+#define IFXMIPS_GPTU_GPT_T5CON_T5CLR (1 << 14)
+#define IFXMIPS_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
+#define IFXMIPS_GPTU_GPT_T5CON_T5CC (1 << 11)
+#define IFXMIPS_GPTU_GPT_T5CON_CT3 (1 << 10)
+#define IFXMIPS_GPTU_GPT_T5CON_T5RC (1 << 9)
+#define IFXMIPS_GPTU_GPT_T5CON_T5UDE (1 << 8)
+#define IFXMIPS_GPTU_GPT_T5CON_T5UD (1 << 7)
+#define IFXMIPS_GPTU_GPT_T5CON_T5R (1 << 6)
+#define IFXMIPS_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define IFXMIPS_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : IOM register address and bits */
/***********************************************************************/
-#define DANUBE_IOM (0xBF105000)
+#define IFXMIPS_IOM (0xBF105000)
/***********************************************************************/
/***Receive FIFO***/
-#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
-#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_RFIFO ((volatile u32*)(IFXMIPS_IOM+ 0x0000))
+#define IFXMIPS_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Transmit FIFO***/
-#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
-#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_XFIFO ((volatile u32*)(IFXMIPS_IOM+ 0x0000))
+#define IFXMIPS_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Interrupt Status Register HDLC***/
-#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080))
-#define DANUBE_IOM_ISTAH_RME (1 << 7)
-#define DANUBE_IOM_ISTAH_RPF (1 << 6)
-#define DANUBE_IOM_ISTAH_RFO (1 << 5)
-#define DANUBE_IOM_ISTAH_XPR (1 << 4)
-#define DANUBE_IOM_ISTAH_XMR (1 << 3)
-#define DANUBE_IOM_ISTAH_XDU (1 << 2)
+#define IFXMIPS_IOM_ISTAH ((volatile u32*)(IFXMIPS_IOM+ 0x0080))
+#define IFXMIPS_IOM_ISTAH_RME (1 << 7)
+#define IFXMIPS_IOM_ISTAH_RPF (1 << 6)
+#define IFXMIPS_IOM_ISTAH_RFO (1 << 5)
+#define IFXMIPS_IOM_ISTAH_XPR (1 << 4)
+#define IFXMIPS_IOM_ISTAH_XMR (1 << 3)
+#define IFXMIPS_IOM_ISTAH_XDU (1 << 2)
/***Interrupt Mask Register HDLC***/
-#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080))
-#define DANUBE_IOM_MASKH_RME (1 << 7)
-#define DANUBE_IOM_MASKH_RPF (1 << 6)
-#define DANUBE_IOM_MASKH_RFO (1 << 5)
-#define DANUBE_IOM_MASKH_XPR (1 << 4)
-#define DANUBE_IOM_MASKH_XMR (1 << 3)
-#define DANUBE_IOM_MASKH_XDU (1 << 2)
+#define IFXMIPS_IOM_MASKH ((volatile u32*)(IFXMIPS_IOM+ 0x0080))
+#define IFXMIPS_IOM_MASKH_RME (1 << 7)
+#define IFXMIPS_IOM_MASKH_RPF (1 << 6)
+#define IFXMIPS_IOM_MASKH_RFO (1 << 5)
+#define IFXMIPS_IOM_MASKH_XPR (1 << 4)
+#define IFXMIPS_IOM_MASKH_XMR (1 << 3)
+#define IFXMIPS_IOM_MASKH_XDU (1 << 2)
/***Status Register***/
-#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084))
-#define DANUBE_IOM_STAR_XDOV (1 << 7)
-#define DANUBE_IOM_STAR_XFW (1 << 6)
-#define DANUBE_IOM_STAR_RACI (1 << 3)
-#define DANUBE_IOM_STAR_XACI (1 << 1)
+#define IFXMIPS_IOM_STAR ((volatile u32*)(IFXMIPS_IOM+ 0x0084))
+#define IFXMIPS_IOM_STAR_XDOV (1 << 7)
+#define IFXMIPS_IOM_STAR_XFW (1 << 6)
+#define IFXMIPS_IOM_STAR_RACI (1 << 3)
+#define IFXMIPS_IOM_STAR_XACI (1 << 1)
/***Command Register***/
-#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084))
-#define DANUBE_IOM_CMDR_RMC (1 << 7)
-#define DANUBE_IOM_CMDR_RRES (1 << 6)
-#define DANUBE_IOM_CMDR_XTF (1 << 3)
-#define DANUBE_IOM_CMDR_XME (1 << 1)
-#define DANUBE_IOM_CMDR_XRES (1 << 0)
+#define IFXMIPS_IOM_CMDR ((volatile u32*)(IFXMIPS_IOM+ 0x0084))
+#define IFXMIPS_IOM_CMDR_RMC (1 << 7)
+#define IFXMIPS_IOM_CMDR_RRES (1 << 6)
+#define IFXMIPS_IOM_CMDR_XTF (1 << 3)
+#define IFXMIPS_IOM_CMDR_XME (1 << 1)
+#define IFXMIPS_IOM_CMDR_XRES (1 << 0)
/***Mode Register***/
-#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088))
-#define DANUBE_IOM_MODEH_MDS2 (1 << 7)
-#define DANUBE_IOM_MODEH_MDS1 (1 << 6)
-#define DANUBE_IOM_MODEH_MDS0 (1 << 5)
-#define DANUBE_IOM_MODEH_RAC (1 << 3)
-#define DANUBE_IOM_MODEH_DIM2 (1 << 2)
-#define DANUBE_IOM_MODEH_DIM1 (1 << 1)
-#define DANUBE_IOM_MODEH_DIM0 (1 << 0)
+#define IFXMIPS_IOM_MODEH ((volatile u32*)(IFXMIPS_IOM+ 0x0088))
+#define IFXMIPS_IOM_MODEH_MDS2 (1 << 7)
+#define IFXMIPS_IOM_MODEH_MDS1 (1 << 6)
+#define IFXMIPS_IOM_MODEH_MDS0 (1 << 5)
+#define IFXMIPS_IOM_MODEH_RAC (1 << 3)
+#define IFXMIPS_IOM_MODEH_DIM2 (1 << 2)
+#define IFXMIPS_IOM_MODEH_DIM1 (1 << 1)
+#define IFXMIPS_IOM_MODEH_DIM0 (1 << 0)
/***Extended Mode Register***/
-#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C))
-#define DANUBE_IOM_EXMR_XFBS (1 << 7)
-#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
-#define DANUBE_IOM_EXMR_SRA (1 << 4)
-#define DANUBE_IOM_EXMR_XCRC (1 << 3)
-#define DANUBE_IOM_EXMR_RCRC (1 << 2)
-#define DANUBE_IOM_EXMR_ITF (1 << 0)
+#define IFXMIPS_IOM_EXMR ((volatile u32*)(IFXMIPS_IOM+ 0x008C))
+#define IFXMIPS_IOM_EXMR_XFBS (1 << 7)
+#define IFXMIPS_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
+#define IFXMIPS_IOM_EXMR_SRA (1 << 4)
+#define IFXMIPS_IOM_EXMR_XCRC (1 << 3)
+#define IFXMIPS_IOM_EXMR_RCRC (1 << 2)
+#define IFXMIPS_IOM_EXMR_ITF (1 << 0)
/***SAPI1 Register***/
-#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094))
-#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define DANUBE_IOM_SAP1_MHA (1 << 0)
+#define IFXMIPS_IOM_SAP1 ((volatile u32*)(IFXMIPS_IOM+ 0x0094))
+#define IFXMIPS_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define IFXMIPS_IOM_SAP1_MHA (1 << 0)
/***Receive Frame Byte Count Low***/
-#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098))
-#define DANUBE_IOM_RBCL_RBC(value) (1 << value)
+#define IFXMIPS_IOM_RBCL ((volatile u32*)(IFXMIPS_IOM+ 0x0098))
+#define IFXMIPS_IOM_RBCL_RBC(value) (1 << value)
/***SAPI2 Register***/
-#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098))
-#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define DANUBE_IOM_SAP2_MLA (1 << 0)
+#define IFXMIPS_IOM_SAP2 ((volatile u32*)(IFXMIPS_IOM+ 0x0098))
+#define IFXMIPS_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define IFXMIPS_IOM_SAP2_MLA (1 << 0)
/***Receive Frame Byte Count High***/
-#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C))
-#define DANUBE_IOM_RBCH_OV (1 << 4)
-#define DANUBE_IOM_RBCH_RBC11 (1 << 3)
-#define DANUBE_IOM_RBCH_RBC10 (1 << 2)
-#define DANUBE_IOM_RBCH_RBC9 (1 << 1)
-#define DANUBE_IOM_RBCH_RBC8 (1 << 0)
+#define IFXMIPS_IOM_RBCH ((volatile u32*)(IFXMIPS_IOM+ 0x009C))
+#define IFXMIPS_IOM_RBCH_OV (1 << 4)
+#define IFXMIPS_IOM_RBCH_RBC11 (1 << 3)
+#define IFXMIPS_IOM_RBCH_RBC10 (1 << 2)
+#define IFXMIPS_IOM_RBCH_RBC9 (1 << 1)
+#define IFXMIPS_IOM_RBCH_RBC8 (1 << 0)
/***TEI1 Register 1***/
-#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C))
-#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define DANUBE_IOM_TEI1_EA (1 << 0)
+#define IFXMIPS_IOM_TEI1 ((volatile u32*)(IFXMIPS_IOM+ 0x009C))
+#define IFXMIPS_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
+#define IFXMIPS_IOM_TEI1_EA (1 << 0)
/***Receive Status Register***/
-#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0))
-#define DANUBE_IOM_RSTA_VFR (1 << 7)
-#define DANUBE_IOM_RSTA_RDO (1 << 6)
-#define DANUBE_IOM_RSTA_CRC (1 << 5)
-#define DANUBE_IOM_RSTA_RAB (1 << 4)
-#define DANUBE_IOM_RSTA_SA1 (1 << 3)
-#define DANUBE_IOM_RSTA_SA0 (1 << 2)
-#define DANUBE_IOM_RSTA_TA (1 << 0)
-#define DANUBE_IOM_RSTA_CR (1 << 1)
+#define IFXMIPS_IOM_RSTA ((volatile u32*)(IFXMIPS_IOM+ 0x00A0))
+#define IFXMIPS_IOM_RSTA_VFR (1 << 7)
+#define IFXMIPS_IOM_RSTA_RDO (1 << 6)
+#define IFXMIPS_IOM_RSTA_CRC (1 << 5)
+#define IFXMIPS_IOM_RSTA_RAB (1 << 4)
+#define IFXMIPS_IOM_RSTA_SA1 (1 << 3)
+#define IFXMIPS_IOM_RSTA_SA0 (1 << 2)
+#define IFXMIPS_IOM_RSTA_TA (1 << 0)
+#define IFXMIPS_IOM_RSTA_CR (1 << 1)
/***TEI2 Register***/
-#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0))
-#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
-#define DANUBE_IOM_TEI2_EA (1 << 0)
+#define IFXMIPS_IOM_TEI2 ((volatile u32*)(IFXMIPS_IOM+ 0x00A0))
+#define IFXMIPS_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
+#define IFXMIPS_IOM_TEI2_EA (1 << 0)
/***Test Mode Register HDLC***/
-#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4))
-#define DANUBE_IOM_TMH_TLP (1 << 0)
+#define IFXMIPS_IOM_TMH ((volatile u32*)(IFXMIPS_IOM+ 0x00A4))
+#define IFXMIPS_IOM_TMH_TLP (1 << 0)
/***Command/Indication Receive 0***/
-#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
-#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_IOM_CIR0_CIC0 (1 << 3)
-#define DANUBE_IOM_CIR0_CIC1 (1 << 2)
-#define DANUBE_IOM_CIR0_SG (1 << 1)
-#define DANUBE_IOM_CIR0_BAS (1 << 0)
+#define IFXMIPS_IOM_CIR0 ((volatile u32*)(IFXMIPS_IOM+ 0x00B8))
+#define IFXMIPS_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_IOM_CIR0_CIC0 (1 << 3)
+#define IFXMIPS_IOM_CIR0_CIC1 (1 << 2)
+#define IFXMIPS_IOM_CIR0_SG (1 << 1)
+#define IFXMIPS_IOM_CIR0_BAS (1 << 0)
/***Command/Indication Transmit 0***/
-#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
-#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
-#define DANUBE_IOM_CIX0_TBA2 (1 << 3)
-#define DANUBE_IOM_CIX0_TBA1 (1 << 2)
-#define DANUBE_IOM_CIX0_TBA0 (1 << 1)
-#define DANUBE_IOM_CIX0_BAC (1 << 0)
+#define IFXMIPS_IOM_CIX0 ((volatile u32*)(IFXMIPS_IOM+ 0x00B8))
+#define IFXMIPS_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define IFXMIPS_IOM_CIX0_TBA2 (1 << 3)
+#define IFXMIPS_IOM_CIX0_TBA1 (1 << 2)
+#define IFXMIPS_IOM_CIX0_TBA0 (1 << 1)
+#define IFXMIPS_IOM_CIX0_BAC (1 << 0)
/***Command/Indication Receive 1***/
-#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
-#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define IFXMIPS_IOM_CIR1 ((volatile u32*)(IFXMIPS_IOM+ 0x00BC))
+#define IFXMIPS_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
/***Command/Indication Transmit 1***/
-#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
-#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
-#define DANUBE_IOM_CIX1_CICW (1 << 1)
-#define DANUBE_IOM_CIX1_CI1E (1 << 0)
+#define IFXMIPS_IOM_CIX1 ((volatile u32*)(IFXMIPS_IOM+ 0x00BC))
+#define IFXMIPS_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define IFXMIPS_IOM_CIX1_CICW (1 << 1)
+#define IFXMIPS_IOM_CIX1_CI1E (1 << 0)
/***Controller Data Access Reg. (CH10)***/
-#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100))
-#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA10 ((volatile u32*)(IFXMIPS_IOM+ 0x0100))
+#define IFXMIPS_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Controller Data Access Reg. (CH11)***/
-#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104))
-#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA11 ((volatile u32*)(IFXMIPS_IOM+ 0x0104))
+#define IFXMIPS_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Controller Data Access Reg. (CH20)***/
-#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108))
-#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA20 ((volatile u32*)(IFXMIPS_IOM+ 0x0108))
+#define IFXMIPS_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Controller Data Access Reg. (CH21)***/
-#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C))
-#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA21 ((volatile u32*)(IFXMIPS_IOM+ 0x010C))
+#define IFXMIPS_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH10)***/
-#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110))
-#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7)
-#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA_TSDP10 ((volatile u32*)(IFXMIPS_IOM+ 0x0110))
+#define IFXMIPS_IOM_CDA_TSDP10_DPS (1 << 7)
+#define IFXMIPS_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH11)***/
-#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114))
-#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7)
-#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA_TSDP11 ((volatile u32*)(IFXMIPS_IOM+ 0x0114))
+#define IFXMIPS_IOM_CDA_TSDP11_DPS (1 << 7)
+#define IFXMIPS_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH20)***/
-#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118))
-#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7)
-#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA_TSDP20 ((volatile u32*)(IFXMIPS_IOM+ 0x0118))
+#define IFXMIPS_IOM_CDA_TSDP20_DPS (1 << 7)
+#define IFXMIPS_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH21)***/
-#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C))
-#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7)
-#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CDA_TSDP21 ((volatile u32*)(IFXMIPS_IOM+ 0x011C))
+#define IFXMIPS_IOM_CDA_TSDP21_DPS (1 << 7)
+#define IFXMIPS_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH10)***/
-#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120))
-#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7)
-#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CO_TSDP10 ((volatile u32*)(IFXMIPS_IOM+ 0x0120))
+#define IFXMIPS_IOM_CO_TSDP10_DPS (1 << 7)
+#define IFXMIPS_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH11)***/
-#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124))
-#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7)
-#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CO_TSDP11 ((volatile u32*)(IFXMIPS_IOM+ 0x0124))
+#define IFXMIPS_IOM_CO_TSDP11_DPS (1 << 7)
+#define IFXMIPS_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH20)***/
-#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128))
-#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7)
-#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CO_TSDP20 ((volatile u32*)(IFXMIPS_IOM+ 0x0128))
+#define IFXMIPS_IOM_CO_TSDP20_DPS (1 << 7)
+#define IFXMIPS_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Time Slot and Data Port Sel. (CH21)***/
-#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C))
-#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7)
-#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_CO_TSDP21 ((volatile u32*)(IFXMIPS_IOM+ 0x012C))
+#define IFXMIPS_IOM_CO_TSDP21_DPS (1 << 7)
+#define IFXMIPS_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138))
-#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5)
-#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4)
-#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3)
-#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2)
-#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1)
-#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0)
+#define IFXMIPS_IOM_CDA1_CR ((volatile u32*)(IFXMIPS_IOM+ 0x0138))
+#define IFXMIPS_IOM_CDA1_CR_EN_TBM (1 << 5)
+#define IFXMIPS_IOM_CDA1_CR_EN_I1 (1 << 4)
+#define IFXMIPS_IOM_CDA1_CR_EN_I0 (1 << 3)
+#define IFXMIPS_IOM_CDA1_CR_EN_O1 (1 << 2)
+#define IFXMIPS_IOM_CDA1_CR_EN_O0 (1 << 1)
+#define IFXMIPS_IOM_CDA1_CR_SWAP (1 << 0)
/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C))
-#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5)
-#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4)
-#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3)
-#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2)
-#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1)
-#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0)
+#define IFXMIPS_IOM_CDA2_CR ((volatile u32*)(IFXMIPS_IOM+ 0x013C))
+#define IFXMIPS_IOM_CDA2_CR_EN_TBM (1 << 5)
+#define IFXMIPS_IOM_CDA2_CR_EN_I1 (1 << 4)
+#define IFXMIPS_IOM_CDA2_CR_EN_I0 (1 << 3)
+#define IFXMIPS_IOM_CDA2_CR_EN_O1 (1 << 2)
+#define IFXMIPS_IOM_CDA2_CR_EN_O0 (1 << 1)
+#define IFXMIPS_IOM_CDA2_CR_SWAP (1 << 0)
/***Control Register B-Channel Data***/
-#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144))
-#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4)
-#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3)
+#define IFXMIPS_IOM_BCHA_CR ((volatile u32*)(IFXMIPS_IOM+ 0x0144))
+#define IFXMIPS_IOM_BCHA_CR_EN_BC2 (1 << 4)
+#define IFXMIPS_IOM_BCHA_CR_EN_BC1 (1 << 3)
/***Control Register B-Channel Data***/
-#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148))
-#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4)
-#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3)
+#define IFXMIPS_IOM_BCHB_CR ((volatile u32*)(IFXMIPS_IOM+ 0x0148))
+#define IFXMIPS_IOM_BCHB_CR_EN_BC2 (1 << 4)
+#define IFXMIPS_IOM_BCHB_CR_EN_BC1 (1 << 3)
/***Control Reg. for HDLC and CI1 Data***/
-#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
-#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7)
-#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6)
-#define DANUBE_IOM_DCI_CR_EN_D (1 << 5)
+#define IFXMIPS_IOM_DCI_CR ((volatile u32*)(IFXMIPS_IOM+ 0x014C))
+#define IFXMIPS_IOM_DCI_CR_DPS_CI1 (1 << 7)
+#define IFXMIPS_IOM_DCI_CR_EN_CI1 (1 << 6)
+#define IFXMIPS_IOM_DCI_CR_EN_D (1 << 5)
/***Control Reg. for HDLC and CI1 Data***/
-#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
-#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7)
-#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6)
-#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5)
+#define IFXMIPS_IOM_DCIC_CR ((volatile u32*)(IFXMIPS_IOM+ 0x014C))
+#define IFXMIPS_IOM_DCIC_CR_DPS_CI0 (1 << 7)
+#define IFXMIPS_IOM_DCIC_CR_EN_CI0 (1 << 6)
+#define IFXMIPS_IOM_DCIC_CR_DPS_D (1 << 5)
/***Control Reg. Serial Data Strobe x***/
-#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154))
-#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7)
-#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
-#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
-#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_SDS_CR ((volatile u32*)(IFXMIPS_IOM+ 0x0154))
+#define IFXMIPS_IOM_SDS_CR_ENS_TSS (1 << 7)
+#define IFXMIPS_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
+#define IFXMIPS_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
+#define IFXMIPS_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
/***Control Register IOM Data***/
-#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C))
-#define DANUBE_IOM_IOM_CR_SPU (1 << 7)
-#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5)
-#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4)
-#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3)
-#define DANUBE_IOM_IOM_CR_CLKM (1 << 2)
-#define DANUBE_IOM_IOM_CR_Res (1 << 1)
-#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0)
+#define IFXMIPS_IOM_IOM_CR ((volatile u32*)(IFXMIPS_IOM+ 0x015C))
+#define IFXMIPS_IOM_IOM_CR_SPU (1 << 7)
+#define IFXMIPS_IOM_IOM_CR_CI_CS (1 << 5)
+#define IFXMIPS_IOM_IOM_CR_TIC_DIS (1 << 4)
+#define IFXMIPS_IOM_IOM_CR_EN_BCL (1 << 3)
+#define IFXMIPS_IOM_IOM_CR_CLKM (1 << 2)
+#define IFXMIPS_IOM_IOM_CR_Res (1 << 1)
+#define IFXMIPS_IOM_IOM_CR_DIS_IOM (1 << 0)
/***Synchronous Transfer Interrupt***/
-#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160))
-#define DANUBE_IOM_STI_STOV21 (1 << 7)
-#define DANUBE_IOM_STI_STOV20 (1 << 6)
-#define DANUBE_IOM_STI_STOV11 (1 << 5)
-#define DANUBE_IOM_STI_STOV10 (1 << 4)
-#define DANUBE_IOM_STI_STI21 (1 << 3)
-#define DANUBE_IOM_STI_STI20 (1 << 2)
-#define DANUBE_IOM_STI_STI11 (1 << 1)
-#define DANUBE_IOM_STI_STI10 (1 << 0)
+#define IFXMIPS_IOM_STI ((volatile u32*)(IFXMIPS_IOM+ 0x0160))
+#define IFXMIPS_IOM_STI_STOV21 (1 << 7)
+#define IFXMIPS_IOM_STI_STOV20 (1 << 6)
+#define IFXMIPS_IOM_STI_STOV11 (1 << 5)
+#define IFXMIPS_IOM_STI_STOV10 (1 << 4)
+#define IFXMIPS_IOM_STI_STI21 (1 << 3)
+#define IFXMIPS_IOM_STI_STI20 (1 << 2)
+#define IFXMIPS_IOM_STI_STI11 (1 << 1)
+#define IFXMIPS_IOM_STI_STI10 (1 << 0)
/***Acknowledge Synchronous Transfer Interrupt***/
-#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160))
-#define DANUBE_IOM_ASTI_ACK21 (1 << 3)
-#define DANUBE_IOM_ASTI_ACK20 (1 << 2)
-#define DANUBE_IOM_ASTI_ACK11 (1 << 1)
-#define DANUBE_IOM_ASTI_ACK10 (1 << 0)
+#define IFXMIPS_IOM_ASTI ((volatile u32*)(IFXMIPS_IOM+ 0x0160))
+#define IFXMIPS_IOM_ASTI_ACK21 (1 << 3)
+#define IFXMIPS_IOM_ASTI_ACK20 (1 << 2)
+#define IFXMIPS_IOM_ASTI_ACK11 (1 << 1)
+#define IFXMIPS_IOM_ASTI_ACK10 (1 << 0)
/***Mask Synchronous Transfer Interrupt***/
-#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164))
-#define DANUBE_IOM_MSTI_STOV21 (1 << 7)
-#define DANUBE_IOM_MSTI_STOV20 (1 << 6)
-#define DANUBE_IOM_MSTI_STOV11 (1 << 5)
-#define DANUBE_IOM_MSTI_STOV10 (1 << 4)
-#define DANUBE_IOM_MSTI_STI21 (1 << 3)
-#define DANUBE_IOM_MSTI_STI20 (1 << 2)
-#define DANUBE_IOM_MSTI_STI11 (1 << 1)
-#define DANUBE_IOM_MSTI_STI10 (1 << 0)
+#define IFXMIPS_IOM_MSTI ((volatile u32*)(IFXMIPS_IOM+ 0x0164))
+#define IFXMIPS_IOM_MSTI_STOV21 (1 << 7)
+#define IFXMIPS_IOM_MSTI_STOV20 (1 << 6)
+#define IFXMIPS_IOM_MSTI_STOV11 (1 << 5)
+#define IFXMIPS_IOM_MSTI_STOV10 (1 << 4)
+#define IFXMIPS_IOM_MSTI_STI21 (1 << 3)
+#define IFXMIPS_IOM_MSTI_STI20 (1 << 2)
+#define IFXMIPS_IOM_MSTI_STI11 (1 << 1)
+#define IFXMIPS_IOM_MSTI_STI10 (1 << 0)
/***Configuration Register for Serial Data Strobes***/
-#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168))
-#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0)
+#define IFXMIPS_IOM_SDS_CONF ((volatile u32*)(IFXMIPS_IOM+ 0x0168))
+#define IFXMIPS_IOM_SDS_CONF_SDS_BCL (1 << 0)
/***Monitoring CDA Bits***/
-#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C))
-#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
-#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
-#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
-#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define IFXMIPS_IOM_MCDA ((volatile u32*)(IFXMIPS_IOM+ 0x016C))
+#define IFXMIPS_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define IFXMIPS_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define IFXMIPS_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define IFXMIPS_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : ASC0 register address and bits */
/***********************************************************************/
-#define DANUBE_ASC0 (KSEG1+0x1E100400)
+#define IFXMIPS_ASC0 (KSEG1+0x1E100400)
/***********************************************************************/
-#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020))
-#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024))
-#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048))
-#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
-#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
-#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
-#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
-#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
-#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
-#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+#define IFXMIPS_ASC0_TBUF ((volatile u32*)(IFXMIPS_ASC0 + 0x0020))
+#define IFXMIPS_ASC0_RBUF ((volatile u32*)(IFXMIPS_ASC0 + 0x0024))
+#define IFXMIPS_ASC0_FSTAT ((volatile u32*)(IFXMIPS_ASC0 + 0x0048))
+#define IFXMIPS_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define IFXMIPS_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define IFXMIPS_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define IFXMIPS_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define IFXMIPS_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define IFXMIPS_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define IFXMIPS_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : ASC1 register address and bits */
/***********************************************************************/
-#define DANUBE_ASC1 (KSEG1+0x1E100C00)
+#define IFXMIPS_ASC1 (KSEG1+0x1E100C00)
/***********************************************************************/
/***ASC Clock Control Register***/
-#define DANUBE_ASC1_CLC ((volatile u32*)(DANUBE_ASC1+ 0x0000))
-#define DANUBE_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
-#define DANUBE_ASC1_CLC_DISS (1 << 1)
-#define DANUBE_ASC1_CLC_DISR (1 << 0)
+#define IFXMIPS_ASC1_CLC ((volatile u32*)(IFXMIPS_ASC1+ 0x0000))
+#define IFXMIPS_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_CLC_DISS (1 << 1)
+#define IFXMIPS_ASC1_CLC_DISR (1 << 0)
/***ASC Port Input Select Register***/
-#define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004))
-#define DANUBE_ASC1_PISEL ((volatile u32*)(DANUBE_ASC1+ 0x0004))
-#define DANUBE_ASC1_PISEL_RIS (1 << 0)
+#define IFXMIPS_ASC1_PISEL ((volatile u32*)(IFXMIPS_ASC1+ 0x0004))
+#define IFXMIPS_ASC1_PISEL ((volatile u32*)(IFXMIPS_ASC1+ 0x0004))
+#define IFXMIPS_ASC1_PISEL_RIS (1 << 0)
/***ASC Control Register***/
-#define DANUBE_ASC1_CON ((volatile u32*)(DANUBE_ASC1+ 0x0010))
-#define DANUBE_ASC1_CON_BEN (1 << 20)
-#define DANUBE_ASC1_CON_TOEN (1 << 20)
-#define DANUBE_ASC1_CON_ROEN (1 << 19)
-#define DANUBE_ASC1_CON_RUEN (1 << 18)
-#define DANUBE_ASC1_CON_FEN (1 << 17)
-#define DANUBE_ASC1_CON_PAL (1 << 16)
-#define DANUBE_ASC1_CON_R (1 << 15)
-#define DANUBE_ASC1_CON_ACO (1 << 14)
-#define DANUBE_ASC1_CON_LB (1 << 13)
-#define DANUBE_ASC1_CON_ERCLK (1 << 10)
-#define DANUBE_ASC1_CON_FDE (1 << 9)
-#define DANUBE_ASC1_CON_BRS (1 << 8)
-#define DANUBE_ASC1_CON_STP (1 << 7)
-#define DANUBE_ASC1_CON_SP (1 << 6)
-#define DANUBE_ASC1_CON_ODD (1 << 5)
-#define DANUBE_ASC1_CON_PEN (1 << 4)
-#define DANUBE_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_CON ((volatile u32*)(IFXMIPS_ASC1+ 0x0010))
+#define IFXMIPS_ASC1_CON_BEN (1 << 20)
+#define IFXMIPS_ASC1_CON_TOEN (1 << 20)
+#define IFXMIPS_ASC1_CON_ROEN (1 << 19)
+#define IFXMIPS_ASC1_CON_RUEN (1 << 18)
+#define IFXMIPS_ASC1_CON_FEN (1 << 17)
+#define IFXMIPS_ASC1_CON_PAL (1 << 16)
+#define IFXMIPS_ASC1_CON_R (1 << 15)
+#define IFXMIPS_ASC1_CON_ACO (1 << 14)
+#define IFXMIPS_ASC1_CON_LB (1 << 13)
+#define IFXMIPS_ASC1_CON_ERCLK (1 << 10)
+#define IFXMIPS_ASC1_CON_FDE (1 << 9)
+#define IFXMIPS_ASC1_CON_BRS (1 << 8)
+#define IFXMIPS_ASC1_CON_STP (1 << 7)
+#define IFXMIPS_ASC1_CON_SP (1 << 6)
+#define IFXMIPS_ASC1_CON_ODD (1 << 5)
+#define IFXMIPS_ASC1_CON_PEN (1 << 4)
+#define IFXMIPS_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0)
/***ASC Staus Register***/
-#define DANUBE_ASC1_STATE ((volatile u32*)(DANUBE_ASC1+ 0x0014))
+#define IFXMIPS_ASC1_STATE ((volatile u32*)(IFXMIPS_ASC1+ 0x0014))
/***ASC Write Hardware Modified Control Register***/
-#define DANUBE_ASC1_WHBSTATE ((volatile u32*)(DANUBE_ASC1+ 0x0018))
-#define DANUBE_ASC1_WHBSTATE_SETBE (1 << 113)
-#define DANUBE_ASC1_WHBSTATE_SETTOE (1 << 12)
-#define DANUBE_ASC1_WHBSTATE_SETROE (1 << 11)
-#define DANUBE_ASC1_WHBSTATE_SETRUE (1 << 10)
-#define DANUBE_ASC1_WHBSTATE_SETFE (1 << 19)
-#define DANUBE_ASC1_WHBSTATE_SETPE (1 << 18)
-#define DANUBE_ASC1_WHBSTATE_CLRBE (1 << 17)
-#define DANUBE_ASC1_WHBSTATE_CLRTOE (1 << 6)
-#define DANUBE_ASC1_WHBSTATE_CLRROE (1 << 5)
-#define DANUBE_ASC1_WHBSTATE_CLRRUE (1 << 4)
-#define DANUBE_ASC1_WHBSTATE_CLRFE (1 << 3)
-#define DANUBE_ASC1_WHBSTATE_CLRPE (1 << 2)
-#define DANUBE_ASC1_WHBSTATE_SETREN (1 << 1)
-#define DANUBE_ASC1_WHBSTATE_CLRREN (1 << 0)
+#define IFXMIPS_ASC1_WHBSTATE ((volatile u32*)(IFXMIPS_ASC1+ 0x0018))
+#define IFXMIPS_ASC1_WHBSTATE_SETBE (1 << 113)
+#define IFXMIPS_ASC1_WHBSTATE_SETTOE (1 << 12)
+#define IFXMIPS_ASC1_WHBSTATE_SETROE (1 << 11)
+#define IFXMIPS_ASC1_WHBSTATE_SETRUE (1 << 10)
+#define IFXMIPS_ASC1_WHBSTATE_SETFE (1 << 19)
+#define IFXMIPS_ASC1_WHBSTATE_SETPE (1 << 18)
+#define IFXMIPS_ASC1_WHBSTATE_CLRBE (1 << 17)
+#define IFXMIPS_ASC1_WHBSTATE_CLRTOE (1 << 6)
+#define IFXMIPS_ASC1_WHBSTATE_CLRROE (1 << 5)
+#define IFXMIPS_ASC1_WHBSTATE_CLRRUE (1 << 4)
+#define IFXMIPS_ASC1_WHBSTATE_CLRFE (1 << 3)
+#define IFXMIPS_ASC1_WHBSTATE_CLRPE (1 << 2)
+#define IFXMIPS_ASC1_WHBSTATE_SETREN (1 << 1)
+#define IFXMIPS_ASC1_WHBSTATE_CLRREN (1 << 0)
/***ASC Baudrate Timer/Reload Register***/
-#define DANUBE_ASC1_BG ((volatile u32*)(DANUBE_ASC1+ 0x0050))
-#define DANUBE_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_BG ((volatile u32*)(IFXMIPS_ASC1+ 0x0050))
+#define IFXMIPS_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0)
/***ASC Fractional Divider Register***/
-#define DANUBE_ASC1_FDV ((volatile u32*)(DANUBE_ASC1+ 0x0018))
-#define DANUBE_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_FDV ((volatile u32*)(IFXMIPS_ASC1+ 0x0018))
+#define IFXMIPS_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
/***ASC Transmit Buffer Register***/
-#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1+ 0x0020))
-#define DANUBE_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_TBUF ((volatile u32*)(IFXMIPS_ASC1+ 0x0020))
+#define IFXMIPS_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
/***ASC Receive Buffer Register***/
-#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1+ 0x0024))
-#define DANUBE_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_RBUF ((volatile u32*)(IFXMIPS_ASC1+ 0x0024))
+#define IFXMIPS_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0)
/***ASC Autobaud Control Register***/
-#define DANUBE_ASC1_ABCON ((volatile u32*)(DANUBE_ASC1+ 0x0030))
-#define DANUBE_ASC1_ABCON_RXINV (1 << 11)
-#define DANUBE_ASC1_ABCON_TXINV (1 << 10)
-#define DANUBE_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8)
-#define DANUBE_ASC1_ABCON_FCDETEN (1 << 4)
-#define DANUBE_ASC1_ABCON_ABDETEN (1 << 3)
-#define DANUBE_ASC1_ABCON_ABSTEN (1 << 2)
-#define DANUBE_ASC1_ABCON_AUREN (1 << 1)
-#define DANUBE_ASC1_ABCON_ABEN (1 << 0)
+#define IFXMIPS_ASC1_ABCON ((volatile u32*)(IFXMIPS_ASC1+ 0x0030))
+#define IFXMIPS_ASC1_ABCON_RXINV (1 << 11)
+#define IFXMIPS_ASC1_ABCON_TXINV (1 << 10)
+#define IFXMIPS_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_ABCON_FCDETEN (1 << 4)
+#define IFXMIPS_ASC1_ABCON_ABDETEN (1 << 3)
+#define IFXMIPS_ASC1_ABCON_ABSTEN (1 << 2)
+#define IFXMIPS_ASC1_ABCON_AUREN (1 << 1)
+#define IFXMIPS_ASC1_ABCON_ABEN (1 << 0)
/***Receive FIFO Control Register***/
-#define DANUBE_ASC1_RXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0040))
-#define DANUBE_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_ASC1_RXFCON_RXFFLU (1 << 1)
-#define DANUBE_ASC1_RXFCON_RXFEN (1 << 0)
+#define IFXMIPS_ASC1_RXFCON ((volatile u32*)(IFXMIPS_ASC1+ 0x0040))
+#define IFXMIPS_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_RXFCON_RXFFLU (1 << 1)
+#define IFXMIPS_ASC1_RXFCON_RXFEN (1 << 0)
/***Transmit FIFO Control Register***/
-#define DANUBE_ASC1_TXFCON ((volatile u32*)(DANUBE_ASC1+ 0x0044))
-#define DANUBE_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_ASC1_TXFCON_TXFFLU (1 << 1)
-#define DANUBE_ASC1_TXFCON_TXFEN (1 << 0)
+#define IFXMIPS_ASC1_TXFCON ((volatile u32*)(IFXMIPS_ASC1+ 0x0044))
+#define IFXMIPS_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_TXFCON_TXFFLU (1 << 1)
+#define IFXMIPS_ASC1_TXFCON_TXFEN (1 << 0)
/***FIFO Status Register***/
-#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0048))
-#define DANUBE_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
-#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
-#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
-#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
-#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
-#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
-#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
-#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
-#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_FSTAT ((volatile u32*)(IFXMIPS_ASC1+ 0x0048))
+#define IFXMIPS_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
+#define IFXMIPS_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define IFXMIPS_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define IFXMIPS_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define IFXMIPS_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define IFXMIPS_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define IFXMIPS_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define IFXMIPS_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define IFXMIPS_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
/***ASC Autobaud Status Register***/
-#define DANUBE_ASC1_ABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x0034))
-#define DANUBE_ASC1_ABSTAT_DETWAIT (1 << 4)
-#define DANUBE_ASC1_ABSTAT_SCCDET (1 << 3)
-#define DANUBE_ASC1_ABSTAT_SCSDET (1 << 2)
-#define DANUBE_ASC1_ABSTAT_FCCDET (1 << 1)
-#define DANUBE_ASC1_ABSTAT_FCSDET (1 << 0)
+#define IFXMIPS_ASC1_ABSTAT ((volatile u32*)(IFXMIPS_ASC1+ 0x0034))
+#define IFXMIPS_ASC1_ABSTAT_DETWAIT (1 << 4)
+#define IFXMIPS_ASC1_ABSTAT_SCCDET (1 << 3)
+#define IFXMIPS_ASC1_ABSTAT_SCSDET (1 << 2)
+#define IFXMIPS_ASC1_ABSTAT_FCCDET (1 << 1)
+#define IFXMIPS_ASC1_ABSTAT_FCSDET (1 << 0)
/***ASC Write HW Modified Autobaud Status Register***/
-#define DANUBE_ASC1_WHBABSTAT ((volatile u32*)(DANUBE_ASC1+ 0x003C))
-#define DANUBE_ASC1_WHBABSTAT_SETDETWAIT (1 << 9)
-#define DANUBE_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8)
-#define DANUBE_ASC1_WHBABSTAT_SETSCCDET (1 << 7)
-#define DANUBE_ASC1_WHBABSTAT_CLRSCCDET (1 << 6)
-#define DANUBE_ASC1_WHBABSTAT_SETSCSDET (1 << 5)
-#define DANUBE_ASC1_WHBABSTAT_CLRSCSDET (1 << 4)
-#define DANUBE_ASC1_WHBABSTAT_SETFCCDET (1 << 3)
-#define DANUBE_ASC1_WHBABSTAT_CLRFCCDET (1 << 2)
-#define DANUBE_ASC1_WHBABSTAT_SETFCSDET (1 << 1)
-#define DANUBE_ASC1_WHBABSTAT_CLRFCSDET (1 << 0)
+#define IFXMIPS_ASC1_WHBABSTAT ((volatile u32*)(IFXMIPS_ASC1+ 0x003C))
+#define IFXMIPS_ASC1_WHBABSTAT_SETDETWAIT (1 << 9)
+#define IFXMIPS_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8)
+#define IFXMIPS_ASC1_WHBABSTAT_SETSCCDET (1 << 7)
+#define IFXMIPS_ASC1_WHBABSTAT_CLRSCCDET (1 << 6)
+#define IFXMIPS_ASC1_WHBABSTAT_SETSCSDET (1 << 5)
+#define IFXMIPS_ASC1_WHBABSTAT_CLRSCSDET (1 << 4)
+#define IFXMIPS_ASC1_WHBABSTAT_SETFCCDET (1 << 3)
+#define IFXMIPS_ASC1_WHBABSTAT_CLRFCCDET (1 << 2)
+#define IFXMIPS_ASC1_WHBABSTAT_SETFCSDET (1 << 1)
+#define IFXMIPS_ASC1_WHBABSTAT_CLRFCSDET (1 << 0)
/***ASC IRNCR0 **/
-#define DANUBE_ASC1_IRNREN ((volatile u32*)(DANUBE_ASC1+ 0x00F4))
-#define DANUBE_ASC1_IRNICR ((volatile u32*)(DANUBE_ASC1+ 0x00FC))
+#define IFXMIPS_ASC1_IRNREN ((volatile u32*)(IFXMIPS_ASC1+ 0x00F4))
+#define IFXMIPS_ASC1_IRNICR ((volatile u32*)(IFXMIPS_ASC1+ 0x00FC))
/***ASC IRNCR1 **/
-#define DANUBE_ASC1_IRNCR ((volatile u32*)(DANUBE_ASC1+ 0x00F8))
+#define IFXMIPS_ASC1_IRNCR ((volatile u32*)(IFXMIPS_ASC1+ 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
@@ -1401,417 +1401,417 @@ If set and clear bit are written concurrently with 1, the associated bit is not
/* Module : DMA register address and bits */
/***********************************************************************/
-#define DANUBE_DMA (0xBE104100)
+#define IFXMIPS_DMA (0xBE104100)
/***********************************************************************/
-#define DANUBE_DMA_BASE DANUBE_DMA
-#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE
-#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08)
-#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10)
-#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14)
-#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18)
-#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C)
-#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20)
-#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24)
-#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28)
-#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C)
+#define IFXMIPS_DMA_BASE IFXMIPS_DMA
+#define IFXMIPS_DMA_CLC (volatile u32*)IFXMIPS_DMA_BASE
+#define IFXMIPS_DMA_ID (volatile u32*)(IFXMIPS_DMA_BASE+0x08)
+#define IFXMIPS_DMA_CTRL (volatile u32*)(IFXMIPS_DMA_BASE+0x10)
+#define IFXMIPS_DMA_CPOLL (volatile u32*)(IFXMIPS_DMA_BASE+0x14)
+#define IFXMIPS_DMA_CS (volatile u32*)(IFXMIPS_DMA_BASE+0x18)
+#define IFXMIPS_DMA_CCTRL (volatile u32*)(IFXMIPS_DMA_BASE+0x1C)
+#define IFXMIPS_DMA_CDBA (volatile u32*)(IFXMIPS_DMA_BASE+0x20)
+#define IFXMIPS_DMA_CDLEN (volatile u32*)(IFXMIPS_DMA_BASE+0x24)
+#define IFXMIPS_DMA_CIS (volatile u32*)(IFXMIPS_DMA_BASE+0x28)
+#define IFXMIPS_DMA_CIE (volatile u32*)(IFXMIPS_DMA_BASE+0x2C)
-#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40)
-#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44)
+#define IFXMIPS_DMA_PS (volatile u32*)(IFXMIPS_DMA_BASE+0x40)
+#define IFXMIPS_DMA_PCTRL (volatile u32*)(IFXMIPS_DMA_BASE+0x44)
-#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4)
-#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8)
-#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc)
+#define IFXMIPS_DMA_IRNEN (volatile u32*)(IFXMIPS_DMA_BASE+0xf4)
+#define IFXMIPS_DMA_IRNCR (volatile u32*)(IFXMIPS_DMA_BASE+0xf8)
+#define IFXMIPS_DMA_IRNICR (volatile u32*)(IFXMIPS_DMA_BASE+0xfc)
/***********************************************************************/
/* Module : Debug register address and bits */
/***********************************************************************/
-#define DANUBE_Debug (0xBF106000)
+#define IFXMIPS_Debug (0xBF106000)
/***********************************************************************/
/***MCD Break Bus Switch Register***/
-#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000))
-#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19)
-#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18)
-#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17)
-#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16)
-#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15)
-#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14)
-#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13)
-#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12)
-#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7)
-#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6)
-#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5)
-#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4)
+#define IFXMIPS_Debug_MCD_BBS ((volatile u32*)(IFXMIPS_Debug+ 0x0000))
+#define IFXMIPS_Debug_MCD_BBS_BTP1 (1 << 19)
+#define IFXMIPS_Debug_MCD_BBS_BTP0 (1 << 18)
+#define IFXMIPS_Debug_MCD_BBS_BSP1 (1 << 17)
+#define IFXMIPS_Debug_MCD_BBS_BSP0 (1 << 16)
+#define IFXMIPS_Debug_MCD_BBS_BT5EN (1 << 15)
+#define IFXMIPS_Debug_MCD_BBS_BT4EN (1 << 14)
+#define IFXMIPS_Debug_MCD_BBS_BT5 (1 << 13)
+#define IFXMIPS_Debug_MCD_BBS_BT4 (1 << 12)
+#define IFXMIPS_Debug_MCD_BBS_BS5EN (1 << 7)
+#define IFXMIPS_Debug_MCD_BBS_BS4EN (1 << 6)
+#define IFXMIPS_Debug_MCD_BBS_BS5 (1 << 5)
+#define IFXMIPS_Debug_MCD_BBS_BS4 (1 << 4)
/***MCD Multiplexer Control Register***/
-#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008))
-#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4)
-#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3)
-#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0)
+#define IFXMIPS_Debug_MCD_MCR ((volatile u32*)(IFXMIPS_Debug+ 0x0008))
+#define IFXMIPS_Debug_MCD_MCR_MUX5 (1 << 4)
+#define IFXMIPS_Debug_MCD_MCR_MUX4 (1 << 3)
+#define IFXMIPS_Debug_MCD_MCR_MUX1 (1 << 0)
/***********************************************************************/
/* Module : SRAM register address and bits */
/***********************************************************************/
-#define DANUBE_SRAM (0xBF980000)
+#define IFXMIPS_SRAM (0xBF980000)
/***********************************************************************/
/***SRAM Size Register***/
-#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800))
-#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
+#define IFXMIPS_SRAM_SRAM_SIZE ((volatile u32*)(IFXMIPS_SRAM+ 0x0800))
+#define IFXMIPS_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
/***********************************************************************/
/* Module : BIU register address and bits */
/***********************************************************************/
-#define DANUBE_BIU (0xBFA80000)
+#define IFXMIPS_BIU (0xBFA80000)
/***********************************************************************/
/***BIU Identification Register***/
-#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000))
-#define DANUBE_BIU_BIU_ID_ARCH (1 << 16)
-#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
-#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
+#define IFXMIPS_BIU_BIU_ID ((volatile u32*)(IFXMIPS_BIU+ 0x0000))
+#define IFXMIPS_BIU_BIU_ID_ARCH (1 << 16)
+#define IFXMIPS_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define IFXMIPS_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
/***BIU Access Error Cause Register***/
-#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100))
-#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31)
-#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
-#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define IFXMIPS_BIU_BIU_ERRCAUSE ((volatile u32*)(IFXMIPS_BIU+ 0x0100))
+#define IFXMIPS_BIU_BIU_ERRCAUSE_ERR (1 << 31)
+#define IFXMIPS_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define IFXMIPS_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
/***BIU Access Error Address Register***/
-#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108))
-#define DANUBE_BIU_BIU_ERRADDR_ADDR
+#define IFXMIPS_BIU_BIU_ERRADDR ((volatile u32*)(IFXMIPS_BIU+ 0x0108))
+#define IFXMIPS_BIU_BIU_ERRADDR_ADDR
/***********************************************************************/
/* Module : ICU register address and bits */
/***********************************************************************/
-#define DANUBE_ICU (0xBF880200)
-/***********************************************************************/
-#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU + 0x0000))
-#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU + 0x0008))
-#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU + 0x0010))
-#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU + 0x0018))
-#define DANUBE_ICU_IM0_IMR ((volatile u32*)(DANUBE_ICU + 0x0020))
-#define DANUBE_ICU_IM0_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM0_IR(value) (1 << (value))
-
-#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU + 0x0028))
-#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU + 0x0030))
-#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU + 0x0038))
-#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU + 0x0040))
-#define DANUBE_ICU_IM1_IMR ((volatile u32*)(DANUBE_ICU + 0x0048))
-#define DANUBE_ICU_IM1_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM1_IR(value) (1 << (value))
-
-#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU + 0x0050))
-#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU + 0x0058))
-#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU + 0x0060))
-#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU + 0x0068))
-#define DANUBE_ICU_IM2_IMR ((volatile u32*)(DANUBE_ICU + 0x0070))
-#define DANUBE_ICU_IM2_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM2_IR(value) (1 << (value))
-
-#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU + 0x0078))
-#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU + 0x0080))
-#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU + 0x0088))
-#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU + 0x0090))
-#define DANUBE_ICU_IM3_IMR ((volatile u32*)(DANUBE_ICU + 0x0098))
-#define DANUBE_ICU_IM3_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM3_IR(value) (1 << (value))
-
-#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU + 0x00A0))
-#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU + 0x00A8))
-#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU + 0x00B0))
-#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU + 0x00B8))
-#define DANUBE_ICU_IM4_IMR ((volatile u32*)(DANUBE_ICU + 0x00C0))
-#define DANUBE_ICU_IM4_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM4_IR(value) (1 << (value))
-
-#define DANUBE_ICU_IM5_ISR ((volatile u32*)(DANUBE_ICU + 0x00C8))
-#define DANUBE_ICU_IM5_IER ((volatile u32*)(DANUBE_ICU + 0x00D0))
-#define DANUBE_ICU_IM5_IOSR ((volatile u32*)(DANUBE_ICU + 0x00D8))
-#define DANUBE_ICU_IM5_IRSR ((volatile u32*)(DANUBE_ICU + 0x00E0))
-#define DANUBE_ICU_IM5_IMR ((volatile u32*)(DANUBE_ICU + 0x00E8))
-#define DANUBE_ICU_IM5_IMR_IID (1 << 31)
-#define DANUBE_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
-#define DANUBE_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
-#define DANUBE_ICU_IM5_IR(value) (1 << (value))
+#define IFXMIPS_ICU (0xBF880200)
+/***********************************************************************/
+#define IFXMIPS_ICU_IM0_ISR ((volatile u32*)(IFXMIPS_ICU + 0x0000))
+#define IFXMIPS_ICU_IM0_IER ((volatile u32*)(IFXMIPS_ICU + 0x0008))
+#define IFXMIPS_ICU_IM0_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x0010))
+#define IFXMIPS_ICU_IM0_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x0018))
+#define IFXMIPS_ICU_IM0_IMR ((volatile u32*)(IFXMIPS_ICU + 0x0020))
+#define IFXMIPS_ICU_IM0_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM0_IR(value) (1 << (value))
+
+#define IFXMIPS_ICU_IM1_ISR ((volatile u32*)(IFXMIPS_ICU + 0x0028))
+#define IFXMIPS_ICU_IM1_IER ((volatile u32*)(IFXMIPS_ICU + 0x0030))
+#define IFXMIPS_ICU_IM1_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x0038))
+#define IFXMIPS_ICU_IM1_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x0040))
+#define IFXMIPS_ICU_IM1_IMR ((volatile u32*)(IFXMIPS_ICU + 0x0048))
+#define IFXMIPS_ICU_IM1_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM1_IR(value) (1 << (value))
+
+#define IFXMIPS_ICU_IM2_ISR ((volatile u32*)(IFXMIPS_ICU + 0x0050))
+#define IFXMIPS_ICU_IM2_IER ((volatile u32*)(IFXMIPS_ICU + 0x0058))
+#define IFXMIPS_ICU_IM2_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x0060))
+#define IFXMIPS_ICU_IM2_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x0068))
+#define IFXMIPS_ICU_IM2_IMR ((volatile u32*)(IFXMIPS_ICU + 0x0070))
+#define IFXMIPS_ICU_IM2_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM2_IR(value) (1 << (value))
+
+#define IFXMIPS_ICU_IM3_ISR ((volatile u32*)(IFXMIPS_ICU + 0x0078))
+#define IFXMIPS_ICU_IM3_IER ((volatile u32*)(IFXMIPS_ICU + 0x0080))
+#define IFXMIPS_ICU_IM3_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x0088))
+#define IFXMIPS_ICU_IM3_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x0090))
+#define IFXMIPS_ICU_IM3_IMR ((volatile u32*)(IFXMIPS_ICU + 0x0098))
+#define IFXMIPS_ICU_IM3_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM3_IR(value) (1 << (value))
+
+#define IFXMIPS_ICU_IM4_ISR ((volatile u32*)(IFXMIPS_ICU + 0x00A0))
+#define IFXMIPS_ICU_IM4_IER ((volatile u32*)(IFXMIPS_ICU + 0x00A8))
+#define IFXMIPS_ICU_IM4_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x00B0))
+#define IFXMIPS_ICU_IM4_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x00B8))
+#define IFXMIPS_ICU_IM4_IMR ((volatile u32*)(IFXMIPS_ICU + 0x00C0))
+#define IFXMIPS_ICU_IM4_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM4_IR(value) (1 << (value))
+
+#define IFXMIPS_ICU_IM5_ISR ((volatile u32*)(IFXMIPS_ICU + 0x00C8))
+#define IFXMIPS_ICU_IM5_IER ((volatile u32*)(IFXMIPS_ICU + 0x00D0))
+#define IFXMIPS_ICU_IM5_IOSR ((volatile u32*)(IFXMIPS_ICU + 0x00D8))
+#define IFXMIPS_ICU_IM5_IRSR ((volatile u32*)(IFXMIPS_ICU + 0x00E0))
+#define IFXMIPS_ICU_IM5_IMR ((volatile u32*)(IFXMIPS_ICU + 0x00E8))
+#define IFXMIPS_ICU_IM5_IMR_IID (1 << 31)
+#define IFXMIPS_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define IFXMIPS_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define IFXMIPS_ICU_IM5_IR(value) (1 << (value))
/***Interrupt Vector Value Register***/
-//#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00f0))
-#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x00EC))
+//#define IFXMIPS_ICU_IM_VEC ((volatile u32*)(IFXMIPS_ICU+ 0x00f0))
+#define IFXMIPS_ICU_IM_VEC ((volatile u32*)(IFXMIPS_ICU+ 0x00EC))
/***Interrupt Vector Value Mask***/
-#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f
-#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0
-#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00
-#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000
-#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000
-
-#define DANUBE_ICU_IM0_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM0_IER_IR(value) (1<<(value))
-#define DANUBE_ICU_IM1_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM1_IER_IR(value) (1<<(value))
-#define DANUBE_ICU_IM2_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM2_IER_IR(value) (1<<(value))
-#define DANUBE_ICU_IM3_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM3_IER_IR(value) (1<<(value))
-#define DANUBE_ICU_IM4_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM4_IER_IR(value) (1<<(value))
-#define DANUBE_ICU_IM5_ISR_IR(value) (1<<(value))
-#define DANUBE_ICU_IM5_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM0_VEC_MASK 0x0000001f
+#define IFXMIPS_ICU_IM1_VEC_MASK 0x000003e0
+#define IFXMIPS_ICU_IM2_VEC_MASK 0x00007c00
+#define IFXMIPS_ICU_IM3_VEC_MASK 0x000f8000
+#define IFXMIPS_ICU_IM4_VEC_MASK 0x01f00000
+
+#define IFXMIPS_ICU_IM0_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM0_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM1_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM1_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM2_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM2_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM3_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM3_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM4_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM4_IER_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM5_ISR_IR(value) (1<<(value))
+#define IFXMIPS_ICU_IM5_IER_IR(value) (1<<(value))
/***DMA Interrupt Mask Value***/
-#define DANUBE_DMA_H_MASK 0x00000fff
+#define IFXMIPS_DMA_H_MASK 0x00000fff
/***External Interrupt Control Register***/
-#define DANUBE_ICU_EIU (KSEG1+0x1f101000)
-#define DANUBE_ICU_EIU_EXIN_C ((volatile u32*)(DANUBE_ICU_EIU+ 0x0000))
-#define DANUBE_ICU_EIU_INIC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0004))
-#define DANUBE_ICU_EIU_INC ((volatile u32*)(DANUBE_ICU_EIU+ 0x0008))
-#define DANUBE_ICU_EIU_INEN ((volatile u32*)(DANUBE_ICU_EIU+ 0x000c))
+#define IFXMIPS_ICU_EIU (KSEG1+0x1f101000)
+#define IFXMIPS_ICU_EIU_EXIN_C ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0000))
+#define IFXMIPS_ICU_EIU_INIC ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0004))
+#define IFXMIPS_ICU_EIU_INC ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x0008))
+#define IFXMIPS_ICU_EIU_INEN ((volatile u32*)(IFXMIPS_ICU_EIU+ 0x000c))
/***********************************************************************/
/* Module : MPS register address and bits */
/***********************************************************************/
-#define DANUBE_MPS (KSEG1+0x1F107000)
+#define IFXMIPS_MPS (KSEG1+0x1F107000)
/***********************************************************************/
-#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344))
-#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
-#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
-#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
-#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
-#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
-#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
+#define IFXMIPS_MPS_CHIPID ((volatile u32*)(IFXMIPS_MPS + 0x0344))
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
+#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
+#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
/* voice channel 0 ... 3 interrupt enable register */
-#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000))
-#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004))
-#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008))
-#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C))
+#define IFXMIPS_MPS_VC0ENR ((volatile u32*)(IFXMIPS_MPS + 0x0000))
+#define IFXMIPS_MPS_VC1ENR ((volatile u32*)(IFXMIPS_MPS + 0x0004))
+#define IFXMIPS_MPS_VC2ENR ((volatile u32*)(IFXMIPS_MPS + 0x0008))
+#define IFXMIPS_MPS_VC3ENR ((volatile u32*)(IFXMIPS_MPS + 0x000C))
/* voice channel 0 ... 3 interrupt status read register */
-#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010))
-#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014))
-#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018))
-#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C))
+#define IFXMIPS_MPS_RVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0010))
+#define IFXMIPS_MPS_RVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0014))
+#define IFXMIPS_MPS_RVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0018))
+#define IFXMIPS_MPS_RVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x001C))
/* voice channel 0 ... 3 interrupt status set register */
-#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020))
-#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024))
-#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028))
-#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C))
+#define IFXMIPS_MPS_SVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0020))
+#define IFXMIPS_MPS_SVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0024))
+#define IFXMIPS_MPS_SVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0028))
+#define IFXMIPS_MPS_SVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x002C))
/* voice channel 0 ... 3 interrupt status clear register */
-#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030))
-#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034))
-#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038))
-#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C))
+#define IFXMIPS_MPS_CVC0SR ((volatile u32*)(IFXMIPS_MPS + 0x0030))
+#define IFXMIPS_MPS_CVC1SR ((volatile u32*)(IFXMIPS_MPS + 0x0034))
+#define IFXMIPS_MPS_CVC2SR ((volatile u32*)(IFXMIPS_MPS + 0x0038))
+#define IFXMIPS_MPS_CVC3SR ((volatile u32*)(IFXMIPS_MPS + 0x003C))
/* common status 0 and 1 read register */
-#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040))
-#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044))
+#define IFXMIPS_MPS_RAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0040))
+#define IFXMIPS_MPS_RAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x0044))
/* common status 0 and 1 set register */
-#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048))
-#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C))
+#define IFXMIPS_MPS_SAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0048))
+#define IFXMIPS_MPS_SAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x004C))
/* common status 0 and 1 clear register */
-#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050))
-#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054))
+#define IFXMIPS_MPS_CAD0SR ((volatile u32*)(IFXMIPS_MPS + 0x0050))
+#define IFXMIPS_MPS_CAD1SR ((volatile u32*)(IFXMIPS_MPS + 0x0054))
/* common status 0 and 1 enable register */
-#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058))
-#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C))
+#define IFXMIPS_MPS_AD0ENR ((volatile u32*)(IFXMIPS_MPS + 0x0058))
+#define IFXMIPS_MPS_AD1ENR ((volatile u32*)(IFXMIPS_MPS + 0x005C))
/* notification enable register */
-#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060))
-#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064))
+#define IFXMIPS_MPS_CPU0_NFER ((volatile u32*)(IFXMIPS_MPS + 0x0060))
+#define IFXMIPS_MPS_CPU1_NFER ((volatile u32*)(IFXMIPS_MPS + 0x0064))
/* CPU to CPU interrup request register */
-#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070))
-#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074))
+#define IFXMIPS_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFXMIPS_MPS + 0x0070))
+#define IFXMIPS_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFXMIPS_MPS + 0x0074))
/* Global interrupt request and request enable register */
-#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078))
-#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C))
+#define IFXMIPS_MPS_GIRR ((volatile u32*)(IFXMIPS_MPS + 0x0078))
+#define IFXMIPS_MPS_GIER ((volatile u32*)(IFXMIPS_MPS + 0x007C))
-#define DANUBE_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000))
+#define IFXMIPS_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000))
-#define DANUBE_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0))
+#define IFXMIPS_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0))
-#define DANUBE_FUSE_BASE_ADDR (KSEG1+0x1F107354)
+#define IFXMIPS_FUSE_BASE_ADDR (KSEG1+0x1F107354)
/************************************************************************/
/* Module : DEU register address and bits */
/************************************************************************/
-//#define DANUBE_DEU_BASE_ADDR (0xBE102000)
-#define DANUBE_DEU_BASE_ADDR (KSEG1 + 0x1E103100)
+//#define IFXMIPS_DEU_BASE_ADDR (0xBE102000)
+#define IFXMIPS_DEU_BASE_ADDR (KSEG1 + 0x1E103100)
/* DEU Control Register */
-#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000))
-#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008))
+#define IFXMIPS_DEU_CLK ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0000))
+#define IFXMIPS_DEU_ID ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0008))
/* DEU control register */
-#define DANUBE_DES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010))
-#define DANUBE_DES_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014))
-#define DANUBE_DES_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018))
-#define DANUBE_DES_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C))
-#define DANUBE_DES_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020))
-#define DANUBE_DES_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024))
-#define DANUBE_DES_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028))
-#define DANUBE_DES_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C))
-#define DANUBE_DES_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030))
-#define DANUBE_DES_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040))
-#define DANUBE_DES_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
+#define IFXMIPS_DES_CON ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0010))
+#define IFXMIPS_DES_IHR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0014))
+#define IFXMIPS_DES_ILR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0018))
+#define IFXMIPS_DES_K1HR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x001C))
+#define IFXMIPS_DES_K1LR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0020))
+#define IFXMIPS_DES_K3HR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0024))
+#define IFXMIPS_DES_K3LR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0028))
+#define IFXMIPS_DES_IVHR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x002C))
+#define IFXMIPS_DES_IVLR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0030))
+#define IFXMIPS_DES_OHR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0040))
+#define IFXMIPS_DES_OLR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0050))
/* AES DEU register */
-#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
-#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054))
-#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058))
-#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C))
-#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060))
+#define IFXMIPS_AES_CON ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0050))
+#define IFXMIPS_AES_ID3R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0054))
+#define IFXMIPS_AES_ID2R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0058))
+#define IFXMIPS_AES_ID1R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x005C))
+#define IFXMIPS_AES_ID0R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0060))
/* AES Key register */
-#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064))
-#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068))
-#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C))
-#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070))
-#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074))
-#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078))
-#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C))
-#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080))
+#define IFXMIPS_AES_K7R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0064))
+#define IFXMIPS_AES_K6R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0068))
+#define IFXMIPS_AES_K5R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x006C))
+#define IFXMIPS_AES_K4R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0070))
+#define IFXMIPS_AES_K3R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0074))
+#define IFXMIPS_AES_K2R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0078))
+#define IFXMIPS_AES_K1R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x007C))
+#define IFXMIPS_AES_K0R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0080))
/* AES vector register */
-#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084))
-#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088))
-#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C))
-#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090))
-#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094))
-#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098))
-#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C))
-#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0))
+#define IFXMIPS_AES_IV3R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0084))
+#define IFXMIPS_AES_IV2R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0088))
+#define IFXMIPS_AES_IV1R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x008C))
+#define IFXMIPS_AES_IV0R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0090))
+#define IFXMIPS_AES_0D3R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0094))
+#define IFXMIPS_AES_0D2R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x0098))
+#define IFXMIPS_AES_OD1R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x009C))
+#define IFXMIPS_AES_OD0R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00A0))
/* hash control registe */
-#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0))
-#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4))
-#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 ))
-#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC ))
-#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 ))
-#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4))
-#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8))
+#define IFXMIPS_HASH_CON ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B0))
+#define IFXMIPS_HASH_MR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B4))
+#define IFXMIPS_HASH_D1R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00B8 ))
+#define IFXMIPS_HASH_D2R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00BC ))
+#define IFXMIPS_HASH_D3R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C0 ))
+#define IFXMIPS_HASH_D4R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C4))
+#define IFXMIPS_HASH_D5R ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00C8))
-#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC))
+#define IFXMIPS_CON ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00EC))
-#define DANUBE_DEU_IRNEN ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F4))
-#define DANUBE_DEU_IRNCR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00F8))
-#define DANUBE_DEU_IRNICR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00FC))
+#define IFXMIPS_DEU_IRNEN ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00F4))
+#define IFXMIPS_DEU_IRNCR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00F8))
+#define IFXMIPS_DEU_IRNICR ((volatile u32 *)(IFXMIPS_DEU_BASE_ADDR + 0x00FC))
/************************************************************************/
/* Module : PPE register address and bits */
/************************************************************************/
-#define DANUBE_PPE32_BASE 0xBE180000
-#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
-#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
-#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
-#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
-#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
-#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
+#define IFXMIPS_PPE32_BASE 0xBE180000
+#define IFXMIPS_PPE32_DEBUG_BREAK_TRACE_REG (IFXMIPS_PPE32_BASE + (0x0000 * 4))
+#define IFXMIPS_PPE32_INT_MASK_STATUS_REG (IFXMIPS_PPE32_BASE + (0x0030 * 4))
+#define IFXMIPS_PPE32_INT_RESOURCE_REG (IFXMIPS_PPE32_BASE + (0x0040 * 4))
+#define IFXMIPS_PPE32_CDM_CODE_MEM_B0 (IFXMIPS_PPE32_BASE + (0x1000 * 4))
+#define IFXMIPS_PPE32_CDM_CODE_MEM_B1 (IFXMIPS_PPE32_BASE + (0x2000 * 4))
+#define IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE (IFXMIPS_PPE32_BASE + (0x4000 * 4))
-#define DANUBE_PPE32_SRST (DANUBE_PPE32_BASE + 0x10080)
+#define IFXMIPS_PPE32_SRST (IFXMIPS_PPE32_BASE + 0x10080)
/*
* ETOP MDIO Registers
*/
-#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
-#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
-#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
-#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
-#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
-#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
-#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
-#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
-#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
-#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
-#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
-#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
+#define IFXMIPS_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
+#define IFXMIPS_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
+#define IFXMIPS_PPE32_ETOP_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
+#define IFXMIPS_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
+#define IFXMIPS_PPE32_ETOP_ISR ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
+#define IFXMIPS_PPE32_ETOP_IER ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
+#define IFXMIPS_PPE32_ETOP_VPID ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
/* ENET Register */
-#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+#define IFXMIPS_PPE32_ENET_MAC_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define IFXMIPS_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define IFXMIPS_PPE32_ENET_CoS_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
/* Sharebuff SB RAM2 control data */
-#define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4)))
-#define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4)))
+#define IFXMIPS_PPE32_SB2_DATABASE ((IFXMIPS_PPE32_BASE + (0x8C00 * 4)))
+#define IFXMIPS_PPE32_SB2_CTRLBASE ((IFXMIPS_PPE32_BASE + (0x92E0 * 4)))
/************************************************************************/
/* Module : PPE register address and bits */
/************************************************************************/
-#define DANUBE_PPE32_BASE 0xBE180000
-#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
-#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
-#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
-#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
-#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
-#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
+#define IFXMIPS_PPE32_BASE 0xBE180000
+#define IFXMIPS_PPE32_DEBUG_BREAK_TRACE_REG (IFXMIPS_PPE32_BASE + (0x0000 * 4))
+#define IFXMIPS_PPE32_INT_MASK_STATUS_REG (IFXMIPS_PPE32_BASE + (0x0030 * 4))
+#define IFXMIPS_PPE32_INT_RESOURCE_REG (IFXMIPS_PPE32_BASE + (0x0040 * 4))
+#define IFXMIPS_PPE32_CDM_CODE_MEM_B0 (IFXMIPS_PPE32_BASE + (0x1000 * 4))
+#define IFXMIPS_PPE32_CDM_CODE_MEM_B1 (IFXMIPS_PPE32_BASE + (0x2000 * 4))
+#define IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE (IFXMIPS_PPE32_BASE + (0x4000 * 4))
/*
* ETOP MDIO Registers
*/
-#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
-#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
-#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
-#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
-#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
-#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
-#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
-#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
-#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
-#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
-#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
-#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
-#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
-#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
-#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
-#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
-#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
-#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
-#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
-#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
-#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
-#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
-
-#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
-#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
-#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
-#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
-#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
-#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
-#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
-
-#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
-#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
-#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
-#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
-#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
-#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
+#define ETOP_MDIO_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
+#define ETOP_MDIO_ACC ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
+#define ETOP_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
+#define ETOP_IG_VLAN_COS ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
+#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
+#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
+#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
+#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
+#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
+#define ETOP_ISR ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
+#define ETOP_IER ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
+#define ETOP_VPID ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
+#define ENET_MAC_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define ENETS_DBA ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
+#define ENETS_CBA ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
+#define ENETS_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
+#define ENETS_PGCNT ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
+#define ENETS_PKTCNT ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
+#define ENETS_BUF_CTRL ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
+#define ENETS_COS_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+#define ENETS_IGDROP ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define ENETS_IGERR ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
+#define ENET_MAC_DA0 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
+#define ENET_MAC_DA1 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
+
+#define ENETF_DBA ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
+#define ENETF_CBA ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
+#define ENETF_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
+#define ENETF_PGCNT ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
+#define ENETF_PKTCNT ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
+#define ENETF_HFCTRL ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
+#define ENETF_TXCTRL ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
+
+#define ENETF_VLCOS0 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
+#define ENETF_VLCOS1 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
+#define ENETF_VLCOS2 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
+#define ENETF_VLCOS3 ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
+#define ENETF_EGERR ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
+#define ENETF_EGDROP ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
/* ENET Register */
-#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
-#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
-#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+#define IFXMIPS_PPE32_ENET_MAC_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define IFXMIPS_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define IFXMIPS_PPE32_ENET_CoS_CFG ((volatile u32 *)(IFXMIPS_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
/* Sharebuff SB RAM2 control data */
-#define DANUBE_PPE32_SB2_DATABASE ((DANUBE_PPE32_BASE + (0x8C00 * 4)))
-#define DANUBE_PPE32_SB2_CTRLBASE ((DANUBE_PPE32_BASE + (0x92E0 * 4)))
+#define IFXMIPS_PPE32_SB2_DATABASE ((IFXMIPS_PPE32_BASE + (0x8C00 * 4)))
+#define IFXMIPS_PPE32_SB2_CTRLBASE ((IFXMIPS_PPE32_BASE + (0x92E0 * 4)))
/***********************************************************************/
/* Module : PCI register address and bits */
@@ -2016,6 +2016,6 @@ If set and clear bit are written concurrently with 1, the associated bit is not
#define IOMEM_RESOURCE_END 0xffffffff
/***********************************************************************/
-#define DANUBE_REG32(addr) *((volatile u32 *)(addr))
+#define IFXMIPS_REG32(addr) *((volatile u32 *)(addr))
/***********************************************************************/
-#endif //DANUBE_H
+#endif //IFXMIPS_H
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
index b404b262c3..749e3b5638 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
@@ -16,14 +16,14 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
-#ifndef _DANUBE_PMU_H__
-#define _DANUBE_PMU_H__
+#ifndef _IFXMIPS_PMU_H__
+#define _IFXMIPS_PMU_H__
-#define DANUBE_PMU_PWDCR_DMA 0x20
-#define DANUBE_PMU_PWDCR_LED 0x800
-#define DANUBE_PMU_PWDCR_GPT 0x1000
-#define DANUBE_PMU_PWDCR_PPE 0x2000
-#define DANUBE_PMU_PWDCR_FPI 0x4000
+#define IFXMIPS_PMU_PWDCR_DMA 0x20
+#define IFXMIPS_PMU_PWDCR_LED 0x800
+#define IFXMIPS_PMU_PWDCR_GPT 0x1000
+#define IFXMIPS_PMU_PWDCR_PPE 0x2000
+#define IFXMIPS_PMU_PWDCR_FPI 0x4000
void danube_pmu_enable (unsigned int module);
void danube_pmu_disable (unsigned int module);
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
index 7b7994751b..93553fe5cf 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
@@ -1,7 +1,7 @@
-/* incaAscSio.h - (DANUBE) ASC UART tty driver header */
+/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
-#ifndef __DANUBE_ASC_H
-#define __DANUBE_ASC_H
+#ifndef __IFXMIPS_ASC_H
+#define __IFXMIPS_ASC_H
/******************************************************************************
**
@@ -41,29 +41,29 @@
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
-#define DANUBEASC_TXFIFO_FL 1
-#define DANUBEASC_RXFIFO_FL 1
-#define DANUBEASC_TXFIFO_FULL 16
+#define IFXMIPSASC_TXFIFO_FL 1
+#define IFXMIPSASC_RXFIFO_FL 1
+#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
-#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
+#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
-#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
-#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
-#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
-#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
-#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
-#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
-#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
+#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
+#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
+#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
+#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
+#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
+#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
+#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
-*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
+*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
-*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
+*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
-*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
+*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
@@ -191,4 +191,4 @@
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
-#endif /* __DANUBE_ASC_H */
+#endif /* __IFXMIPS_ASC_H */
diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
index 1c31fc9ee2..919b708d43 100644
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
@@ -18,31 +18,31 @@
*
*/
-#ifndef DANUBE_WDT_H
-#define DANUBE_WDT_H
+#ifndef IFXMIPS_WDT_H
+#define IFXMIPS_WDT_H
/* Danube wdt ioctl control */
-#define DANUBE_WDT_IOC_MAGIC 0xc0
-#define DANUBE_WDT_IOC_START _IOW(DANUBE_WDT_IOC_MAGIC, 0, int)
-#define DANUBE_WDT_IOC_STOP _IO(DANUBE_WDT_IOC_MAGIC, 1)
-#define DANUBE_WDT_IOC_PING _IO(DANUBE_WDT_IOC_MAGIC, 2)
-#define DANUBE_WDT_IOC_SET_PWL _IOW(DANUBE_WDT_IOC_MAGIC, 3, int)
-#define DANUBE_WDT_IOC_SET_DSEN _IOW(DANUBE_WDT_IOC_MAGIC, 4, int)
-#define DANUBE_WDT_IOC_SET_LPEN _IOW(DANUBE_WDT_IOC_MAGIC, 5, int)
-#define DANUBE_WDT_IOC_GET_STATUS _IOR(DANUBE_WDT_IOC_MAGIC, 6, int)
-#define DANUBE_WDT_IOC_SET_CLKDIV _IOW(DANUBE_WDT_IOC_MAGIC, 7, int)
+#define IFXMIPS_WDT_IOC_MAGIC 0xc0
+#define IFXMIPS_WDT_IOC_START _IOW(IFXMIPS_WDT_IOC_MAGIC, 0, int)
+#define IFXMIPS_WDT_IOC_STOP _IO(IFXMIPS_WDT_IOC_MAGIC, 1)
+#define IFXMIPS_WDT_IOC_PING _IO(IFXMIPS_WDT_IOC_MAGIC, 2)
+#define IFXMIPS_WDT_IOC_SET_PWL _IOW(IFXMIPS_WDT_IOC_MAGIC, 3, int)
+#define IFXMIPS_WDT_IOC_SET_DSEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 4, int)
+#define IFXMIPS_WDT_IOC_SET_LPEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 5, int)
+#define IFXMIPS_WDT_IOC_GET_STATUS _IOR(IFXMIPS_WDT_IOC_MAGIC, 6, int)
+#define IFXMIPS_WDT_IOC_SET_CLKDIV _IOW(IFXMIPS_WDT_IOC_MAGIC, 7, int)
/* password 1 and 2 */
-#define DANUBE_WDT_PW1 0x000000BE
-#define DANUBE_WDT_PW2 0x000000DC
+#define IFXMIPS_WDT_PW1 0x000000BE
+#define IFXMIPS_WDT_PW2 0x000000DC
-#define DANUBE_WDT_CLKDIV0_VAL 1
-#define DANUBE_WDT_CLKDIV1_VAL 64
-#define DANUBE_WDT_CLKDIV2_VAL 4096
-#define DANUBE_WDT_CLKDIV3_VAL 262144
-#define DANUBE_WDT_CLKDIV0 0
-#define DANUBE_WDT_CLKDIV1 1
-#define DANUBE_WDT_CLKDIV2 2
-#define DANUBE_WDT_CLKDIV3 3
+#define IFXMIPS_WDT_CLKDIV0_VAL 1
+#define IFXMIPS_WDT_CLKDIV1_VAL 64
+#define IFXMIPS_WDT_CLKDIV2_VAL 4096
+#define IFXMIPS_WDT_CLKDIV3_VAL 262144
+#define IFXMIPS_WDT_CLKDIV0 0
+#define IFXMIPS_WDT_CLKDIV1 1
+#define IFXMIPS_WDT_CLKDIV2 2
+#define IFXMIPS_WDT_CLKDIV3 3
#endif
diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h b/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
index 7f1e7d3325..e836cf0882 100644
--- a/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
+++ b/target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
@@ -1,5 +1,5 @@
-#ifndef __DANUBE_IRQ_H
-#define __DANUBE_IRQ_H
+#ifndef __IFXMIPS_IRQ_H
+#define __IFXMIPS_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>
diff --git a/target/linux/ifxmips/patches/100-board.patch b/target/linux/ifxmips/patches/100-board.patch
index c73c4e7fdc..10b49e83e5 100644
--- a/target/linux/ifxmips/patches/100-board.patch
+++ b/target/linux/ifxmips/patches/100-board.patch
@@ -6,7 +6,7 @@ Index: linux-2.6.23/arch/mips/Kconfig
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
-+config DANUBE
++config IFXMIPS
+ bool "Danube support"
+ select DMA_NONCOHERENT
+ select IRQ_CPU
@@ -37,11 +37,11 @@ Index: linux-2.6.23/arch/mips/Makefile
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
+#
-+# Infineon DANUBE
++# Infineon IFXMIPS
+#
-+core-$(CONFIG_DANUBE) += arch/mips/danube/
-+cflags-$(CONFIG_DANUBE) += -Iinclude/asm-mips/mach-danube
-+load-$(CONFIG_DANUBE) += 0xffffffff80002000
++core-$(CONFIG_IFXMIPS) += arch/mips/danube/
++cflags-$(CONFIG_IFXMIPS) += -Iinclude/asm-mips/mach-danube
++load-$(CONFIG_IFXMIPS) += 0xffffffff80002000
+
#
# DECstation family
@@ -57,8 +57,8 @@ Index: linux-2.6.23/include/asm-mips/bootinfo.h
+/*
+ * Valid machtype for group ATHEROS
+ */
-+#define MACH_GROUP_DANUBE 29
-+#define MACH_INFINEON_DANUBE 0
++#define MACH_GROUP_IFXMIPS 29
++#define MACH_INFINEON_IFXMIPS 0
+
+
#define CL_SIZE COMMAND_LINE_SIZE
diff --git a/target/linux/ifxmips/patches/110-drivers.patch b/target/linux/ifxmips/patches/110-drivers.patch
index 35a2024bb6..7119392655 100644
--- a/target/linux/ifxmips/patches/110-drivers.patch
+++ b/target/linux/ifxmips/patches/110-drivers.patch
@@ -6,9 +6,9 @@ Index: linux-2.6.23/drivers/serial/Kconfig
Currently, only 8250 compatible ports are supported, but
others can easily be added.
-+config SERIAL_DANUBE
++config SERIAL_IFXMIPS
+ bool "Danube serial driver"
-+ depends on DANUBE
++ depends on IFXMIPS
+ help
+ Driver for the danubes built in ASC hardware
+
@@ -21,7 +21,7 @@ Index: linux-2.6.23/drivers/serial/Makefile
obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
-+obj-$(CONFIG_SERIAL_DANUBE) += danube_asc.o
++obj-$(CONFIG_SERIAL_IFXMIPS) += danube_asc.o
Index: linux-2.6.23/drivers/mtd/maps/Makefile
===================================================================
--- linux-2.6.23.orig/drivers/mtd/maps/Makefile 2007-12-13 20:41:42.000000000 +0100
@@ -30,7 +30,7 @@ Index: linux-2.6.23/drivers/mtd/maps/Makefile
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
-+obj-$(CONFIG_MTD_DANUBE) += danube.o
++obj-$(CONFIG_MTD_IFXMIPS) += danube.o
Index: linux-2.6.23/drivers/net/Kconfig
===================================================================
--- linux-2.6.23.orig/drivers/net/Kconfig 2007-12-13 20:41:42.000000000 +0100
@@ -39,15 +39,15 @@ Index: linux-2.6.23/drivers/net/Kconfig
source "drivers/net/arm/Kconfig"
-+config DANUBE_MII0
++config IFXMIPS_MII0
+ tristate "Infineon Danube eth0 driver"
-+ depends on DANUBE
++ depends on IFXMIPS
+ help
+ Support for the MII0 inside the Danube SOC
+
-+config DANUBE_MII1
++config IFXMIPS_MII1
+ tristate "Infineon Danube eth1 driver"
-+ depends on DANUBE
++ depends on IFXMIPS
+ help
+ Support for the MII1 inside the Danube SOC
+
@@ -62,7 +62,7 @@ Index: linux-2.6.23/drivers/net/Makefile
obj-$(CONFIG_FEC_8XX) += fec_8xx/
obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
obj-$(CONFIG_MLX4_CORE) += mlx4/
-+obj-$(CONFIG_DANUBE_MII0) += danube_mii0.o
++obj-$(CONFIG_IFXMIPS_MII0) += danube_mii0.o
obj-$(CONFIG_MACB) += macb.o
@@ -74,7 +74,7 @@ Index: linux-2.6.23/drivers/char/watchdog/Makefile
obj-$(CONFIG_INDYDOG) += indydog.o
obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
-+obj-$(CONFIG_DANUBE_WDT) += danube_wdt.o
++obj-$(CONFIG_IFXMIPS_WDT) += danube_wdt.o
# PARISC Architecture
@@ -87,7 +87,7 @@ Index: linux-2.6.23/drivers/char/Makefile
endif
+
-+obj-$(CONFIG_DANUBE_LED) += danube_led.o
-+obj-$(CONFIG_DANUBE_GPIO) += danube_gpio.o
-+obj-$(CONFIG_DANUBE_SSC) += danube_ssc.o
-+obj-$(CONFIG_DANUBE_EEPROM) += danube_eeprom.o
++obj-$(CONFIG_IFXMIPS_LED) += danube_led.o
++obj-$(CONFIG_IFXMIPS_GPIO) += danube_gpio.o
++obj-$(CONFIG_IFXMIPS_SSC) += danube_ssc.o
++obj-$(CONFIG_IFXMIPS_EEPROM) += danube_eeprom.o
diff --git a/target/linux/ifxmips/patches/160-cfi-swap.patch b/target/linux/ifxmips/patches/160-cfi-swap.patch
index ca70928713..116503f65d 100644
--- a/target/linux/ifxmips/patches/160-cfi-swap.patch
+++ b/target/linux/ifxmips/patches/160-cfi-swap.patch
@@ -7,7 +7,7 @@ Index: linux-2.6.23/drivers/mtd/chips/cfi_cmdset_0002.c
map_word oldd;
int retry_cnt = 0;
-
-+#ifdef CONFIG_DANUBE
++#ifdef CONFIG_IFXMIPS
+ adr ^= 2;
+#endif
adr += chip->start;
--
cgit v1.2.3