From 0aa6c7df60d0d4a4fa01dc1b185df31ffb2c53f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 12 Jun 2016 11:49:46 +0200 Subject: kernel: update kernel 4.4 to version 4.4.13 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- ...-add-a-round-up-ability-to-the-clock-divi.patch | 10 ++--- ...cm2835-Support-for-clock-parent-selection.patch | 8 ++-- .../0254-clk-bcm2835-Add-PWM-clock-support.patch | 2 +- ...-pll_off-should-only-update-CM_PLL_ANARST.patch | 43 ---------------------- ...bcm2835-divider-value-has-to-be-1-or-more.patch | 36 ------------------ ...-correctly-enable-fractional-clock-suppor.patch | 6 +-- ...-clk-bcm2835-clean-up-coding-style-issues.patch | 4 +- ...35-expose-raw-clock-registers-via-debugfs.patch | 14 +++---- ...-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch | 4 +- ...-reorganize-bcm2835_clock_array-assignmen.patch | 4 +- ...lk-bcm2835-enable-management-of-PCM-clock.patch | 2 +- ...lk-bcm2835-add-missing-PLL-clock-dividers.patch | 4 +- ...lk-bcm2835-add-missing-osc-and-per-clocks.patch | 12 +++--- .../0266-clk-bcm2835-Fix-PLL-poweron.patch | 6 +-- ...lk-bcm2835-Mark-the-VPU-clock-as-critical.patch | 4 +- ...-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch | 4 +- ...-Skip-PLLC-clocks-when-deciding-on-a-new-.patch | 4 +- 17 files changed, 44 insertions(+), 123 deletions(-) delete mode 100644 target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-pll_off-should-only-update-CM_PLL_ANARST.patch delete mode 100644 target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-divider-value-has-to-be-1-or-more.patch (limited to 'target/linux/brcm2708') diff --git a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch index b83cd8be56..5866df4d38 100644 --- a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch +++ b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch @@ -17,7 +17,7 @@ Signed-off-by: Michael Turquette --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1154,22 +1154,24 @@ static int bcm2835_clock_is_on(struct cl +@@ -1164,22 +1164,24 @@ static int bcm2835_clock_is_on(struct cl static u32 bcm2835_clock_choose_div(struct clk_hw *hw, unsigned long rate, @@ -48,9 +48,9 @@ Signed-off-by: Michael Turquette + div += unused_frac_mask + 1; + div &= ~unused_frac_mask; - /* Clamp to the limits. */ - div = max(div, unused_frac_mask + 1); -@@ -1208,7 +1210,7 @@ static long bcm2835_clock_round_rate(str + /* clamp to min divider of 1 */ + div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS); +@@ -1219,7 +1221,7 @@ static long bcm2835_clock_round_rate(str unsigned long *parent_rate) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); @@ -59,7 +59,7 @@ Signed-off-by: Michael Turquette return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div); } -@@ -1277,7 +1279,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1288,7 +1290,7 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; diff --git a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch index aeb5134ef1..f2221f3d3f 100644 --- a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch +++ b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch @@ -24,7 +24,7 @@ Signed-off-by: Michael Turquette --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1205,16 +1205,6 @@ static long bcm2835_clock_rate_from_divi +@@ -1216,16 +1216,6 @@ static long bcm2835_clock_rate_from_divi return temp; } @@ -41,7 +41,7 @@ Signed-off-by: Michael Turquette static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, unsigned long parent_rate) { -@@ -1286,13 +1276,75 @@ static int bcm2835_clock_set_rate(struct +@@ -1297,13 +1287,75 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -118,7 +118,7 @@ Signed-off-by: Michael Turquette }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1308,7 +1360,9 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1319,7 +1371,9 @@ static const struct clk_ops bcm2835_vpu_ .is_prepared = bcm2835_vpu_clock_is_on, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, @@ -129,7 +129,7 @@ Signed-off-by: Michael Turquette }; static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, -@@ -1402,45 +1456,23 @@ static struct clk *bcm2835_register_cloc +@@ -1413,45 +1467,23 @@ static struct clk *bcm2835_register_cloc { struct bcm2835_clock *clock; struct clk_init_data init; diff --git a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch index fc18c6c7d1..b0d2ec2917 100644 --- a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch +++ b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch @@ -33,7 +33,7 @@ Signed-off-by: Michael Turquette struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1590,6 +1600,9 @@ static int bcm2835_clk_probe(struct plat +@@ -1601,6 +1611,9 @@ static int bcm2835_clk_probe(struct plat cprman->regs + CM_PERIICTL, CM_GATE_BIT, 0, &cprman->regs_lock); diff --git a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-pll_off-should-only-update-CM_PLL_ANARST.patch b/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-pll_off-should-only-update-CM_PLL_ANARST.patch deleted file mode 100644 index 6199cbe32b..0000000000 --- a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-pll_off-should-only-update-CM_PLL_ANARST.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 4d4b769727386c6a1b7274e3083cc6b24364b4fa Mon Sep 17 00:00:00 2001 -From: Martin Sperl -Date: Mon, 29 Feb 2016 11:39:17 +0000 -Subject: [PATCH 256/381] clk: bcm2835: pll_off should only update - CM_PLL_ANARST - -bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control -register, which may lose the other bits that are currently set by the -clock dividers. - -It also now locks during the read/modify/write cycle of both -registers. - -Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the -audio domain clocks") - -Signed-off-by: Martin Sperl -Signed-off-by: Eric Anholt -Reviewed-by: Eric Anholt -(cherry picked from commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06) ---- - drivers/clk/bcm/clk-bcm2835.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/clk/bcm/clk-bcm2835.c -+++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -913,8 +913,14 @@ static void bcm2835_pll_off(struct clk_h - struct bcm2835_cprman *cprman = pll->cprman; - const struct bcm2835_pll_data *data = pll->data; - -- cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); -- cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); -+ spin_lock(&cprman->regs_lock); -+ cprman_write(cprman, data->cm_ctrl_reg, -+ cprman_read(cprman, data->cm_ctrl_reg) | -+ CM_PLL_ANARST); -+ cprman_write(cprman, data->a2w_ctrl_reg, -+ cprman_read(cprman, data->a2w_ctrl_reg) | -+ A2W_PLL_CTRL_PWRDN); -+ spin_unlock(&cprman->regs_lock); - } - - static int bcm2835_pll_on(struct clk_hw *hw) diff --git a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-divider-value-has-to-be-1-or-more.patch b/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-divider-value-has-to-be-1-or-more.patch deleted file mode 100644 index 49bbacd955..0000000000 --- a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-divider-value-has-to-be-1-or-more.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 260572944700ab13fa3f7a68a387556220cef277 Mon Sep 17 00:00:00 2001 -From: Martin Sperl -Date: Mon, 29 Feb 2016 11:39:20 +0000 -Subject: [PATCH 257/381] clk: bcm2835: divider value has to be 1 or more - -Current clamping of a normal divider allows a value < 1 to be valid. - -A divider of < 1 would actually only be possible if we had a PLL... - -So this patch clamps the divider to 1. - -Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the -audio domain clocks") - -Signed-off-by: Martin Sperl -Signed-off-by: Eric Anholt -Reviewed-by: Eric Anholt -(cherry picked from commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e) ---- - drivers/clk/bcm/clk-bcm2835.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/bcm/clk-bcm2835.c -+++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1202,8 +1202,9 @@ static u32 bcm2835_clock_choose_div(stru - div += unused_frac_mask + 1; - div &= ~unused_frac_mask; - -- /* Clamp to the limits. */ -- div = max(div, unused_frac_mask + 1); -+ /* clamp to min divider of 1 */ -+ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS); -+ /* clamp to the highest possible fractional divider */ - div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, - CM_DIV_FRAC_BITS - data->frac_bits)); - diff --git a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch index 8735a9b1e3..73cf8d3abd 100644 --- a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch +++ b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch @@ -67,7 +67,7 @@ Reviewed-by: Eric Anholt }; struct bcm2835_pll { -@@ -1192,7 +1196,7 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1196,7 +1200,7 @@ static u32 bcm2835_clock_choose_div(stru GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; u64 rem; @@ -76,7 +76,7 @@ Reviewed-by: Eric Anholt rem = do_div(temp, rate); div = temp; -@@ -1202,11 +1206,23 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1206,11 +1210,23 @@ static u32 bcm2835_clock_choose_div(stru div += unused_frac_mask + 1; div &= ~unused_frac_mask; @@ -105,7 +105,7 @@ Reviewed-by: Eric Anholt return div; } -@@ -1300,9 +1316,26 @@ static int bcm2835_clock_set_rate(struct +@@ -1304,9 +1320,26 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); diff --git a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-clean-up-coding-style-issues.patch b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-clean-up-coding-style-issues.patch index 538ebb7e07..b9d6af5b28 100644 --- a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-clean-up-coding-style-issues.patch +++ b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-clean-up-coding-style-issues.patch @@ -33,7 +33,7 @@ Signed-off-by: Eric Anholt const char *osc_name; struct clk_onecell_data onecell; -@@ -1340,7 +1337,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1344,7 +1341,7 @@ static int bcm2835_clock_set_rate(struct } static int bcm2835_clock_determine_rate(struct clk_hw *hw, @@ -42,7 +42,7 @@ Signed-off-by: Eric Anholt { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; -@@ -1398,7 +1395,6 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1402,7 +1399,6 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } diff --git a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch index 38ff1a65b8..8d301eac80 100644 --- a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch +++ b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch @@ -58,7 +58,7 @@ Acked-by: Eric Anholt /* * These are fixed clocks. They're probably not all root clocks and it may * be possible to turn them on and off but until this is mapped out better -@@ -1040,6 +1062,36 @@ static int bcm2835_pll_set_rate(struct c +@@ -1044,6 +1066,36 @@ static int bcm2835_pll_set_rate(struct c return 0; } @@ -95,7 +95,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_pll_clk_ops = { .is_prepared = bcm2835_pll_is_on, .prepare = bcm2835_pll_on, -@@ -1047,6 +1099,7 @@ static const struct clk_ops bcm2835_pll_ +@@ -1051,6 +1103,7 @@ static const struct clk_ops bcm2835_pll_ .recalc_rate = bcm2835_pll_get_rate, .set_rate = bcm2835_pll_set_rate, .round_rate = bcm2835_pll_round_rate, @@ -103,7 +103,7 @@ Acked-by: Eric Anholt }; struct bcm2835_pll_divider { -@@ -1147,6 +1200,26 @@ static int bcm2835_pll_divider_set_rate( +@@ -1151,6 +1204,26 @@ static int bcm2835_pll_divider_set_rate( return 0; } @@ -130,7 +130,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_pll_divider_clk_ops = { .is_prepared = bcm2835_pll_divider_is_on, .prepare = bcm2835_pll_divider_on, -@@ -1154,6 +1227,7 @@ static const struct clk_ops bcm2835_pll_ +@@ -1158,6 +1231,7 @@ static const struct clk_ops bcm2835_pll_ .recalc_rate = bcm2835_pll_divider_get_rate, .set_rate = bcm2835_pll_divider_set_rate, .round_rate = bcm2835_pll_divider_round_rate, @@ -138,7 +138,7 @@ Acked-by: Eric Anholt }; /* -@@ -1395,6 +1469,31 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1399,6 +1473,31 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } @@ -170,7 +170,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_clock_clk_ops = { .is_prepared = bcm2835_clock_is_on, .prepare = bcm2835_clock_on, -@@ -1404,6 +1503,7 @@ static const struct clk_ops bcm2835_cloc +@@ -1408,6 +1507,7 @@ static const struct clk_ops bcm2835_cloc .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, @@ -178,7 +178,7 @@ Acked-by: Eric Anholt }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1422,6 +1522,7 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1426,6 +1526,7 @@ static const struct clk_ops bcm2835_vpu_ .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, diff --git a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch index 087eaf1977..0c338ce4a8 100644 --- a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch +++ b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch @@ -57,7 +57,7 @@ Reviewed-by: Eric Anholt struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1654,14 +1673,81 @@ static struct clk *bcm2835_register_cloc +@@ -1658,14 +1677,81 @@ static struct clk *bcm2835_register_cloc return devm_clk_register(cprman->dev, &clock->hw); } @@ -140,7 +140,7 @@ Reviewed-by: Eric Anholt if (!cprman) return -ENOMEM; -@@ -1678,80 +1764,15 @@ static int bcm2835_clk_probe(struct plat +@@ -1682,80 +1768,15 @@ static int bcm2835_clk_probe(struct plat platform_set_drvdata(pdev, cprman); diff --git a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch index d6887b19cf..b1b574ceaf 100644 --- a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch +++ b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch @@ -474,7 +474,7 @@ Reviewed-by: Eric Anholt struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1590,7 +1173,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1594,7 +1177,7 @@ bcm2835_register_pll_divider(struct bcm2 memset(&init, 0, sizeof(init)); @@ -483,7 +483,7 @@ Reviewed-by: Eric Anholt init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; -@@ -1689,50 +1272,401 @@ struct bcm2835_clk_desc { +@@ -1693,50 +1276,401 @@ struct bcm2835_clk_desc { const void *data; }; diff --git a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-enable-management-of-PCM-clock.patch b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-enable-management-of-PCM-clock.patch index c67c80cab9..8e9a441bc4 100644 --- a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-enable-management-of-PCM-clock.patch +++ b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-enable-management-of-PCM-clock.patch @@ -17,7 +17,7 @@ Reviewed-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1634,6 +1634,13 @@ static const struct bcm2835_clk_desc clk +@@ -1638,6 +1638,13 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_HSMDIV, .int_bits = 4, .frac_bits = 8), diff --git a/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch index 1b92074202..02385cc4f4 100644 --- a/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch +++ b/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch @@ -14,7 +14,7 @@ Reviewed-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1383,6 +1383,22 @@ static const struct bcm2835_clk_desc clk +@@ -1387,6 +1387,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, .fixed_divider = 1), @@ -37,7 +37,7 @@ Reviewed-by: Eric Anholt /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( -@@ -1497,6 +1513,22 @@ static const struct bcm2835_clk_desc clk +@@ -1501,6 +1517,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, .fixed_divider = 1), diff --git a/target/linux/brcm2708/patches-4.4/0265-clk-bcm2835-add-missing-osc-and-per-clocks.patch b/target/linux/brcm2708/patches-4.4/0265-clk-bcm2835-add-missing-osc-and-per-clocks.patch index d9943ac7da..8be0dce99e 100644 --- a/target/linux/brcm2708/patches-4.4/0265-clk-bcm2835-add-missing-osc-and-per-clocks.patch +++ b/target/linux/brcm2708/patches-4.4/0265-clk-bcm2835-add-missing-osc-and-per-clocks.patch @@ -26,7 +26,7 @@ Reviewed-by: Eric Anholt #define CM_EMMCCTL 0x1c0 #define CM_EMMCDIV 0x1c4 -@@ -1606,6 +1608,12 @@ static const struct bcm2835_clk_desc clk +@@ -1610,6 +1612,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), @@ -39,7 +39,7 @@ Reviewed-by: Eric Anholt /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( -@@ -1620,6 +1628,7 @@ static const struct bcm2835_clk_desc clk +@@ -1624,6 +1632,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_ISPDIV, .int_bits = 4, .frac_bits = 8), @@ -47,7 +47,7 @@ Reviewed-by: Eric Anholt /* * Secondary SDRAM clock. Used for low-voltage modes when the PLL * in the SDRAM controller can't be used. -@@ -1651,6 +1660,36 @@ static const struct bcm2835_clk_desc clk +@@ -1655,6 +1664,36 @@ static const struct bcm2835_clk_desc clk .is_vpu_clock = true), /* clocks with per parent mux */ @@ -84,7 +84,7 @@ Reviewed-by: Eric Anholt /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( -@@ -1659,6 +1698,29 @@ static const struct bcm2835_clk_desc clk +@@ -1663,6 +1702,29 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_EMMCDIV, .int_bits = 4, .frac_bits = 8), @@ -114,7 +114,7 @@ Reviewed-by: Eric Anholt /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( .name = "hsm", -@@ -1680,12 +1742,26 @@ static const struct bcm2835_clk_desc clk +@@ -1684,12 +1746,26 @@ static const struct bcm2835_clk_desc clk .int_bits = 12, .frac_bits = 12, .is_mash_clock = true), @@ -141,7 +141,7 @@ Reviewed-by: Eric Anholt /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( .name = "vec", -@@ -1694,6 +1770,20 @@ static const struct bcm2835_clk_desc clk +@@ -1698,6 +1774,20 @@ static const struct bcm2835_clk_desc clk .int_bits = 4, .frac_bits = 0), diff --git a/target/linux/brcm2708/patches-4.4/0266-clk-bcm2835-Fix-PLL-poweron.patch b/target/linux/brcm2708/patches-4.4/0266-clk-bcm2835-Fix-PLL-poweron.patch index 6762263d76..fcc950df0f 100644 --- a/target/linux/brcm2708/patches-4.4/0266-clk-bcm2835-Fix-PLL-poweron.patch +++ b/target/linux/brcm2708/patches-4.4/0266-clk-bcm2835-Fix-PLL-poweron.patch @@ -19,9 +19,9 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -557,6 +557,10 @@ static int bcm2835_pll_on(struct clk_hw - const struct bcm2835_pll_data *data = pll->data; - ktime_t timeout; +@@ -561,6 +561,10 @@ static int bcm2835_pll_on(struct clk_hw + cprman_read(cprman, data->a2w_ctrl_reg) & + ~A2W_PLL_CTRL_PWRDN); + cprman_write(cprman, data->a2w_ctrl_reg, + cprman_read(cprman, data->a2w_ctrl_reg) & diff --git a/target/linux/brcm2708/patches-4.4/0349-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch b/target/linux/brcm2708/patches-4.4/0349-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch index 2275957a3b..95bcb497f5 100644 --- a/target/linux/brcm2708/patches-4.4/0349-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch +++ b/target/linux/brcm2708/patches-4.4/0349-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch @@ -27,7 +27,7 @@ Signed-off-by: Eric Anholt bool is_vpu_clock; bool is_mash_clock; }; -@@ -1242,7 +1244,7 @@ static struct clk *bcm2835_register_cloc +@@ -1246,7 +1248,7 @@ static struct clk *bcm2835_register_cloc init.parent_names = parents; init.num_parents = data->num_mux_parents; init.name = data->name; @@ -36,7 +36,7 @@ Signed-off-by: Eric Anholt if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; -@@ -1661,6 +1663,7 @@ static const struct bcm2835_clk_desc clk +@@ -1665,6 +1667,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_VPUDIV, .int_bits = 12, .frac_bits = 8, diff --git a/target/linux/brcm2708/patches-4.4/0350-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch b/target/linux/brcm2708/patches-4.4/0350-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch index a4708f9eff..01c1c1b64e 100644 --- a/target/linux/brcm2708/patches-4.4/0350-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch +++ b/target/linux/brcm2708/patches-4.4/0350-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch @@ -20,7 +20,7 @@ Signed-off-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1246,6 +1246,15 @@ static struct clk *bcm2835_register_cloc +@@ -1250,6 +1250,15 @@ static struct clk *bcm2835_register_cloc init.name = data->name; init.flags = data->flags | CLK_IGNORE_UNUSED; @@ -36,7 +36,7 @@ Signed-off-by: Eric Anholt if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; } else { -@@ -1720,13 +1729,15 @@ static const struct bcm2835_clk_desc clk +@@ -1724,13 +1733,15 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_GP1DIV, .int_bits = 12, .frac_bits = 12, diff --git a/target/linux/brcm2708/patches-4.4/0351-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch b/target/linux/brcm2708/patches-4.4/0351-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch index 634db51224..d8c80918e4 100644 --- a/target/linux/brcm2708/patches-4.4/0351-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch +++ b/target/linux/brcm2708/patches-4.4/0351-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch @@ -22,7 +22,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1020,16 +1020,28 @@ static int bcm2835_clock_set_rate(struct +@@ -1024,16 +1024,28 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -51,7 +51,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain /* * Select parent clock that results in the closest but lower rate */ -@@ -1037,6 +1049,17 @@ static int bcm2835_clock_determine_rate( +@@ -1041,6 +1053,17 @@ static int bcm2835_clock_determine_rate( parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; -- cgit v1.2.3