From 029093a302c9a66b74bec46285a179abd122a40a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 21 Feb 2021 10:00:18 +0100 Subject: bmips: add new target MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas Acked-by: Adrian Schmutzler --- .../bcm6368-interrupt-controller.h | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h (limited to 'target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h') diff --git a/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h new file mode 100644 index 0000000000..96a73d645e --- /dev/null +++ b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H +#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H + +#define BCM6368_IRQ_TIMER 0 +#define BCM6368_IRQ_SPI 1 +#define BCM6368_IRQ_UART0 2 +#define BCM6368_IRQ_UART1 3 +#define BCM6368_IRQ_XDSL 4 +#define BCM6368_IRQ_OHCI 5 +#define BCM6368_IRQ_IPSEC 6 +#define BCM6368_IRQ_EHCI 7 +#define BCM6368_IRQ_USBS 8 +#define BCM6368_IRQ_RING_OSC 9 +#define BCM6368_IRQ_NAND 10 +#define BCM6368_IRQ_ATM 11 +#define BCM6368_IRQ_PCM 12 +#define BCM6368_IRQ_MPI 13 +#define BCM6368_IRQ_DG 14 +#define BCM6368_IRQ_EPHY 15 +#define BCM6368_IRQ_EPHY_EN0 16 +#define BCM6368_IRQ_EPHY_EN1 17 +#define BCM6368_IRQ_EPHY_EN2 18 +#define BCM6368_IRQ_EPHY_EN3 19 +#define BCM6368_IRQ_EXT0 20 +#define BCM6368_IRQ_EXT1 21 +#define BCM6368_IRQ_EXT2 22 +#define BCM6368_IRQ_EXT3 23 +#define BCM6368_IRQ_EXT4 24 +#define BCM6368_IRQ_EXT5 25 +#define BCM6368_IRQ_USB_CTL_RX_DMA 26 +#define BCM6368_IRQ_USB_CTL_TX_DMA 27 +#define BCM6368_IRQ_USB_BULK_RX_DMA 28 +#define BCM6368_IRQ_USB_BULK_TX_DMA 29 +#define BCM6368_IRQ_USB_ISO_RX_DMA 30 +#define BCM6368_IRQ_USB_ISO_TX_DMA 31 +#define BCM6368_IRQ_ENETSW_RX_DMA0 32 +#define BCM6368_IRQ_ENETSW_RX_DMA1 33 +#define BCM6368_IRQ_ENETSW_RX_DMA2 34 +#define BCM6368_IRQ_ENETSW_RX_DMA3 35 +#define BCM6368_IRQ_ENETSW_TX_DMA0 36 +#define BCM6368_IRQ_ENETSW_TX_DMA1 37 +#define BCM6368_IRQ_ENETSW_TX_DMA2 38 +#define BCM6368_IRQ_ENETSW_TX_DMA3 39 +#define BCM6368_IRQ_ATM_DMA0 40 +#define BCM6368_IRQ_ATM_DMA1 41 +#define BCM6368_IRQ_ATM_DMA2 42 +#define BCM6368_IRQ_ATM_DMA3 43 +#define BCM6368_IRQ_ATM_DMA4 44 +#define BCM6368_IRQ_ATM_DMA5 45 +#define BCM6368_IRQ_ATM_DMA6 46 +#define BCM6368_IRQ_ATM_DMA7 47 +#define BCM6368_IRQ_ATM_DMA8 48 +#define BCM6368_IRQ_ATM_DMA9 49 +#define BCM6368_IRQ_ATM_DMA10 50 +#define BCM6368_IRQ_ATM_DMA11 51 +#define BCM6368_IRQ_ATM_DMA12 52 +#define BCM6368_IRQ_ATM_DMA13 53 +#define BCM6368_IRQ_ATM_DMA14 54 +#define BCM6368_IRQ_ATM_DMA15 55 +#define BCM6368_IRQ_ATM_DMA16 56 +#define BCM6368_IRQ_ATM_DMA17 57 +#define BCM6368_IRQ_ATM_DMA18 58 +#define BCM6368_IRQ_ATM_DMA19 59 +#define BCM6368_IRQ_IPSEC_DMA0 60 +#define BCM6368_IRQ_IPSEC_DMA1 61 +#define BCM6368_IRQ_PCM_DMA0 62 +#define BCM6368_IRQ_PCM_DMA1 63 + +#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H */ -- cgit v1.2.3