From ca5c695a4522091234026e22e8336f05d65602ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Mon, 22 Aug 2022 14:02:36 +0200 Subject: kernel: bump 5.15 to 5.15.62 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deleted following upstreamed patches: bcm27xx: 950-0006-drm-vc4-hdmi-Fix-HPD-GPIO-detection.patch bcm27xx: 950-0420-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx: 950-0425-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx: 950-0432-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx: 950-0433-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx: 950-0435-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx: 950-0436-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx: 950-0437-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx: 950-0438-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx: 950-0443-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx: 950-0445-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch bcm27xx: 950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch bcm27xx: 950-0476-drm-vc4-Release-workaround-buffer-and-DMA-in-error-p.patch bcm27xx: 950-0477-drm-vc4-Correct-DSI-divider-calculations.patch bcm27xx: 950-0664-drm-vc4-dsi-Correct-max-divider-to-255-not-7.patch bcm53xx: 072-next-ARM_dts_BCM53015-add-mr26.patch mediatek: 920-linux-next-dts-mt7622-bpi-r64-fix-wps-button.patch Manually rebased following patches: bcm27xx: 950-0004-drm-vc4-hdmi-Remove-the-DDC-probing-for-status-detec.patch bcm27xx: 950-0700-net-phy-lan87xx-Decrease-phy-polling-rate.patch bcm27xx: 950-0711-drm-vc4-Rename-bridge-to-out_bridge.patch bcm27xx: 950-0713-drm-vc4-Remove-splitting-the-bridge-chain-from-the-d.patch bcm27xx: 950-0715-drm-vc4-Convert-vc4_dsi-to-using-a-bridge-instead-of.patch bcm27xx: 950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch bcm27xx: 950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch Runtime tested on turris-omnia and glinet-b1300. Tested-by: John Audia [bcm2711/RPi4B, mt7622/RT3200] Signed-off-by: Petr Štetiar --- ..._plane-Keep-fractional-source-coords-insi.patch | 41 +++++++++++----------- 1 file changed, 21 insertions(+), 20 deletions(-) (limited to 'target/linux/bcm27xx/patches-5.15/950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch') diff --git a/target/linux/bcm27xx/patches-5.15/950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch b/target/linux/bcm27xx/patches-5.15/950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch index 715f9b1930..7bb57aafa5 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch @@ -35,18 +35,19 @@ Signed-off-by: Dom Cobley return VC4_SCALING_PPF; else return VC4_SCALING_TPZ; -@@ -388,14 +388,10 @@ static int vc4_plane_setup_clipping_and_ +@@ -388,15 +388,10 @@ static int vc4_plane_setup_clipping_and_ for (i = 0; i < num_planes; i++) vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; -- /* We don't support subpixel source positioning for scaling, +- /* +- * We don't support subpixel source positioning for scaling, - * but fractional coordinates can be generated by clipping - * so just round for now - */ -- vc4_state->src_x = DIV_ROUND_CLOSEST(state->src.x1, 1<<16); -- vc4_state->src_y = DIV_ROUND_CLOSEST(state->src.y1, 1<<16); -- vc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1<<16) - vc4_state->src_x; -- vc4_state->src_h[0] = DIV_ROUND_CLOSEST(state->src.y2, 1<<16) - vc4_state->src_y; +- vc4_state->src_x = DIV_ROUND_CLOSEST(state->src.x1, 1 << 16); +- vc4_state->src_y = DIV_ROUND_CLOSEST(state->src.y1, 1 << 16); +- vc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1 << 16) - vc4_state->src_x; +- vc4_state->src_h[0] = DIV_ROUND_CLOSEST(state->src.y2, 1 << 16) - vc4_state->src_y; + vc4_state->src_x = state->src.x1; + vc4_state->src_y = state->src.y1; + vc4_state->src_w[0] = state->src.x2 - vc4_state->src_x; @@ -54,7 +55,7 @@ Signed-off-by: Dom Cobley vc4_state->crtc_x = state->dst.x1; vc4_state->crtc_y = state->dst.y1; -@@ -448,7 +444,7 @@ static void vc4_write_tpz(struct vc4_pla +@@ -449,7 +444,7 @@ static void vc4_write_tpz(struct vc4_pla { u32 scale, recip; @@ -63,7 +64,7 @@ Signed-off-by: Dom Cobley /* The specs note that while the reciprocal would be defined * as (1<<32)/scale, ~0 is close enough. -@@ -494,7 +490,7 @@ static u32 vc4_lbm_size(struct drm_plane +@@ -495,7 +490,7 @@ static u32 vc4_lbm_size(struct drm_plane if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ) pix_per_line = vc4_state->crtc_w; else @@ -72,7 +73,7 @@ Signed-off-by: Dom Cobley if (!vc4_state->is_yuv) { if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) -@@ -585,7 +581,8 @@ static void vc4_plane_calc_load(struct d +@@ -586,7 +581,8 @@ static void vc4_plane_calc_load(struct d for (i = 0; i < fb->format->num_planes; i++) { /* Even if the bandwidth/plane required for a single frame is * @@ -82,7 +83,7 @@ Signed-off-by: Dom Cobley * * when downscaling, we have to read more pixels per line in * the time frame reserved for a single line, so the bandwidth -@@ -594,11 +591,11 @@ static void vc4_plane_calc_load(struct d +@@ -595,11 +591,11 @@ static void vc4_plane_calc_load(struct d * load by this number. We're likely over-estimating the read * demand, but that's better than under-estimating it. */ @@ -98,7 +99,7 @@ Signed-off-by: Dom Cobley vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; } -@@ -751,7 +748,8 @@ static int vc4_plane_mode_set(struct drm +@@ -752,7 +748,8 @@ static int vc4_plane_mode_set(struct drm bool mix_plane_alpha; bool covers_screen; u32 scl0, scl1, pitch0; @@ -108,7 +109,7 @@ Signed-off-by: Dom Cobley u32 hvs_format = format->hvs; unsigned int rotation; int ret, i; -@@ -763,6 +761,9 @@ static int vc4_plane_mode_set(struct drm +@@ -764,6 +761,9 @@ static int vc4_plane_mode_set(struct drm if (ret) return ret; @@ -118,7 +119,7 @@ Signed-off-by: Dom Cobley /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB * and 4:4:4, scl1 should be set to scl0 so both channels of * the scaler do the same thing. For YUV, the Y plane needs -@@ -783,9 +784,11 @@ static int vc4_plane_mode_set(struct drm +@@ -784,9 +784,11 @@ static int vc4_plane_mode_set(struct drm DRM_MODE_REFLECT_Y); /* We must point to the last line when Y reflection is enabled. */ @@ -132,7 +133,7 @@ Signed-off-by: Dom Cobley switch (base_format_mod) { case DRM_FORMAT_MOD_LINEAR: -@@ -800,7 +803,7 @@ static int vc4_plane_mode_set(struct drm +@@ -801,7 +803,7 @@ static int vc4_plane_mode_set(struct drm (i ? v_subsample : 1) * fb->pitches[i]; @@ -141,7 +142,7 @@ Signed-off-by: Dom Cobley (i ? h_subsample : 1) * fb->format->cpp[i]; } -@@ -823,7 +826,7 @@ static int vc4_plane_mode_set(struct drm +@@ -824,7 +826,7 @@ static int vc4_plane_mode_set(struct drm * pitch * tile_h == tile_size * tiles_per_row */ u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); @@ -150,7 +151,7 @@ Signed-off-by: Dom Cobley u32 tiles_r = tiles_w - tiles_l; u32 tiles_t = src_y >> tile_h_shift; /* Intra-tile offsets, which modify the base address (the -@@ -833,7 +836,7 @@ static int vc4_plane_mode_set(struct drm +@@ -834,7 +836,7 @@ static int vc4_plane_mode_set(struct drm u32 tile_y = (src_y >> 4) & 1; u32 subtile_y = (src_y >> 2) & 3; u32 utile_y = src_y & 3; @@ -159,7 +160,7 @@ Signed-off-by: Dom Cobley u32 y_off = src_y & tile_h_mask; /* When Y reflection is requested we must set the -@@ -929,7 +932,7 @@ static int vc4_plane_mode_set(struct drm +@@ -930,7 +932,7 @@ static int vc4_plane_mode_set(struct drm * of the 12-pixels in that 128-bit word is the * first pixel to be used */ @@ -168,7 +169,7 @@ Signed-off-by: Dom Cobley u32 aligned = remaining_pixels / 12; u32 last_bits = remaining_pixels % 12; -@@ -951,12 +954,12 @@ static int vc4_plane_mode_set(struct drm +@@ -952,12 +954,12 @@ static int vc4_plane_mode_set(struct drm return -EINVAL; } pix_per_tile = tile_w / fb->format->cpp[0]; @@ -183,7 +184,7 @@ Signed-off-by: Dom Cobley vc4_state->offsets[i] += param * tile_w * tile; vc4_state->offsets[i] += src_y / -@@ -1017,10 +1020,8 @@ static int vc4_plane_mode_set(struct drm +@@ -1018,10 +1020,8 @@ static int vc4_plane_mode_set(struct drm vc4_dlist_write(vc4_state, (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | vc4_hvs4_get_alpha_blend_mode(state) | @@ -196,7 +197,7 @@ Signed-off-by: Dom Cobley /* Position Word 3: Context. Written by the HVS. */ vc4_dlist_write(vc4_state, 0xc0c0c0c0); -@@ -1078,10 +1079,8 @@ static int vc4_plane_mode_set(struct drm +@@ -1079,10 +1079,8 @@ static int vc4_plane_mode_set(struct drm /* Position Word 2: Source Image Size */ vc4_state->pos2_offset = vc4_state->dlist_count; vc4_dlist_write(vc4_state, -- cgit v1.2.3