From 387736af41444945da6a5e51748e91011569c03e Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Tue, 7 Aug 2018 12:02:07 +0800 Subject: ath79: ag71xx: remove PHY reset Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo --- target/linux/ath79/dts/ar9132.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/linux/ath79/dts/ar9132.dtsi') diff --git a/target/linux/ath79/dts/ar9132.dtsi b/target/linux/ath79/dts/ar9132.dtsi index d079811fe6..f3105e330d 100644 --- a/target/linux/ath79/dts/ar9132.dtsi +++ b/target/linux/ath79/dts/ar9132.dtsi @@ -191,6 +191,6 @@ pll-data = <0x1a000000 0x13000a44 0x00441099>; pll-reg = <0x4 0x10 17>; pll-handle = <&pll>; - resets = <&rst 8>, <&rst 9>; - reset-names = "phy", "mac"; + resets = <&rst 9>; + reset-names = "mac"; }; -- cgit v1.2.3