From d32c8f92c0fa25bd490a2196c32aa32cc1baa680 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 11 Jun 2009 07:18:05 +0000 Subject: [ar71xx] flush more register writings git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16415 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ar71xx/irq.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index 797e6f81a5..7d204fd668 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -113,6 +113,9 @@ static void ar71xx_gpio_irq_unmask(unsigned int irq) irq -= AR71XX_GPIO_IRQ_BASE; ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_gpio_rr(GPIO_REG_INT_ENABLE); } static void ar71xx_gpio_irq_mask(unsigned int irq) @@ -120,6 +123,9 @@ static void ar71xx_gpio_irq_mask(unsigned int irq) irq -= AR71XX_GPIO_IRQ_BASE; ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_gpio_rr(GPIO_REG_INT_ENABLE); } #if 0 @@ -211,6 +217,9 @@ static void ar71xx_misc_irq_unmask(unsigned int irq) irq -= AR71XX_MISC_IRQ_BASE; ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); } static void ar71xx_misc_irq_mask(unsigned int irq) @@ -218,6 +227,9 @@ static void ar71xx_misc_irq_mask(unsigned int irq) irq -= AR71XX_MISC_IRQ_BASE; ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); } struct irq_chip ar71xx_misc_irq_chip = { -- cgit v1.2.3