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* realtek: fix RTL838x receive tag decodingBjørn Mork2022-09-081-3/+6
| | | | | | | | | | | | | | | | | | | Commit dc9cc0d3e2a1 ("realtek: add QoS and rate control") replaced a 16 bit reserved field in the RTL83xx packet header with the initial cpu_tag word, shifting the real cpu_tag fields by one. Adjusting for this new shift was partially forgotten in the new RX tag decoders. This caused the switch to block IGMP, effectively blocking IPv4 multicast. The bug was partially fixed by commit 9d847244d9fd ("realtek: fix RTL839X receive tag decoding") Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value. Suggested-by: Jan Hoffmann <jan@3e8.eu> Fixes: dc9cc0d3e2a1 ("realtek: add QoS and rate control") Signed-off-by: Bjørn Mork <bjorn@mork.no>
* realtek: replace fix for spurious GPIO interruptsSander Vanheule2022-09-042-30/+373
| | | | | | | | | | | | | 8 and 16 bit writes to the GPIO peripheral are apparently not supported, and only worked most of the time. This resulted in garbabe writes to the interrupt mask registers, causing spurious unhandled interrupts, which could lead to CPU lock-ups as these kept retriggering. Instead of clearing these spurious interrupt when they occur, the upstream patch will just make sure all register writes have the intended result, so these don't happen at all. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: Fix missing clock module CONFIG settingMarkus Stockhausen2022-08-311-0/+1
| | | | | | | Since introduction of clock driver we have a new kernel config setting. Provide an initial value for the 930x targets. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: fix PLL register inconsistenciesMarkus Stockhausen2022-08-311-0/+3
| | | | | | | Some devices have wrong/empty values in the PLL registers. Work around that by reporting the default values. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* kernel: bump 5.10 to 5.10.139John Audia2022-08-312-27/+21
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* realtek: tl-sg2008p: fix labeling of lan portsAlexandru Gagniuc2022-08-291-8/+8
| | | | | | | | The SG2008P has its ethernet ports in the rear, and LEDs in the front. The ports should be labeled lan8->lan1, not lan1->lan8. To resolve this, fix the phy mapping in the "ports" node. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: tl-sg2008p: use correct i2c address for TPS23861Alexandru Gagniuc2022-08-291-2/+2
| | | | | | | | Address 0x30 is a "broadcast" address for the TPS23861. It should not be used by drivers, as all TPS23861 devices on the bus are supposed to respond. Change this to the correct address, 0x28. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: ignore disabled switch portsSander Vanheule2022-08-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When marking a switch port as disabled in the device tree, by using 'status = "disabled";', the switch driver fails on boot, causing a restart: CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802c3064, ra == 8022b4b4 [ ... ] Call Trace: [<802c3064>] strlen+0x0/0x2c [<8022b4b4>] start_creating.part.0+0x78/0x194 [<8022bd3c>] debugfs_create_dir+0x44/0x1c0 [<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258 [<80397508>] rtl838x_dbgfs_init+0xe0/0x56c This is caused by the DSA subsystem (mostly) ignoring the port, while rtl83xx_mdio_probe() still extracts some details on this disabled port from the device tree, resulting in the usage of a NULL pointer where a port name is expected. By not probing ignoring disabled ports, no attempt is made to create a debugfs directory later. The device then boots as expected without the disabled port. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: switch RTL838X/RTL839X DT to new clock driverMarkus Stockhausen2022-08-282-20/+141
| | | | | | | | | | | | | | Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work we need to change some nodes: - define the external oscillator speed (25MHz) - define SRAM - add clock controller - Add second CPU for RTL839X - map all devices to new clocks - Remove dummy LXB clock - add CPU OPP table Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: activate clock driver for RTL838X/RTL839X targetsMarkus Stockhausen2022-08-282-0/+40
| | | | | | | | Make use the new clock driver for RTL838X and RTL839x target devices. Of course we will enable their primary consumer (cpufreq-dt) too. To be careful just set the default governor to userspace. As we rely on SRAM activate that module too. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: enable basic config for cpufreq frameworkMarkus Stockhausen2022-08-281-1/+5
| | | | | | | | | | | | | | | | A new clock driver makes more sense if it can be used from consumers like cpufreq. Before we enable the driver we must tell the config that the RTL838X and RTL839X targets allow CPU frequency changing. Even though these targets currently rely on the CPU's internal R4K timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change testing. The Realtek timers, which are clocked by the Lexra bus, still need to be supported and used in order to provide correct wall times when reclocking the CPU. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [add paragraph about MIPS_EXTERNAL_TIMER to commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add patch to enable new clock driver in kernelMarkus Stockhausen2022-08-281-0/+26
| | | | | | Allow building the clock driver with kernel config options. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: add RTL83XX clock driverMarkus Stockhausen2022-08-286-0/+1151
| | | | | | | | | | | | | | | | | | | Add a new self-contained combined clock & platform driver that allows to access the PLL hardware clocks of RTL83XX devices. Currently it provides info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and additionally allows to change the CPU clocks. Changing the clocks multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and is multithreading safe on the RTL839X. Even a cpufreq initiated change of the CPU clock works fine. Loading the driver will add some meaningful logging. [0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz [0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz, MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [remove trailing whitespaces, C-style SPDX comments for ASM and headers] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add PLL DT binding includesMarkus Stockhausen2022-08-281-0/+15
| | | | | | Add some constants for sharing between DT and drivers. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: more generic platform initializationMarkus Stockhausen2022-08-201-5/+34
| | | | | | | | | Platform startup still "guesses" the CPU clock speed by DT fixed values. If possible take clock rates from a to be developed driver and align to MIPS generic platfom initialization code. Pack old behaviour into a fallback function. We might get rid of that some day. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: d-link: add support for dgs-1210-10mpDaniel Groth2022-08-202-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General hardware info: ------------------------------------------------------------------------------- D-Link DGS-1210-10MP is a switch with 8 ethernet ports and 2 SFP ports, all ports Gbit capable. It is based on a RTL8380 SoC @ 500MHz, DRAM 128MB and 32MB flash. All ethernet ports are 802.3af/at PoE capable with a total PoE power budget of 130W. File info: ------------------------------------------------------------------------------- The dgs-1210-10mp is very similar to dgs-1210-10p so I used that as a start. rtl838x.mk: - Removed lua-rs232 package since it was a leftover from the old rtl83xx-poe package. - Updated the soc to 8380. - Specified device variant: F. - Installed the new realtek-poe package. rtl8380_d-link_dgs-1210-10mp.dts: - Moved dgs-1210 family common parts and non PoE related ports on rtl8231 to the new device tree dtsi files. Serial connection: ------------------------------------------------------------------------------- The UART for the SoC (115200 8N1) is available close to the front panel next to the LED/key card connector via unpopulated standard 0.1" pin header marked j4. Pin1 is marked with arrow and square. Pin 1: Vcc 3,3V Pin 2: Tx Pin 3: Rx Pin 4: Gnd Installation with TFTP from u-boot ------------------------------------------------------------------------------- I originally used the install procedure: 'OpenWrt installation using the TFTP method and serial console access' found in the device wiki for the dgs-1210-16. < https://openwrt.org/toh/d-link/dgs-1210-16_g1#openwrt_installation_using _the_tftp_method_and_serial_console_access > About the realtek-poe package ------------------------------------------------------------------------------- The realtek-poe package is installed but there isn't any automatic PoE config setting at this time so for now the PoE config must be edited manually. Original OEM hardware/firmware data at first installation ------------------------------------------------------------------------------- It has been installed, developed, and tested on a device with these OEM hardware and firmware versions. - U-boot: 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 15:03:58) - Boot version: 1.01.001 - Firmware version: 6.20.007 - Hardware version: F1 Things to be done when support are developed ------------------------------------------------------------------------------- - realtek-poe has been included in OpenWrt but the automatic config handling has not been solved yet so in the future there will probably be some minor updates for this device to handle the poe config. - LED link_act and poe are per function supposed to be connected to the PoE system. But some software development is also needed to make this LED work and shift the LED array between act and poe indication and to shift the mode lights with mode key. - LED poe_max should probably be used as straight forward error output from the realtek-poe package error handling. But no code has been written for this. - SFP is currently not hot pluggable. Development is under progress to get working I2C communication with SFP and have them hot pluggable. When any device in the dgs-1210 family gets this working, I expect it should be possible to implement the same solution in this device. Signed-off-by: Daniel Groth <flygarn12@gmail.com> [Capitalisation of abbreviations, DEVICE_VARIANT and update filenames, device compatibles on single line] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: d-link: dgs-1210 remake of the device treeDaniel Groth2022-08-206-133/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have collected the known information from the dts files we have. After that I made a new device tree that should work for this whole D-Link switch family. This device tree is based on modules where you first select which SoC group the device belongs to. Then you include the GPIO dtsi file depending on what hardware your device has, see examples below. This tree is also expandable for more hardware, see the part 'Future expansion possibilities' further down. ------------------------------------------------------------------------------- The device tree now looks like this: ---------------- | rtl838x.dtsi | // Note 1. ---------------- | | --------------------------------------- | rtl838x_d-link_dgs-1210_common.dtsi | // Note 2. --------------------------------------- | | -------------- |-------| device.dts | // Note 3. | -------------- | ------------------------------------- | rtl83xx_d-link_dgs-1210_gpio.dtsi | // Note 4. ------------------------------------- | | -------------- |-------| device.dts | // Note 5. -------------- Note 1; Included in rtl838x_d-link_dgs-1210_common.dtsi. Note 2; SoC level information and memory mapping. Choose which one to include in the device dts. Note 3; At this point dgs-1210-16 will come out here. Note 4; In this dtsi only common board hardware based on the rtl8231 is found. No PoE based hardware in this dtsi. In this dtsi there is no <#include> to above *_common.dtsi. Note 5; Device dts with only rtl8231 based hardware without PoE will come out here. ------------------------------------------------------------------------------- How to set up in dts file: The device dts will have one of these two <#include> alternatives. This alternative includes only common features: <#include "rtl838x_d-link_dgs-1210_common.dtsi"> This alternative includes common and the rtl8231 GPIO (no PoE) features: <#include "rtl838x_d-link_dgs-1210_common.dtsi"> <#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"> ------------------------------------------------------------------------------- Implementation: Finally, I also implemented this new family device tree on the current supported devices: dgs-1210-10p dgs-1210-16 dgs-1210-20 dgs-1210-28 The implementation for the dgs-1210-10p is different. I have removed the information from the rtl8382_d-link_dgs-1210-10p.dts that is already present in rtl838x_d-link_dgs-1210_common.dtsi. Since the rest isn't officially probed in the device dts I do not want to include the rtl83xx_d-link_dgs-1210_gpio.dtsi with dgs-1210-10p.dts. Since I don't have these devices to test on I have built the original firmware for each one of these devices before this change and saved the dtb file and then compared the original dtb file with the dtb file built with this new device tree. ------------------------------------------------------------------------------- Future expansion possibilities: In parallel with the rtl838x_d-link_dgs-1210_common.dtsi in the tree map we can make a rtl839x_d-link_dgs-1210_common.dtsi to use the rtl839x.dtsi if the need arises with more devices based on rtl839x soc. When we have more PoE devices so the hardware map for these gets more clear we can make a rtl83xx_d-link_dgs-1210_poe.dtsi below the rtl83xx_d-link_dgs-1210_gpio.dtsi in the tree map. I looked at the port and switch setup to see if it could be moved to the dtsi. I decided not to touch this part now. The reason was that there isn't really any meaningful way this could be shared between the devices. The only thing in common over the family is the 8+2sfp ports on the dgs-1210-10xx device. And then there is the hot plug SFP and I2C ports that aren’t implemented on any device. So maybe when we see the whole port map for the family then maybe the ports can be moved to a *_common.dtsi but I don't think it is the right moment for that now. Signed-off-by: Daniel Groth <flygarn12@gmail.com> [Capitalisation of abbreviations and 'D-Link'] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add support for TP-Link SG2008PAlexandru Gagniuc2022-08-135-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the TP-Link SG2008P switch. This is an RTL8380 based switch with 802.3af one the first four ports. Specifications: --------------- * SoC: Realtek RTL8380M * Flash: 32 MiB SPI flash (Vendor varies) * RAM: 256 MiB (Vendor varies) * Ethernet: 8x 10/100/1000 Mbps with PoE on 4 ports * Buttons: 1x "Reset" button on front panel * Power: 53.5V DC barrel jack * UART: 1x serial header, unpopulated * PoE: 1x TI TPS23861 I2C PoE controller Works: ------ - (8) RJ-45 ethernet ports - Switch functions - System LED Not yet enabled: ---------------- - Power-over-Ethernet (driver works, but doesn't enable "auto" mode) - PoE, Link/Act, PoE max and System LEDs Install via web interface: ------------------------- Not supported at this time. Install via serial console/tftp: -------------------------------- The footprints R27 (0201) and R28 (0402) are not populated. To enable serial console, 50 ohm resistors should be soldered -- any value from 0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge. The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at 38400 baud. There is no known way to exit out of this shell, and no way to do anything useful. Ideally, one would trick the bootloader into flashing the sysupgrade image first. However, if the image exceeds 6MiB in size, it will not work. The sysupgrade image can also be flashed. To install OpenWRT: Prepare a tftp server with: 1. server address: 192.168.0.146 2. the image as: "uImage.img" Power on device, and stop boot by pressing any key. Once the shell is active: 1. Ground out the CLK (pin 16) of the ROM (U7) 2. Select option "3. Start" 3. Bootloader notes that "The kernel has been damaged!" 4. Release CLK as sson as bootloader thinks image is corrupted. 5. Bootloader enters automatic recovery -- details printed on console 6. Watch as the bootloader flashes and boots OpenWRT. Blind install via tftp: ----------------------- This method works when it's not feasible to install a serial header. Prepare a tftp server with: 1. server address: 192.168.0.146 2. the image as: "uImage.img" 3. Watch network traffic (tcpdump or wireshark works) 4. Power on the device. 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U7) 6. When 192.168.0.30 makes tftp requests, release pin 16 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: EnGenius EWS2910P: use the mtd3 partition for root overlayAlexandru Gagniuc2022-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | The root overlay is mounted on the "rootfs_data" partition. This comes at the end of the firmware image, courtesy of mtdsplit. There is very little space left (About 1MB), which can fill up rapidly. The "firmware" and "firmware2" partitions are part of the bootloader dual firmware logic. They should contain independent, valid uImages. This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates. mtd3 is about 13.7 MB and is used by the vendor firmware to store configuration settings. It is only erased by vendor firmware during a factory reset. By naming this partition "rootfs_data", it becomes the root overlay, providing significantly more room. Even with mtdsplit wanting to create a "rootfs_data" on the firmware partition, mtd3 is used as the overlay. Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: Netgear GS110TPP v1: add lan9 and lan10Sander Vanheule2022-08-131-0/+12
| | | | | | | | | The original commit for the GS110TP was missing ports 9 and 10. These are provided by an external RTL8214C phy, for which no support was available at the time. Now that this phy is supported, add the missing entries to enable all device ports. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: skip SFP ports in PoE setupPaul Spooren2022-08-131-4/+7
| | | | | | | | | | | | | | The function `ucidef_set_poe` receives a list of ports to add to the PoE array. Since switches have many ports the varibale `lan_list` is passed instead of writing every single lan port. However, this list includes partly SFP ports which are unrelated to PoE. This commits adds the option to add a third parameter to manually exclide interfaces, usually the last two. Signed-off-by: Paul Spooren <mail@aparcar.org> [Replace glob by regex to be more specific about matching characters] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* kernel: Activate CONFIG_GPIOLIB in generic configurationHauke Mehrtens2022-08-104-4/+0
| | | | | | | | All targets expect the malta target already activate the CONFIG_GPIOLIB option. Move it to generic kernel configuration and also activate it for malta. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* realtek: add support for Panasonic Switch-M48eG PN28480KINAGAKI Hiroshi2022-08-062-0/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Panasonic Switch-M48eG PN28480K is a 48 + 4 port gigabit switch, based on RTL8393M. Specification: - SoC : Realtek RTL8393M - RAM : DDR3 128 MiB (Winbond W631GG8KB-15) - Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G) - Ethernet : 10/100/1000 Mbps x48 + 2 - port 1-40 : TP, RTL8218B x5 - port 41-48 : RTL8218FB - port 41-44: TP - port 45-48: TP/SFP (Combo) - LEDs/Keys : 7x / 1x - UART : RS-232 port on the front panel (connector: RJ-45) - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45) - 9600n8 - Power : 100-240 VAC, 50/60 Hz, 0.5 A - Plug : IEC 60320-C13 - Stock OS : VxWorks based Flash instruction using initramfs image: 1. Prepare the TFTP server with the IP address 192.168.1.111 2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to the TFTP directory 3. Download the official upgrading firmware (ex: pn28480k_v30000.rom) and place it to the TFTP directory 4. Boot M48eG and interrupt the U-Boot with Ctrl + C keys 5. Execute the following commands and boot with the OpenWrt initramfs image rtk network on tftpboot 0x81000000 bootm 6. Backup mtdblock files to the computer by scp or anything and reboot 7. Interrupt the U-Boot and execute the following commands to re-create filesystem in the flash ffsmount c:/ ffsfmt c:/ this step takes a long time, about ~ 4 mins 8. Execute the following commands to put the official images to the filesystem updatert <official image> example: updatert pn28480k_v30000.rom this step takes about ~ 40 secs 9. Set the environment variables of the U-Boot by the following commands setenv loadaddr 0xb4e00000 setenv bootcmd 'sleep 10; bootm;' saveenv 'sleep 10;' is required as dummy to execute 'bootm' command correctly 10: Download the OpenWrt initramfs image and boot with it tftpboot 0x81000000 0101A8C0.img bootm 11: On the initramfs image, download the sysupgrade image and perform sysupgrade with it sysupgrade <imagename> 12: Wait ~ 120 seconds to complete flashing Known Issues: - 4x SFP ports are provided as combo ports by the RTL8218FB chip, but the phy driver has no support for it. Currently, only TP ports work by the RTL8218B support. Note: - "Switch-M48eG" is a model name, and "PN28480K" is a model number. Switch-M48eG has an another (old) model number ("PN28480"), it's not a Realtek based hardware. - Switch-M48eG has a "POWER" LED (Green), but it's not connected to any GPIO pin. - U-Boot checks the runtime images in the flash when booting and fails to execute "bootcmd" variable if the images are not existing. - A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock firmware and it includes the stock images, configuration files and checksum files. It's unknown format, can't be managed on the OpenWrt. To get the enough space for OpenWrt, move the filesystem to the head of "fs_reserved" partition by execution of "ffsfmt" and "updatert". - A GPIO pin on PCA9539 is used for resetting external RTL8218B phys and RTL8218FB phy. This should be specified as "reset-gpios" property in MDIO node, but the current configuration of RTL8218B phy in the driver seems to be incomplete and RTL8218FB won't be configured on RTL8218D support. So, ethernet ports on these phys will be broken after hard-resetting. At the moment, configure this pin as gpio-hog to avoid breaking by resetting. - This model has 2x Microchip TCN75A thermal sensors. Linux Kernel supports TCN75 chip on lm75 driver, but no support for TCN75'A' variant. At the moment, use TCN75 support for the chips instead. Back to the stock firmware: 1. Delete "loadaddr" variable and set "bootcmd" to the original value on U-Boot: setenv loadaddr setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;' on OpenWrt: fw_setenv loadaddr fw_setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;' 2. Perform reset or reboot on U-Boot: reset on OpenWrt: reboot Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: enable pca953x GPIO driver for rtl839x subtargetINAGAKI Hiroshi2022-08-061-0/+3
| | | | | | | | | The system status LED on Panasonic Switch-M48eG PN28480K is connected to a PCA9539PW. To use the LED as a status LED of OpenWrt while booting, enable the pca953x driver and built-in to the kernel. Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: add support for Panasonic Switch-M24eG PN28240KINAGAKI Hiroshi2022-08-062-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on RTL8382M. Specification: - SoC : Realtek RTL8382M - RAM : DDR3 128 MiB (Winbond W631GG8KB-15) - Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G) - Ethernet : 10/100/1000 Mbps x24 + 2 - port 1-8 : TP, RTL8218B - port 9-16 : TP, RTL8218B (SoC) - port 17-24 : RTL8218FB - port 17-22: TP - port 23-24: TP/SFP (Combo) - LEDs/Keys : 7x / 1x - UART : RS-232 port on the front panel (connector: RJ-45) - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45) - 9600n8 - Power : 100-240 VAC, 50/60 Hz, 0.5 A - Plug : IEC 60320-C13 - Stock OS : VxWorks based Flash instruction using initramfs image: 1. Prepare the TFTP server with the IP address 192.168.1.111 2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to the TFTP directory 3. Download the official upgrading firmware (ex: pn28240k_v30000.rom) and place it to the TFTP directory 4. Boot M24eG and interrupt the U-Boot with Ctrl + C keys 5. Execute the following commands and boot with the OpenWrt initramfs image rtk network on tftpboot 0x81000000 bootm 6. Backup mtdblock files to the computer by scp or anything and reboot 7. Interrupt the U-Boot and execute the following commands to re-create filesystem in the flash ffsmount c:/ ffsfmt c:/ this step takes a long time, about ~ 4 mins 8. Execute the following commands to put the official images to the filesystem updatert <official image> example: updatert pn28240k_v30000.rom this step takes about ~ 40 secs 9. Set the environment variables of the U-Boot by the following commands setenv loadaddr 0xb4e00000 setenv bootcmd bootm saveenv 10: Download the OpenWrt initramfs image and boot with it tftpboot 0x81000000 0101A8C0.img bootm 11: On the initramfs image, download the sysupgrade image and perform sysupgrade with it sysupgrade <imagename> 12: Wait ~ 120 seconds to complete flashing Known Issues: - 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the phy driver has no support for it. Currently, only TP ports work by the RTL8218D support. Note: - "Switch-M24eG" is a model name, and "PN28240K" is a model number. Switch-M24eG has an another (old) model number ("PN28240"), it's not a Realtek based hardware. - Switch-M24eG has a "POWER" LED (Green), but it's not connected to any GPIO pin. - U-Boot checks the runtime images in the flash when booting and fails to execute "bootcmd" variable if the images are not existing. - A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock firmware and it includes the stock images, configuration files and checksum files. It's unknown format, can't be managed on the OpenWrt. To get the enough space for OpenWrt, move the filesystem to the head of "fs_reserved" partition by execution of "ffsfmt" and "updatert". - A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and RTL8218FB phy. This should be specified as "reset-gpios" property in MDIO node, but the current configuration of RTL8218B phy in the phy driver seems to be incomplete and RTL8218FB won't be configured on RTL8218D support. So, ethernet ports on these phys will be broken after hard-resetting. At the moment, configure this pin as gpio-hog to avoid breaking by resetting. Back to the stock firmware: 1. Delete "loadaddr" variable and set "bootcmd" to the original value on U-Boot: setenv loadaddr setenv bootcmd 'bootm 0x81000000' on OpenWrt: fw_setenv loadaddr fw_setenv bootcmd 'bootm 0x81000000' 2. Perform reset or reboot on U-Boot: reset on OpenWrt: reboot Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: add support for Panasonic Switch-M16eG PN28160KINAGAKI Hiroshi2022-08-063-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Panasonic Switch-M16eG PN28160K is a 16 + 2 port gigabit switch, based on RTL8382M. Specification: - SoC : Realtek RTL8382M - RAM : DDR3 128 MiB (Winbond W631GG8KB-15) - Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G) - Ethernet : 10/100/1000 Mbps x16 + 2 - port 1-8 : TP, RTL8218B (SoC) - port 9-16 : RTL8218FB - port 9-14: TP - port 15-16: TP/SFP (Combo) - LEDs/Keys : 7x / 1x - UART : RS-232 port on the front panel (connector: RJ-45) - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45) - 9600n8 - Power : 100-240 VAC, 50/60 Hz, 0.5 A - Plug : IEC 60320-C13 - Stock OS : VxWorks based Flash instruction using initramfs image: 1. Prepare the TFTP server with the IP address 192.168.1.111 2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to the TFTP directory 3. Download the official upgrading firmware (ex: pn28160k_v30003.rom) and place it to the TFTP directory 4. Boot M16eG and interrupt the U-Boot with Ctrl + C keys 5. Execute the following commands and boot with the OpenWrt initramfs image rtk network on tftpboot 0x81000000 bootm 6. Backup mtdblock files to the computer by scp or anything and reboot 7. Interrupt the U-Boot and execute the following commands to re-create filesystem in the flash ffsmount c:/ ffsfmt c:/ this step takes a long time, about ~ 4 mins 8. Execute the following commands to put the official images to the filesystem updatert <official image> example: updatert pn28160k_v30003.rom this step takes about ~ 40 secs 9. Set the environment variables of the U-Boot by the following commands setenv loadaddr 0xb4e00000 setenv bootcmd bootm saveenv 10: Download the OpenWrt initramfs image and boot with it tftpboot 0x81000000 0101A8C0.img bootm 11: On the initramfs image, download the sysupgrade image and perform sysupgrade with it sysupgrade <imagename> 12: Wait ~ 120 seconds to complete flashing Known Issues: - 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the phy driver has no support for it. Currently, only TP ports work by the RTL8218D support. Note: - "Switch-M16eG" is a model name, and "PN28160K" is a model number. Switch-M16eG has an another (old) model number ("PN28160"), it's not a Realtek based hardware. - Switch-M16eG has a "POWER" LED (Green), but it's not connected to any GPIO pin. - U-Boot checks the runtime images in the flash when booting and fails to execute "bootcmd" variable if the images are not existing. - A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock firmware and it includes the stock images, configuration files and checksum files. It's unknown format, can't be managed on the OpenWrt. To get the enough space for OpenWrt, move the filesystem to the head of "fs_reserved" partition by execution of "ffsfmt" and "updatert". - A GPIO pin on PCA9539 is used for resetting external RTL8218FB phy. This should be specified as "reset-gpios" property in MDIO node, but RTL8218FB won't be configured on RTL8218D support in the phy driver. So, ethernet ports on the phy will be broken after hard-resetting. At the moment, configure this pin as gpio-hog to avoid breaking by resetting. Back to the stock firmware: 1. Delete "loadaddr" variable and set "bootcmd" to the original value on U-Boot: setenv loadaddr setenv bootcmd 'bootm 0x81000000' on OpenWrt: fw_setenv loadaddr fw_setenv bootcmd 'bootm 0x81000000' 2. Perform reset or reboot on U-Boot: reset on OpenWrt: reboot Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: Fix typo in Kconfig promptOlliver Schinagl2022-08-051-1/+1
| | | | | | | | | As the symbol RTL930x shows, the bool enables the RTL930x platform, not the RTL839x one. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> (slightly changed commit subject) Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* Revert "realtek: remove support for HPE 1920 series"Daniel Golle2022-07-2810-3/+540
| | | | | | This reverts commit a63aeaecf1f3387df020854c9b22a365207399ce. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: remove support for HPE 1920 seriesSander Vanheule2022-07-2810-540/+3
| | | | | | | | | Support for HPE 1920 images depends on two non-existent tools (mkh3cimg and mkh3cvfs) from the in the firmware-utils package. Revert commit f2f09bc00280 ("realtek: add support for HPE 1920 series") until support for these tools is merged and made available in OpenWrt. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add support for HPE 1920 seriesJan Hoffmann2022-07-2810-3/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware information: --------------------- - HPE 1920-8G: - RTL8380 SoC - 8 Gigabit RJ45 ports (built-in RTL8218B) - 2 SFP ports (built-in SerDes) - HPE 1920-16G / HPE 1920-24G (same board): - RTL8382 SoC - 16/24 Gigabit RJ45 ports (built-in RTL8218B, 1/2 external RTL8218D) - 4 SFP ports (external RTL8214FC) - Common: - RJ45 RS232 port on front panel - 32 MiB NOR Flash - 128 MiB DDR3 DRAM - PT7A7514 watchdog Booting initramfs image: ------------------------ - Prepare a FTP or TFTP server serving the OpenWrt initramfs image and connect the server to a switch port. - Connect to the console port of the device and enter the extended boot menu by typing Ctrl+B when prompted. - Choose the menu option "<3> Enter Ethernet SubMenu". - Set network parameters via the option "<5> Modify Ethernet Parameter". Enter the FTP/TFTP filename as "Load File Name" ("Target File Name" can be left blank, it is not required for booting from RAM). Note that the configuration is saved on flash, so it only needs to be done once. - Select "<1> Download Application Program To SDRAM And Run". Initial installation: --------------------- - Boot an initramfs image as described above, then use sysupgrade to install OpenWrt permanently. After initial installation, the bootloader needs to be configured to load the correct image file - Enter the extended boot menu again and choose "<4> File Control", then select "<2> Set Application File type". - Enter the number of the file "openwrt-kernel.bin" (should be 1), and use the option "<1> +Main" to select it as boot image. - Choose "<0> Exit To Main Menu" and then "<1> Boot System". NOTE: The bootloader on these devices can only boot from the VFS filesystem which normally spans most of the flash. With OpenWrt, only the first part of the firmware partition contains a valid filesystem, the rest is used for rootfs. As the bootloader does not know about this, you must not do any file operations in the bootloader, as this may corrupt the OpenWrt installation (selecting the boot image is an exception, as it only stores a flag in the bootloader data, but doesn't write to the filesystem). Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: clean up rtl838x MDIO busy wait loopJan Hoffmann2022-07-281-15/+22
| | | | | | | | | | | | | Don't use udelay to allow other kernel tasks to execute if the kernel has been built without preemption. Also determine the timeout based on jiffies instead of loop iterations. This is especially important on devices containing a watchdog with a short timeout. Without this change, the watchdog is not serviced during PHY patching which can take multiple seconds. Tested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: add SFP support for RTL8214FC PHYJan Hoffmann2022-07-281-1/+25
| | | | | | | | | | Probe the SFP module during PHY initialization and implement insertion/removal handlers to automatically configure the media type of the respective port. Suggested-by: Birger Koblitz <git@birger-koblitz.de> Tested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: rtl83xx-phy: decouple RTL8214FC media change and power configJan Hoffmann2022-07-281-52/+70
| | | | | | | | | | | | | Move RTL8214FC power configuration to newly created suspend and resume methods. A media change now only results in power configuration if the PHY is not suspended, to avoid powering up a port when the interface is currently not up. While at it, remove the rtl8380 prefix from function names, as this is actually not SoC-specific. Tested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: rtl83xx-phy: fix RTL8214FC media changeJan Hoffmann2022-07-281-16/+16
| | | | | | | | Toggle power on the individual PHY instead of the package. Otherwise a media change always toggles power on the first port, and not the one that is being configured. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: make DGS-1210 u-boot-env partition writeableMarkus Stockhausen2022-07-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | We are close to provide enduser friendly OpenWrt images for DGS-1210 switches that do not need serial console. Nevertheless a small bit is missing. We cannot switch back to the vendor partition or initiate a download of a vendor firmware image. To issue this from inside OpenWrt we need write access to U-Boot environment. Case 1: Switch back to secondary (vendor) image > fw_setenv bootcmd run addargs\; bootm 0xb4e80000 > fw_setenv image /dev/mtdblock7 > reboot Case 2: Issue D-Link Network Assistant based download on next reboot. This is a combination of some vendor specific protocol (DDP) and a TFTP download afterwards. > fw_setenv bootstop on > reboot Allow these commands by opening up u-boot-env for write access. Tested on DGS-1210-20. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: clear spurious GPIO interruptsSander Vanheule2022-07-211-0/+30
| | | | | | | | | | | | | | The interrupt controller in the internal GPIO peripheral will sometimes generate spurious interrupts. If these are not properly acknowledged, the system will be held busy until reboot. These spurious interrupts are identified by the fact that there is no system IRQ number associated, since the interrupt line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have also displayed this behaviour. Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> # DGS-1210-52 Reported-by: Birger Koblitz <mail@birger-koblitz.de> # Netgear GS724TP v2 Reported-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-16G Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: correct egress frame port verificationSander Vanheule2022-07-172-39/+36
| | | | | | | | | | | | | | | | | | | | Destination switch ports for outgoing frame can range from 0 to CPU_PORT-1. Refactor the code to only generate egress frame CPU headers when a valid destination port number is available, and make the code a bit more consistent between different switch generations. Change the dest_port argument's type to 'unsigned int', since only positive values are valid. This fixes the issue where egress frames on switch port 0 did not receive a VLAN tag, because they are sent out without a CPU header. Also fixes a potential issue with invalid (negative) egress port numbers on RTL93xx switches. Reported-by: Arınç ÜNAL <arinc.unal@xeront.com> Suggested-by: Birger Koblitz <mail@birger-koblitz.de> Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: correct egress frame priority assignmentSander Vanheule2022-07-171-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | Priority values passed to the egress (TX) frame header initialiser are invalid when smaller than 0, and should not be assigned to the frame. Queue assignment is then left to the switch core logic. Current code for RTL83xx forces the passed priority value to be positive, by always masking it to the lower bits, resulting in the priority always being set and enabled. RTL93xx code doesn't even check the value and unconditionally assigns the (32 bit) value to the (5 bit) QID field without masking. Fix priority assignment by only setting the AS_QID/AS_PRI flag when a valid value is passed, and properly mask the value to not overflow the QID/PRI field. For RTL839x, also assign the priority to the right part of the frame header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36 and 37-39. The means they should be assigned to the third 16 bit value, containing bits 32-47. Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix egress L2 learning on rtl839xSander Vanheule2022-07-171-1/+1
| | | | | | | | | | | | The flag to enable L2 address learning on egress frames is in CPU header bit 40, with bit 0 being the leftmost bit of the header. This corresponds to BIT(7) in the third 16-bit value of the header. Correctly set L2LEARNING by fixing the off-by-one error. Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage") Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix egress port mask on rtl839xSander Vanheule2022-07-171-1/+1
| | | | | | | | | | | | The flag to enable the outgoing port mask is in CPU header bit 43, with bit 0 being the leftmost bit of the header. This corresponds to BIT(4) in the third 16-bit value of the header. Correctly set AS_DPM by fixing the off-by-one error. Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage") Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: remove hardcoded sys-led configurationsSander Vanheule2022-07-101-40/+0
| | | | | | | | | | | | setup.c unconditionally sets the sys-led mode (blinking rate) to a permanent high output. This may cause issues when a board expects this pin to toggle periodically, e.g. when hooked up to an external watchdog. If the sys-led peripheral is used to control an LED, the mux should be configured to use the pin as GPIO0, allowing for better control as a GPIO LED. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add mux pinctrl for rtl931xSander Vanheule2022-07-101-0/+19
| | | | | | | | | | Add a pinctrl-single node to manage the sys-led mux and JTAG mux. This allows using the associated pins as GPIOs: - sys-led: GPIO0 - JTAG: GPIO6, GPIO7, others unknown (TDO, TDI, TMS, TCK /TRST) Suggested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add system LED for ZyXEL XGS1250-12Sander Vanheule2022-07-101-0/+21
| | | | | | | | The devicetree for the ZyXEL XGS1250-12 was missing the description of the front panel LED labeled "PWR SYS". Let's add it so it can be controlled by the user. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add sys-led disable pinctrl for rtl930xSander Vanheule2022-07-101-0/+15
| | | | | | | | | Like for RTL838x devices, add a pinctrl-single node to manage the sys-led/gpio0 mux, and allow using the pin as GPIO. Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add missing gpio0 pinctrl propertiesSander Vanheule2022-07-103-0/+9
| | | | | | | | | | | Not all devices using the gpio0/sys-led pin as a GPIO, configure the pinmux. Add the necessary pinctrl properties to these devices to ensure the pin is set up for use as GPIO. Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Bjørn Mork <bjorn@mork.no>
* realtek: build sane factory images for DGS-1210 modelsMarkus Stockhausen2022-07-082-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | During upload of firmware images the WebUI and CLI patch process extracts a version information from the uploaded file and stores it onto the jffs2 partition. To be precise it is written into the flash.txt or flash2.txt files depending on the selected target image. This data is not used anywhere else. The current OpenWrt factory image misses this label. Therefore version information shows only garbage. Fix this. Before: DGS-1210-20> show firmware information IMAGE ONE: Version : xfo/QE~WQD"A\Scxq... Size : 5505185 Bytes After: DGS-1210-20> show firmware information IMAGE ONE: Version : OpenWrt Size : 5505200 Bytes Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: build factory images for all DGS-1210 modelsMarkus Stockhausen2022-07-081-7/+7
| | | | | | | | | Currently we build factory images only for DGS-1210-28 model. Relax that constraint and take care about all models. Tested on DGS-1210-20 and should work on other models too because of common flash layout. Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: rename u-boot-env2 to board-nameLuiz Angelo Daros de Luca2022-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | Some realtek boards have two u-boot-env partitions. However, in the DGS-1210 series, the mtdblock2 partition is not a valid u-boot env and simply contains the board/device name, followed by nulls. 00000000 44 47 53 2d 31 32 31 30 2d 32 38 2d 46 31 00 00 |DGS-1210-28-F1..| 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| * 00040000 00000000 44 47 53 2d 31 32 31 30 2d 35 32 2d 46 31 00 00 |DGS-1210-52-F1..| 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| * 00040000 The misleading u-boot-env2 name also confuses uboot-envtools. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
* realtek: build DGS-1210 images with CAMEO tagMarkus Stockhausen2022-07-052-0/+5
| | | | | | | | From now on we will insert CAMEO tags into sysupgrade images for DGS-1210 devices. This will make the "OS:...FAILED" and "FS:...FAILED" messages go away. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: EnGenius EWS2910P: declare and hog the poe-enable GPIOAlexandru Gagniuc2022-07-021-0/+7
| | | | | | | | | | | | GPIO 1 on the RTL8231 is used to force the PoE MCU to disable power outputs. It is not used by any driver, but if accidentally set low, PoE outputs are disabled. This situation is hard to debug, and requires knowledge of the Broadcom PoE protocol used by the MCU. To prevent this situation, hog it as an output high. This is consistent with the ZyXel GS1900 series handles it. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 11:04:44 +0000