| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | mediatek: sync MT7986 device trees with upstream | Daniel Golle | 2023-06-09 | 1 | -1/+1 |
| * | mediatek: add driver for built-in 2.5G Ethernet PHY | Daniel Golle | 2023-05-24 | 1 | -0/+262 |
| * | mediatek: update pending SoC Ethernet PHY driver | Daniel Golle | 2023-05-24 | 1 | -0/+1263 |
| * | mediatek: add mt7988 pinctrl driver support | Sam Shih | 2023-05-24 | 1 | -0/+1281 |
| * | mediatek: add mt7988 clock drivers support | Sam Shih | 2023-05-24 | 4 | -0/+1333 |
| * | mediatek: sync pinctrl-mt7981 and pinctrl-mt7986 drivers | Daniel Golle | 2023-04-13 | 2 | -25/+150 |
| * | mediatek: backport pinctrl driver for MT7981 SoC | Daniel Golle | 2023-03-27 | 1 | -0/+993 |
| * | mediatek: backport clk driver for MT7981 SoC | Daniel Golle | 2023-03-27 | 4 | -0/+926 |
| * | mediatek: filogic: consolidate adc '32k' clock | Daniel Golle | 2022-10-20 | 1 | -1/+1 |
| * | mediatek: add mt7986 soc support to the target | Sam Shih | 2022-08-28 | 5 | -0/+1731 |
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index : openwrt/upstream | |
| upstream openwrt | James |
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