openwrt/upstream - upstream openwrt

diff options

Diffstat (limited to 'tools')

-rw-r--r--

294

2 files changed, 295 insertions, 0 deletions

/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ // [[CITE]] ABC // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification // http://www.eecs.berkeley.edu/~alanmi/abc/ // [[CITE]] Berkeley Logic Interchange Format (BLIF) // University of California. Berkeley. July 28, 1992 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf // [[CITE]] Kahn's Topological sorting algorithm // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting #define ABC_COMMAND_LIB "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}" #define ABC_COMMAND_CTR "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" #define ABC_COMMAND_LUT "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v" #define ABC_COMMAND_DFL "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" #define ABC_FAST_COMMAND_LIB "retime -v {D}; map -v {D}" #define ABC_FAST_COMMAND_CTR "retime -v {D}; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" #define ABC_FAST_COMMAND_LUT "retime -v; if -v" #define ABC_FAST_COMMAND_DFL "retime -v; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" #include <unistd.h> #include <stdlib.h> #include <stdio.h> #include <string.h> #include <dirent.h> #include <cerrno> #include <sstream> #include <climits> #include "blifparse.h" enum class gate_type_t { G_NONE, G_FF, G_NOT, G_AND, G_NAND, G_OR, G_NOR, G_XOR, G_XNOR, G_MUX, G_AOI3, G_OAI3, G_AOI4, G_OAI4 }; #define G(_name) gate_type_t::G_ ## _name struct gate_t { int id; gate_type_t type; int in1, in2, in3, in4; bool is_port; RTLIL::SigBit bit; }; static int map_autoidx; static SigMap assign_map; static RTLIL::Module *module; static std::vector<gate_t> signal_list; static std::map<RTLIL::SigBit, int> signal_map; static bool clk_polarity; static RTLIL::SigSpec clk_sig; static int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1) { assign_map.apply(bit); if (signal_map.count(bit) == 0) { gate_t gate; gate.id = signal_list.size(); gate.type = G(NONE); gate.in1 = -1; gate.in2 = -1; gate.in3 = -1; gate.in4 = -1; gate.is_port = false; gate.bit = bit; signal_list.push_back(gate); signal_map[bit] = gate.id; } gate_t &gate = signal_list[signal_map[bit]]; if (gate_type != G(NONE)) gate.type = gate_type; if (in1 >= 0) gate.in1 = in1; if (in2 >= 0) gate.in2 = in2; if (in3 >= 0) gate.in3 = in3; if (in4 >= 0) gate.in4 = in4; return gate.id; } static void mark_port(RTLIL::SigSpec sig) { for (auto &bit : assign_map(sig)) if (bit.wire != NULL && signal_map.count(bit) > 0) signal_list[signal_map[bit]].is_port = true; } static void extract_cell(RTLIL::Cell *cell, bool keepff) { if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") { if (clk_polarity != (cell->type == "$_DFF_P_")) return; if (clk_sig != assign_map(cell->getPort("\\C"))) return; RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_q = cell->getPort("\\Q"); if (keepff) for (auto &c : sig_q.chunks()) if (c.wire != NULL) c.wire->attributes["\\keep"] = 1; assign_map.apply(sig_d); assign_map.apply(sig_q); map_signal(sig_q, G(FF), map_signal(sig_d)); module->remove(cell); return; } if (cell->type == "$_NOT_") { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_y); map_signal(sig_y, G(NOT), map_signal(sig_a)); module->remove(cell); return; } if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); assign_map.apply(sig_y); int mapped_a = map_signal(sig_a); int mapped_b = map_signal(sig_b); if (cell->type == "$_AND_") map_signal(sig_y, G(AND), mapped_a, mapped_b); else if (cell->type == "$_NAND_") map_signal(sig_y, G(NAND), mapped_a, mapped_b); else if (cell->type == "$_OR_") map_signal(sig_y, G(OR), mapped_a, mapped_b); else if (cell->type == "$_NOR_") map_signal(sig_y, G(NOR), mapped_a, mapped_b); else if (cell->type == "$_XOR_") map_signal(sig_y, G(XOR), mapped_a, mapped_b); else if (cell->type == "$_XNOR_") map_signal(sig_y, G(XNOR), mapped_a, mapped_b); else log_abort(); module->remove(cell); return; } if (cell->type == "$_MUX_") { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_s = cell->getPort("\\S"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); assign_map.apply(sig_s); assign_map.apply(sig_y); int mapped_a = map_signal(sig_a); int mapped_b = map_signal(sig_b); int mapped_s = map_signal(sig_s); map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s); module->remove(cell); return; } if (cell->type.in("$_AOI3_", "$_OAI3_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_c = cell->getPort("\\C"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); assign_map.apply(sig_c); assign_map.apply(sig_y); int mapped_a = map_signal(sig_a); int mapped_b = map_signal(sig_b); int mapped_c = map_signal(sig_c); map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c); module->remove(cell); return; } if (cell->type.in("$_AOI4_", "$_OAI4_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_c = cell->getPort("\\C"); RTLIL::SigSpec sig_d = cell->getPort("\\D"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); assign_map.apply(sig_c); assign_map.apply(sig_d); assign_map.apply(sig_y); int mapped_a = map_signal(sig_a); int mapped_b = map_signal(sig_b); int mapped_c = map_signal(sig_c); int mapped_d = map_signal(sig_d); map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d); module->remove(cell); return; } } static std::string remap_name(RTLIL::IdString abc_name) { std::stringstream sstr; sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1); return sstr.str(); } static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts) { if (f == NULL) return; log("Dumping loop state graph to slide %d.\n", ++nr); fprintf(f, "digraph \"slide%d\" {\n", nr); fprintf(f, " label=\"slide%d\";\n", nr); fprintf(f, " rankdir=\"TD\";\n"); std::set<int> nodes; for (auto &e : edges) { nodes.insert(e.first); for (auto n : e.second) nodes.insert(n); } for (auto n : nodes) fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) for (auto n : e.second) fprintf(f, " n%d -> n%d;\n", e.first, n); fprintf(f, "}\n"); } static void handle_loops() { // http://en.wikipedia.org/wiki/Topological_sorting // (Kahn, Arthur B. (1962), "Topological sorting of large networks") std::map<int, std::set<int>> edges; std::vector<int> in_edges_count(signal_list.size()); std::set<int> workpool; FILE *dot_f = NULL; int dot_nr = 0; // uncomment for troubleshooting the loop detection code // dot_f = fopen("test.dot", "w"); for (auto &g : signal_list) { if (g.type == G(NONE) || g.type == G(FF)) { workpool.insert(g.id); } else { if (g.in1 >= 0) { edges[g.in1].insert(g.id); in_edges_count[g.id]++; } if (g.in2 >= 0 && g.in2 != g.in1) { edges[g.in2].insert(g.id); in_edges_count[g.id]++; } if (g.in3 >= 0 && g.in3 != g.in2 && g.in3 != g.in1) { edges[g.in3].insert(g.id); in_edges_count[g.id]++; } if (g.in4 >= 0 && g.in4 != g.in3 && g.in4 != g.in2 && g.in4 != g.in1) { edges[g.in4].insert(g.id); in_edges_count[g.id]++; } } } dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); while (workpool.size() > 0) { int id = *workpool.begin(); workpool.erase(id); // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit)); for (int id2 : edges[id]) { log_assert(in_edges_count[id2] > 0); if (--in_edges_count[id2] == 0) workpool.insert(id2); } edges.erase(id); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); while (workpool.size() == 0) { if (edges.size() == 0) break; int id1 = edges.begin()->first; for (auto &edge_it : edges) { int id2 = edge_it.first; RTLIL::Wire *w1 = signal_list[id1].bit.wire; RTLIL::Wire *w2 = signal_list[id2].bit.wire; if (w1 == NULL) id1 = id2; else if (w2 == NULL) continue; else if (w1->name[0] == '$' && w2->name[0] == '\\') id1 = id2; else if (w1->name[0] == '\\' && w2->name[0] == '$') continue; else if (edges[id1].size() < edges[id2].size()) id1 = id2; else if (edges[id1].size() > edges[id2].size()) continue; else if (w2->name.str() < w1->name.str()) id1 = id2; } if (edges[id1].size() == 0) { edges.erase(id1); continue; } log_assert(signal_list[id1].bit.wire != NULL); std::stringstream sstr; sstr << "$abcloop$" << (autoidx++); RTLIL::Wire *wire = module->addWire(sstr.str()); bool first_line = true; for (int id2 : edges[id1]) { if (first_line) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); else log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); first_line = false; } int id3 = map_signal(RTLIL::SigSpec(wire)); signal_list[id1].is_port = true; signal_list[id3].is_port = true; log_assert(id3 == int(in_edges_count.size())); in_edges_count.push_back(0); workpool.insert(id3); for (int id2 : edges[id1]) { if (signal_list[id2].in1 == id1) signal_list[id2].in1 = id3; if (signal_list[id2].in2 == id1) signal_list[id2].in2 = id3; if (signal_list[id2].in3 == id1) signal_list[id2].in3 = id3; if (signal_list[id2].in4 == id1) signal_list[id2].in4 = id3; } edges[id1].swap(edges[id3]); module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } if (dot_f != NULL) fclose(dot_f); } static std::string add_echos_to_abc_cmd(std::string str) { std::string new_str, token; for (size_t i = 0; i < str.size(); i++) { token += str[i]; if (str[i] == ';') { while (i+1 < str.size() && str[i+1] == ' ') i++; if (!new_str.empty()) new_str += "echo; "; new_str += "echo + " + token + " " + token + " "; token.clear(); } } if (!token.empty()) { if (!new_str.empty()) new_str += "echo; echo + " + token + "; "; new_str += token; } return new_str; } static std::string fold_abc_cmd(std::string str) { std::string token, new_str = " "; int char_counter = 10; for (size_t i = 0; i <= str.size(); i++) { if (i < str.size()) token += str[i]; if (i == str.size() || str[i] == ';') { if (char_counter + token.size() > 75) new_str += "\n ", char_counter = 14; new_str += token, char_counter += token.size(); token.clear(); } } return new_str; } static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, bool fast_mode) { module = current_module; map_autoidx = autoidx++; signal_map.clear(); signal_list.clear(); assign_map.set(module); clk_polarity = true; clk_sig = RTLIL::SigSpec(); char tempdir_name[] = "/tmp/yosys-abc-XXXXXX"; if (!cleanup) tempdir_name[0] = tempdir_name[4] = '_'; char *p = mkdtemp(tempdir_name); log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), tempdir_name); if (p == NULL) log_error("For some reason mkdtemp() failed!\n"); std::string abc_command; if (!script_file.empty()) { if (script_file[0] == '+') { for (size_t i = 1; i < script_file.size(); i++) if (script_file[i] == '\'') abc_command += "'\\''"; else if (script_file[i] == ',') abc_command += " "; else abc_command += script_file[i]; } else abc_command = stringf("source %s", script_file.c_str()); } else if (lut_mode) abc_command = fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; else if (!liberty_file.empty()) abc_command = constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR); else abc_command = fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL; for (size_t pos = abc_command.find("{D}"); pos != std::string::npos; pos = abc_command.find("{D}", pos)) abc_command = abc_command.substr(0, pos) + delay_target + abc_command.substr(pos+3); abc_command = add_echos_to_abc_cmd(abc_command); if (abc_command.size() > 128) { for (size_t i = 0; i+1 < abc_command.size(); i++) if (abc_command[i] == ';' && abc_command[i+1] == ' ') abc_command[i+1] = '\n'; FILE *f = fopen(stringf("%s/abc.script", tempdir_name).c_str(), "wt"); fprintf(f, "%s\n", abc_command.c_str()); fclose(f); abc_command = stringf("source %s/abc.script", tempdir_name); } if (clk_str.empty()) { if (clk_str[0] == '!') { clk_polarity = false; clk_str = clk_str.substr(1); } if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0) clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) { int best_dff_counter = 0; std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters; for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") continue; std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C"))); if (++dff_counters[key] > best_dff_counter) { best_dff_counter = dff_counters[key]; clk_polarity = key.first; clk_sig = key.second; } } } if (dff_mode || !clk_str.empty()) { if (clk_sig.size() == 0) log("No (matching) clock domain found. Not extracting any FF cells.\n"); else log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig)); } if (clk_sig.size() != 0) mark_port(clk_sig); std::vector<RTLIL::Cell*> cells; cells.reserve(module->cells_.size()); for (auto &it : module->cells_) if (design->selected(current_module, it.second)) cells.push_back(it.second); for (auto c : cells) extract_cell(c, keepff); for (auto &wire_it : module->wires_) { if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) mark_port(RTLIL::SigSpec(wire_it.second)); } for (auto &cell_it : module->cells_) for (auto &port_it : cell_it.second->connections()) mark_port(port_it.second); handle_loops(); if (asprintf(&p, "%s/input.blif", tempdir_name) < 0) log_abort(); FILE *f = fopen(p, "wt"); if (f == NULL) log_error("Opening %s for writing failed: %s\n", p, strerror(errno)); free(p); fprintf(f, ".model netlist\n"); int count_input = 0; fprintf(f, ".inputs"); for (auto &si : signal_list) { if (!si.is_port || si.type != G(NONE)) continue; fprintf(f, " n%d", si.id); count_input++; } if (count_input == 0) fprintf(f, " dummy_input\n"); fprintf(f, "\n"); int count_output = 0; fprintf(f, ".outputs"); for (auto &si : signal_list) { if (!si.is_port || si.type == G(NONE)) continue; fprintf(f, " n%d", si.id); count_output++; } fprintf(f, "\n"); for (auto &si : signal_list) fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit)); for (auto &si : signal_list) { if (si.bit.wire == NULL) { fprintf(f, ".names n%d\n", si.id); if (si.bit == RTLIL::State::S1) fprintf(f, "1\n"); } } int count_gates = 0; for (auto &si : signal_list) { if (si.type == G(NOT)) { fprintf(f, ".names n%d n%d\n", si.in1, si.id); fprintf(f, "0 1\n"); } else if (si.type == G(AND)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "11 1\n"); } else if (si.type == G(NAND)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "0- 1\n"); fprintf(f, "-0 1\n"); } else if (si.type == G(OR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "-1 1\n"); fprintf(f, "1- 1\n"); } else if (si.type == G(NOR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "00 1\n"); } else if (si.type == G(XOR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "01 1\n"); fprintf(f, "10 1\n"); } else if (si.type == G(XNOR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "00 1\n"); fprintf(f, "11 1\n"); } else if (si.type == G(MUX)) { fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "1-0 1\n"); fprintf(f, "-11 1\n"); } else if (si.type == G(AOI3)) { fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "-00 1\n"); fprintf(f, "0-0 1\n"); } else if (si.type == G(OAI3)) { fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "00- 1\n"); fprintf(f, "--0 1\n"); } else if (si.type == G(AOI4)) { fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); fprintf(f, "-0-0 1\n"); fprintf(f, "-00- 1\n"); fprintf(f, "0--0 1\n"); fprintf(f, "0-0- 1\n"); } else if (si.type == G(OAI4)) { fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); fprintf(f, "00-- 1\n"); fprintf(f, "--00 1\n"); } else if (si.type == G(FF)) { fprintf(f, ".latch n%d n%d\n", si.in1, si.id); } else if (si.type != G(NONE)) log_abort(); if (si.type != G(NONE)) count_gates++; } fprintf(f, ".end\n"); fclose(f); log("Extracted %d gates and %zd wires to a netlist network with %d inputs and %d outputs.\n", count_gates, signal_list.size(), count_input, count_output); log_push(); if (count_output > 0) { log_header("Executing ABC.\n"); if (asprintf(&p, "%s/stdcells.genlib", tempdir_name) < 0) log_abort(); f = fopen(p, "wt"); if (f == NULL) log_error("Opening %s for writing failed: %s\n", p, strerror(errno)); fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE NOT 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE NOR 1 Y=!(A+B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE XOR 1 Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n"); fprintf(f, "GATE XNOR 1 Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n"); fprintf(f, "GATE MUX 1 Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n"); fprintf(f, "GATE AOI3 1 Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OAI3 1 Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE AOI4 1 Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OAI4 1 Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n"); fclose(f); free(p); if (lut_mode) { if (asprintf(&p, "%s/lutdefs.txt", tempdir_name) < 0) log_abort(); f = fopen(p, "wt"); if (f == NULL) log_error("Opening %s for writing failed: %s\n", p, strerror(errno)); for (int i = 0; i < lut_mode; i++) fprintf(f, "%d 1.00 1.00\n", i+1); fclose(f); free(p); } std::string buffer; if (!liberty_file.empty()) { buffer += stringf("%s -s -c 'read_blif %s/input.blif; read_lib -w %s; ", exe_file.c_str(), tempdir_name, liberty_file.c_str()); if (!constr_file.empty()) buffer += stringf("read_constr -v %s; ", constr_file.c_str()); buffer += abc_command + "; "; } else if (lut_mode) buffer += stringf("%s -s -c 'read_blif %s/input.blif; read_lut %s/lutdefs.txt; %s; ", exe_file.c_str(), tempdir_name, tempdir_name, abc_command.c_str()); else buffer += stringf("%s -s -c 'read_blif %s/input.blif; read_library %s/stdcells.genlib; %s; ", exe_file.c_str(), tempdir_name, tempdir_name, abc_command.c_str()); buffer += stringf("write_blif %s/output.blif' 2>&1", tempdir_name); log("%s\n", buffer.c_str()); errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand f = popen(buffer.c_str(), "r"); if (f == NULL) log_error("Opening pipe to `%s' for reading failed: %s\n", buffer.c_str(), strerror(errno)); #if 0 char logbuf[1024]; while (fgets(logbuf, 1024, f) != NULL) log("ABC: %s", logbuf); #else bool got_cr = false; int escape_seq_state = 0; std::string linebuf; char logbuf[1024]; while (fgets(logbuf, 1024, f) != NULL) for (char *p = logbuf; *p; p++) { if (escape_seq_state == 0 && *p == '\033') { escape_seq_state = 1; continue; } if (escape_seq_state == 1) { escape_seq_state = *p == '[' ? 2 : 0; continue; } if (escape_seq_state == 2) { if ((*p < '0' || '9' < *p) && *p != ';') escape_seq_state = 0; continue; } escape_seq_state = 0; if (*p == '\r') { got_cr = true; continue; } if (*p == '\n') { log("ABC: %s\n", linebuf.c_str()); got_cr = false, linebuf.clear(); continue; } if (got_cr) got_cr = false, linebuf.clear(); linebuf += *p;


context:
space:
mode: