diff options
Diffstat (limited to 'target')
105 files changed, 3943 insertions, 5439 deletions
diff --git a/target/linux/generic/patches-4.3/142-mtd-spi-nor-include-mtd.h-header-for-struct-mtd_info.patch b/target/linux/generic/patches-4.3/142-mtd-spi-nor-include-mtd.h-header-for-struct-mtd_info.patch index f25c79c281..b0a064fb4e 100644 --- a/target/linux/generic/patches-4.3/142-mtd-spi-nor-include-mtd.h-header-for-struct-mtd_info.patch +++ b/target/linux/generic/patches-4.3/142-mtd-spi-nor-include-mtd.h-header-for-struct-mtd_info.patch @@ -17,8 +17,6 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com> include/linux/mtd/spi-nor.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h -index 7bed974..fac3f6f 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -12,6 +12,7 @@ diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile index a92b287fcf..9d7bb5b6a8 100644 --- a/target/linux/ramips/Makefile +++ b/target/linux/ramips/Makefile @@ -10,10 +10,10 @@ ARCH:=mipsel BOARD:=ramips BOARDNAME:=Ralink RT288x/RT3xxx SUBTARGETS:=rt305x mt7620 mt7621 mt7628 mt7688 rt3883 rt288x -FEATURES:=squashfs gpio ubifs +FEATURES:=squashfs gpio MAINTAINER:=John Crispin <blogic@openwrt.org> -KERNEL_PATCHVER:=3.18 +KERNEL_PATCHVER:=4.3 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index fd2e1008a3..801b075e27 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -77,7 +77,7 @@ reg = <0xc00 0x100>; interrupt-parent = <&gic>; - interrupts = <26>; + interrupts = <0 26 4>; reg-shift = <2>; reg-io-width = <4>; @@ -210,28 +210,27 @@ reg = <0x1E130000 4000>; interrupt-parent = <&gic>; - interrupts = <20>; + interrupts = <0 20 4>; }; xhci@1E1C0000 { - status = "disabled"; + status = "okay"; compatible = "xhci-platform"; reg = <0x1E1C0000 4000>; interrupt-parent = <&gic>; - interrupts = <22>; + interrupts = <0 22 4>; }; - gic: gic@1fbc0000 { - #address-cells = <0>; - #interrupt-cells = <1>; + gic: interrupt-controller@1fbc0000 { + compatible = "mti,gic"; + reg = <0x1fbc0000 0x80>; + interrupt-controller; - compatible = "ralink,mt7621-gic"; - reg = < 0x1fbc0000 0x80 /* gic */ - 0x1fbf0000 0x8000 /* cpc */ - 0x1fbf8000 0x8000 /* gpmc */ - >; + #interrupt-cells = <3>; + + mti,reserved-cpu-vectors = <7>; }; nand@1e003000 { @@ -274,7 +273,7 @@ reset-names = "fe", "eth"; interrupt-parent = <&gic>; - interrupts = <3>; + interrupts = <0 3 4>; mdio-bus { #address-cells = <1>; @@ -291,7 +290,7 @@ compatible = "ralink,mt7620a-gsw"; reg = <0x1e110000 8000>; interrupt-parent = <&gic>; - interrupts = <23>; + interrupts = <0 23 4>; }; pcie@1e140000 { @@ -313,6 +312,11 @@ 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ >; + interrupt-parent = <&gic>; + interrupts = <0 4 4 + 0 24 4 + 0 25 4>; + status = "okay"; pcie0 { diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c index 55d5729f43..e564dd81e5 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c @@ -611,7 +611,7 @@ static void esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 29, 0x598b); /* select local register */ rt305x_mii_write(esw, 0, 31, 0x8000); - } else if (ralink_soc == MT762X_SOC_MT7628AN) { + } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { int i; // u32 phy_val; u32 val; @@ -1042,7 +1042,7 @@ esw_get_port_tr_badgood(struct switch_dev *dev, int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; u32 reg; - if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN)) ++ if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688)) return -EINVAL; if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c index 0f3009cc73..5bc9b58336 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.c @@ -575,13 +575,15 @@ static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev, txd.txd4 |= TX_DMA_CHKSUM; /* VLAN header offload */ - if (vlan_tx_tag_present(skb)) { + if (skb_vlan_tag_present(skb)) { + u16 tag = skb_vlan_tag_get(skb); + if (IS_ENABLED(CONFIG_SOC_MT7621)) - txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb); + txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag; else txd.txd4 |= TX_DMA_INS_VLAN | - ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) | - (vlan_tx_tag_get(skb) & 0xF); + ((tag >> VLAN_PRIO_SHIFT) << 4) | + (tag & 0xF); } /* TSO: fill MSS info in tcp checksum field */ @@ -711,8 +713,7 @@ static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) { if ((priv->flags & FE_FLAG_PADDING_64B) && !(priv->flags & FE_FLAG_PADDING_BUG)) return ret; - - if (vlan_tx_tag_present(skb)) + if (skb_vlan_tag_present(skb)) len = ETH_ZLEN; else if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) len = VLAN_ETH_ZLEN; @@ -999,6 +1000,8 @@ static int fe_poll(struct napi_struct *napi, int budget) napi_complete(napi); fe_int_enable(tx_intr | rx_intr); + } else { + rx_done = budget; } poll_again: diff --git a/target/linux/ramips/mt7620/config-3.18 b/target/linux/ramips/mt7620/config-4.3 index 5dbfaa262f..bae003a37c 100644 --- a/target/linux/ramips/mt7620/config-3.18 +++ b/target/linux/ramips/mt7620/config-4.3 @@ -1,19 +1,21 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_AT803X_PHY=y -CONFIG_ICPLUS_PHY=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CEVT_R4K=y +CONFIG_CEVT_SYSTICK_QUIRK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKEVT_RT3352=y CONFIG_CLKSRC_MMIO=y @@ -36,22 +38,24 @@ CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_PINCTRL=y CONFIG_DMA_NONCOHERENT=y # CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_MT7628AN_EVAL is not set CONFIG_DTB_RT_NONE=y CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -63,6 +67,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -84,6 +89,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -93,21 +99,28 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y +CONFIG_ICPLUS_PHY=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y # CONFIG_MT7621_WDT is not set # CONFIG_MTD_CFI_INTELEXT is not set @@ -144,36 +157,37 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHY_RALINK_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_USBPHY=y CONFIG_RALINK_WDT=y # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set # CONFIG_SOC_RT288X is not set # CONFIG_SOC_RT305X is not set # CONFIG_SOC_RT3883 is not set -CONFIG_SND_MT76XX_SOC_MT7620=y -# CONFIG_SND_MT76XX_SOC_MT7628 is not set CONFIG_SPI=y CONFIG_SPI_MASTER=y # CONFIG_SPI_MT7621 is not set CONFIG_SPI_RT2880=y +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y @@ -182,7 +196,6 @@ CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_USB_PHY=y CONFIG_USB_SUPPORT=y CONFIG_USE_OF=y CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/mt7621/config-3.18 b/target/linux/ramips/mt7621/config-4.3 index 8861795854..3657460f9b 100644 --- a/target/linux/ramips/mt7621/config-3.18 +++ b/target/linux/ramips/mt7621/config-4.3 @@ -1,17 +1,17 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_BOARD_SCACHE=y -CONFIG_BOUNCE=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_CEVT_GIC is not set CONFIG_CEVT_R4K=y # CONFIG_CEVT_SYSTICK_QUIRK is not set CONFIG_CLKDEV_LOOKUP=y @@ -50,11 +50,12 @@ CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -66,6 +67,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -87,6 +89,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -96,35 +99,39 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HIGHMEM=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_GIC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y CONFIG_MIPS_CM=y CONFIG_MIPS_CMP=y CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_GIC=y CONFIG_MIPS_GIC_IPI=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=6 -CONFIG_MIPS_L1_CACHE_SHIFT_6=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set CONFIG_MIPS_MT=y CONFIG_MIPS_MT_FPAFF=y CONFIG_MIPS_MT_SMP=y +CONFIG_MIPS_NO_APPENDED_DTB=y CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y # CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MTK_MTD_NAND=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MT7621_WDT=y # CONFIG_MTD_CFI_INTELEXT is not set @@ -171,6 +178,7 @@ CONFIG_PCI=y CONFIG_PCI_DISABLE_COMMON_QUIRKS=y CONFIG_PCI_DOMAINS=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y # CONFIG_PHY_RALINK_USB is not set CONFIG_PINCTRL=y @@ -178,11 +186,7 @@ CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y -# CONFIG_POWER_RESET_GPIO_RESTART is not set -# CONFIG_POWER_RESET_LTC2952 is not set -# CONFIG_POWER_RESET_SYSCON is not set CONFIG_POWER_SUPPLY=y -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y # CONFIG_RALINK_WDT is not set CONFIG_RCU_STALL_COMMON=y @@ -190,10 +194,13 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RFS_ACCEL=y CONFIG_RPS=y CONFIG_RTC_CLASS=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set CONFIG_SCHED_SMT=y # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y CONFIG_SLUB_CPU_PARTIAL=y @@ -208,15 +215,17 @@ CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MT7621=y # CONFIG_SPI_RT2880 is not set +CONFIG_SRCU=y CONFIG_STOP_MACHINE=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_SYS_SUPPORTS_MIPS_CMP=y diff --git a/target/linux/ramips/mt7628/config-3.18 b/target/linux/ramips/mt7628/config-4.3 index 9ab31acdc3..35bfc97741 100644 --- a/target/linux/ramips/mt7628/config-3.18 +++ b/target/linux/ramips/mt7628/config-4.3 @@ -1,18 +1,21 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_AT803X_PHY=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CEVT_R4K=y +CONFIG_CEVT_SYSTICK_QUIRK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKEVT_RT3352=y CONFIG_CLKSRC_MMIO=y @@ -35,6 +38,8 @@ CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_PINCTRL=y CONFIG_DMA_NONCOHERENT=y @@ -44,12 +49,13 @@ CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -61,6 +67,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -82,6 +89,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -91,22 +99,28 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_ICPLUS_PHY=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MT7621_WDT=y # CONFIG_MTD_CFI_INTELEXT is not set @@ -141,36 +155,37 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHY_RALINK_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_USBPHY=y # CONFIG_RALINK_WDT is not set # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set # CONFIG_SOC_RT288X is not set # CONFIG_SOC_RT305X is not set # CONFIG_SOC_RT3883 is not set -# CONFIG_SND_MT76XX_SOC_MT7620 is not set -CONFIG_SND_MT76XX_SOC_MT7628=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MT7621=y # CONFIG_SPI_RT2880 is not set +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y @@ -179,7 +194,6 @@ CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_USB_PHY=y CONFIG_USB_SUPPORT=y CONFIG_USE_OF=y CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/mt7688/config-3.18 b/target/linux/ramips/mt7688/config-4.3 index 27eab9a4fe..01abcf10c7 100644 --- a/target/linux/ramips/mt7688/config-3.18 +++ b/target/linux/ramips/mt7688/config-4.3 @@ -1,13 +1,15 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_AT803X_PHY=y @@ -36,6 +38,8 @@ CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_PINCTRL=y CONFIG_DMA_NONCOHERENT=y @@ -45,12 +49,13 @@ CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -62,6 +67,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -83,6 +89,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -92,24 +99,29 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_ICPLUS_PHY=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y -CONFIG_LINKIT_BOOTSTRAP=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y CONFIG_MIPS_FPU_EMULATOR=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MT7621_WDT=y # CONFIG_MTD_CFI_INTELEXT is not set @@ -144,40 +156,42 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHY_RALINK_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_PWM=y -# CONFIG_PWM_FSL_FTM is not set CONFIG_PWM_MEDIATEK=y CONFIG_PWM_SYSFS=y CONFIG_RALINK=y # CONFIG_RALINK_WDT is not set # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set # CONFIG_SOC_RT288X is not set # CONFIG_SOC_RT305X is not set # CONFIG_SOC_RT3883 is not set -# CONFIG_SND_MT76XX_SOC_MT7620 is not set -CONFIG_SND_MT76XX_SOC_MT7628=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MT7621=y # CONFIG_SPI_RT2880 is not set CONFIG_SPI_SPIDEV=y +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y diff --git a/target/linux/ramips/patches-3.18/0001-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.18/0001-MIPS-ralink-add-verbose-pmu-info.patch deleted file mode 100644 index 5bf90c6fee..0000000000 --- a/target/linux/ramips/patches-3.18/0001-MIPS-ralink-add-verbose-pmu-info.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:16:50 +0100 -Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info - -Print the PMU and LDO settings on boot. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -20,6 +20,22 @@ - - #include "common.h" - -+/* analog */ -+#define PMU0_CFG 0x88 -+#define PMU_SW_SET BIT(28) -+#define A_DCDC_EN BIT(24) -+#define A_SSC_PERI BIT(19) -+#define A_SSC_GEN BIT(18) -+#define A_SSC_M 0x3 -+#define A_SSC_S 16 -+#define A_DLY_M 0x7 -+#define A_DLY_S 8 -+#define A_VTUNE_M 0xff -+ -+/* digital */ -+#define PMU1_CFG 0x8C -+#define DIG_SW_SEL BIT(25) -+ - /* does the board have sdram or ddram */ - static int dram_type; - -@@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_inf - u32 n1; - u32 rev; - u32 cfg0; -+ u32 pmu0; -+ u32 pmu1; - - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); -@@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_inf - BUG(); - } - soc_info->mem_base = MT7620_DRAM_BASE; -+ -+ pmu0 = __raw_readl(sysc + PMU0_CFG); -+ pmu1 = __raw_readl(sysc + PMU1_CFG); -+ -+ pr_info("Analog PMU set to %s control\n", -+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); -+ pr_info("Digital PMU set to %s control\n", -+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - } diff --git a/target/linux/ramips/patches-3.18/0002-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch b/target/linux/ramips/patches-3.18/0002-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch deleted file mode 100644 index 237ba00a5a..0000000000 --- a/target/linux/ramips/patches-3.18/0002-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 1751f28d4779df83cc793c9d7ff75485c0ceaa23 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 16 Mar 2014 04:53:02 +0000 -Subject: [PATCH 02/57] MIPS: ralink: add a helper for reading the ECO version - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -105,4 +105,9 @@ - #define MT7620_GPIO_MODE_EPHY BIT(15) - #define MT7620_GPIO_MODE_WDT BIT(22) - -+static inline int mt7620_get_eco(void) -+{ -+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; -+} -+ - #endif diff --git a/target/linux/ramips/patches-3.18/0003-MIPS-ralink-add-rt_sysc_m32-helper.patch b/target/linux/ramips/patches-3.18/0003-MIPS-ralink-add-rt_sysc_m32-helper.patch deleted file mode 100644 index 66126e6889..0000000000 --- a/target/linux/ramips/patches-3.18/0003-MIPS-ralink-add-rt_sysc_m32-helper.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0f0f041cd6a05eb865e391155d3299bb55ff00e3 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 19 May 2013 00:42:23 +0200 -Subject: [PATCH 03/57] MIPS: ralink: add rt_sysc_m32 helper - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/include/asm/mach-ralink/ralink_regs.h | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h -+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h -@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r - return __raw_readl(rt_sysc_membase + reg); - } - -+static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg) -+{ -+ u32 val = rt_sysc_r32(reg) & ~clr; -+ -+ __raw_writel(val | set, rt_sysc_membase + reg); -+} -+ - static inline void rt_memc_w32(u32 val, unsigned reg) - { - __raw_writel(val, rt_memc_membase + reg); diff --git a/target/linux/ramips/patches-3.18/0004-MIPS-ralink-adds-a-bootrom-dumper-module.patch b/target/linux/ramips/patches-3.18/0004-MIPS-ralink-adds-a-bootrom-dumper-module.patch deleted file mode 100644 index 049a876961..0000000000 --- a/target/linux/ramips/patches-3.18/0004-MIPS-ralink-adds-a-bootrom-dumper-module.patch +++ /dev/null @@ -1,74 +0,0 @@ -From af03898c74172ab16d610f3eeaa65f66401eb7db Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Tue, 21 May 2013 15:50:31 +0200 -Subject: [PATCH 04/57] MIPS: ralink: adds a bootrom dumper module - -This patch adds a trivial driver that allows userland to extract the bootrom of -a SoC via debugfs. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/Makefile | 2 ++ - arch/mips/ralink/bootrom.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 50 insertions(+) - create mode 100644 arch/mips/ralink/bootrom.c - ---- a/arch/mips/ralink/Makefile -+++ b/arch/mips/ralink/Makefile -@@ -16,3 +16,5 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o - obj-$(CONFIG_SOC_MT7620) += mt7620.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+ -+obj-$(CONFIG_DEBUG_FS) += bootrom.o ---- /dev/null -+++ b/arch/mips/ralink/bootrom.c -@@ -0,0 +1,48 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org> -+ */ -+ -+#include <linux/debugfs.h> -+#include <linux/seq_file.h> -+ -+#define BOOTROM_OFFSET 0x10118000 -+#define BOOTROM_SIZE 0x8000 -+ -+static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET); -+ -+static int bootrom_show(struct seq_file *s, void *unused) -+{ -+ seq_write(s, membase, BOOTROM_SIZE); -+ -+ return 0; -+} -+ -+static int bootrom_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, bootrom_show, NULL); -+} -+ -+static const struct file_operations bootrom_file_ops = { -+ .open = bootrom_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int bootrom_setup(void) -+{ -+ if (!debugfs_create_file("bootrom", 0444, -+ NULL, NULL, &bootrom_file_ops)) { -+ pr_err("Failed to create bootrom debugfs file\n"); -+ -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+postcore_initcall(bootrom_setup); diff --git a/target/linux/ramips/patches-3.18/0005-MIPS-ralink-add-illegal-access-driver.patch b/target/linux/ramips/patches-3.18/0005-MIPS-ralink-add-illegal-access-driver.patch deleted file mode 100644 index fa9cd21b03..0000000000 --- a/target/linux/ramips/patches-3.18/0005-MIPS-ralink-add-illegal-access-driver.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 60999174904c731e55992a4087999bbd4e5f2051 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Thu, 16 May 2013 23:28:23 +0200 -Subject: [PATCH 05/57] MIPS: ralink: add illegal access driver - -these SoCs have a special irq that fires upon an illegal memmory access. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/Makefile | 2 + - arch/mips/ralink/ill_acc.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 89 insertions(+) - create mode 100644 arch/mips/ralink/ill_acc.c - ---- a/arch/mips/ralink/Makefile -+++ b/arch/mips/ralink/Makefile -@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o - - obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o - -+obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o -+ - obj-$(CONFIG_SOC_RT288X) += rt288x.o - obj-$(CONFIG_SOC_RT305X) += rt305x.o - obj-$(CONFIG_SOC_RT3883) += rt3883.o ---- /dev/null -+++ b/arch/mips/ralink/ill_acc.c -@@ -0,0 +1,87 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org> -+ */ -+ -+#include <linux/interrupt.h> -+#include <linux/of_platform.h> -+#include <linux/of_irq.h> -+ -+#include <asm/mach-ralink/ralink_regs.h> -+ -+#define REG_ILL_ACC_ADDR 0x10 -+#define REG_ILL_ACC_TYPE 0x14 -+ -+#define ILL_INT_STATUS BIT(31) -+#define ILL_ACC_WRITE BIT(30) -+#define ILL_ACC_LEN_M 0xff -+#define ILL_ACC_OFF_M 0xf -+#define ILL_ACC_OFF_S 16 -+#define ILL_ACC_ID_M 0x7 -+#define ILL_ACC_ID_S 8 -+ -+#define DRV_NAME "ill_acc" -+ -+static const char *ill_acc_ids[] = { -+ "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb", -+}; -+ -+static irqreturn_t ill_acc_irq_handler(int irq, void *_priv) -+{ -+ struct device *dev = (struct device *) _priv; -+ u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR); -+ u32 type = rt_memc_r32(REG_ILL_ACC_TYPE); -+ -+ dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n", -+ (type & ILL_ACC_WRITE) ? ("write") : ("read"), -+ ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M], -+ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M, -+ type & ILL_ACC_LEN_M); -+ -+ rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE); -+ -+ return IRQ_HANDLED; -+} -+ -+static int __init ill_acc_of_setup(void) -+{ -+ struct platform_device *pdev; -+ struct device_node *np; -+ int irq; -+ -+ /* somehow this driver breaks on RT5350 */ -+ if (of_machine_is_compatible("ralink,rt5350-soc")) -+ return -EINVAL; -+ -+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc"); -+ if (!np) -+ return -EINVAL; -+ -+ pdev = of_find_device_by_node(np); -+ if (!pdev) { -+ pr_err("%s: failed to lookup pdev\n", np->name); -+ return -EINVAL; -+ } -+ -+ irq = irq_of_parse_and_map(np, 0); -+ if (!irq) { -+ dev_err(&pdev->dev, "failed to get irq\n"); -+ return -EINVAL; -+ } -+ -+ if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) { -+ dev_err(&pdev->dev, "failed to request irq\n"); -+ return -EINVAL; -+ } -+ -+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE); -+ -+ dev_info(&pdev->dev, "irq registered\n"); -+ -+ return 0; -+} -+ -+arch_initcall(ill_acc_of_setup); diff --git a/target/linux/ramips/patches-3.18/0006-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch b/target/linux/ramips/patches-3.18/0006-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch deleted file mode 100644 index 8085e4be68..0000000000 --- a/target/linux/ramips/patches-3.18/0006-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 979ad9f0324ad8fa5eb4a00b57d9feb061aa3200 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 16 Mar 2014 04:38:07 +0000 -Subject: [PATCH 06/57] MIPS: ralink: add missing clk_set_rate() to clk.c - -This function was missing causing allmod to fail. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/clk.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/mips/ralink/clk.c -+++ b/arch/mips/ralink/clk.c -@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c - } - EXPORT_SYMBOL_GPL(clk_get_rate); - -+int clk_set_rate(struct clk *clk, unsigned long rate) -+{ -+ return -1; -+} -+EXPORT_SYMBOL_GPL(clk_set_rate); -+ - void __init plat_time_init(void) - { - struct clk *clk; diff --git a/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch b/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch deleted file mode 100644 index 1d507101f3..0000000000 --- a/target/linux/ramips/patches-3.18/0007-MIPS-ralink-add-support-for-MT7620n.patch +++ /dev/null @@ -1,66 +0,0 @@ -From efc0f99cebcab21dbabcc634b9dbb963bbbbcab8 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:23:36 +0100 -Subject: [PATCH 07/57] MIPS: ralink: add support for MT7620n - -This is the small version of MT7620a. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++----- - arch/mips/ralink/mt7620.c | 19 ++++++++++++------- - 2 files changed, 14 insertions(+), 12 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -25,11 +25,8 @@ - #define SYSC_REG_CPLL_CONFIG0 0x54 - #define SYSC_REG_CPLL_CONFIG1 0x58 - --#define MT7620N_CHIP_NAME0 0x33365452 --#define MT7620N_CHIP_NAME1 0x20203235 -- --#define MT7620A_CHIP_NAME0 0x3637544d --#define MT7620A_CHIP_NAME1 0x20203032 -+#define MT7620_CHIP_NAME0 0x3637544d -+#define MT7620_CHIP_NAME1 0x20203032 - - #define SYSCFG0_XTAL_FREQ_SEL BIT(6) - ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -357,22 +357,27 @@ void prom_soc_init(struct ralink_soc_inf - u32 cfg0; - u32 pmu0; - u32 pmu1; -+ u32 bga; - - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); -+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); -+ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; - -- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) { -- name = "MT7620N"; -- soc_info->compatible = "ralink,mt7620n-soc"; -- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) { -+ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1) -+ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1); -+ -+ if (bga) { - name = "MT7620A"; - soc_info->compatible = "ralink,mt7620a-soc"; - } else { -- panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1); -+ name = "MT7620N"; -+ soc_info->compatible = "ralink,mt7620n-soc"; -+#ifdef CONFIG_PCI -+ panic("mt7620n is only supported for non pci kernels"); -+#endif - } - -- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); -- - snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, - "Ralink %s ver:%u eco:%u", - name, diff --git a/target/linux/ramips/patches-3.18/0008-MIPS-ralink-allow-manual-memory-override.patch b/target/linux/ramips/patches-3.18/0008-MIPS-ralink-allow-manual-memory-override.patch deleted file mode 100644 index 1870d13efc..0000000000 --- a/target/linux/ramips/patches-3.18/0008-MIPS-ralink-allow-manual-memory-override.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 071e97587a291d3a5bbd614a425f46b7f90310aa Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 16 Mar 2014 04:40:48 +0000 -Subject: [PATCH 08/57] MIPS: ralink: allow manual memory override - -RT5350 relies on the bootloader setting up the memc correctly. -On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range -. -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/of.c | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -53,6 +53,17 @@ void __init device_tree_init(void) - unflatten_and_copy_device_tree(); - } - -+static int memory_dtb; -+ -+static int __init early_init_dt_find_memory(unsigned long node, const char *uname, -+ int depth, void *data) -+{ -+ if (depth == 1 && !strcmp(uname, "memory@0")) -+ memory_dtb = 1; -+ -+ return 0; -+} -+ - void __init plat_mem_setup(void) - { - set_io_port_base(KSEG1); -@@ -63,7 +74,10 @@ void __init plat_mem_setup(void) - */ - __dt_setup_arch(__dtb_start); - -- if (soc_info.mem_size) -+ of_scan_flat_dt(early_init_dt_find_memory, NULL); -+ if (memory_dtb) -+ of_scan_flat_dt(early_init_dt_scan_memory, NULL); -+ else if (soc_info.mem_size) - add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, - BOOT_MEM_RAM); - else diff --git a/target/linux/ramips/patches-3.18/0009-MIPS-ralink-define-the-wmac-clock-on-mt7620.patch b/target/linux/ramips/patches-3.18/0009-MIPS-ralink-define-the-wmac-clock-on-mt7620.patch deleted file mode 100644 index 225afd503c..0000000000 --- a/target/linux/ramips/patches-3.18/0009-MIPS-ralink-define-the-wmac-clock-on-mt7620.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 1cb19fe02c830e278b91498edea09fbda37c4a21 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 10:13:43 +0100 -Subject: [PATCH 09/57] MIPS: ralink: define the wmac clock on mt7620 - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/mt7620.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -336,6 +336,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("10000500.uart", periph_rate); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", periph_rate); -+ ralink_clk_add("10180000.wmac", xtal_rate); - } - - void __init ralink_of_remap(void) diff --git a/target/linux/ramips/patches-3.18/0010-MIPS-ralink-define-the-wmac-clock-on-rt3883.patch b/target/linux/ramips/patches-3.18/0010-MIPS-ralink-define-the-wmac-clock-on-rt3883.patch deleted file mode 100644 index 2de066be4b..0000000000 --- a/target/linux/ramips/patches-3.18/0010-MIPS-ralink-define-the-wmac-clock-on-rt3883.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 1f17cf131fc2ae7fa2651dbe6a622dd125939718 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 10:14:30 +0100 -Subject: [PATCH 10/57] MIPS: ralink: define the wmac clock on rt3883 - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/rt3883.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/ralink/rt3883.c -+++ b/arch/mips/ralink/rt3883.c -@@ -204,6 +204,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", 40000000); - ralink_clk_add("10100000.ethernet", sys_rate); -+ ralink_clk_add("10180000.wmac", 40000000); - } - - void __init ralink_of_remap(void) diff --git a/target/linux/ramips/patches-3.18/0011-MIPS-ralink-add-rt2880-wmac-clock.patch b/target/linux/ramips/patches-3.18/0011-MIPS-ralink-add-rt2880-wmac-clock.patch deleted file mode 100644 index 76d2f6a354..0000000000 --- a/target/linux/ramips/patches-3.18/0011-MIPS-ralink-add-rt2880-wmac-clock.patch +++ /dev/null @@ -1,29 +0,0 @@ -From bf4f5250117cd65a78903b8ce302499806416ed1 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Mon, 4 Aug 2014 09:52:22 +0200 -Subject: [PATCH 11/57] MIPS: ralink: add rt2880 wmac clock - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/rt288x.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/mips/ralink/rt288x.c -+++ b/arch/mips/ralink/rt288x.c -@@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = { - - void __init ralink_clk_init(void) - { -- unsigned long cpu_rate; -+ unsigned long cpu_rate, wmac_rate = 40000000; - u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); - t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); - -@@ -101,6 +101,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("300500.uart", cpu_rate / 2); - ralink_clk_add("300c00.uartlite", cpu_rate / 2); - ralink_clk_add("400000.ethernet", cpu_rate / 2); -+ ralink_clk_add("480000.wmac", wmac_rate); - } - - void __init ralink_of_remap(void) diff --git a/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch b/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch deleted file mode 100644 index 1e5c90b6c8..0000000000 --- a/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch +++ /dev/null @@ -1,104 +0,0 @@ -From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 24 Jan 2014 17:01:17 +0100 -Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk - -Add support for the new MT7621/8 SoC and kill ifdefs. -Cleanup some whitespace error while we are at it. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++------------- - 1 file changed, 30 insertions(+), 15 deletions(-) - ---- a/arch/mips/ralink/early_printk.c -+++ b/arch/mips/ralink/early_printk.c -@@ -12,21 +12,26 @@ - #include <asm/addrspace.h> - - #ifdef CONFIG_SOC_RT288X --#define EARLY_UART_BASE 0x300c00 -+#define EARLY_UART_BASE 0x300c00 -+#define CHIPID_BASE 0x300004 -+#elif defined(CONFIG_SOC_MT7621) -+#define EARLY_UART_BASE 0x1E000c00 -+#define CHIPID_BASE 0x1E000004 - #else --#define EARLY_UART_BASE 0x10000c00 -+#define EARLY_UART_BASE 0x10000c00 -+#define CHIPID_BASE 0x10000004 - #endif - --#define UART_REG_RX 0x00 --#define UART_REG_TX 0x04 --#define UART_REG_IER 0x08 --#define UART_REG_IIR 0x0c --#define UART_REG_FCR 0x10 --#define UART_REG_LCR 0x14 --#define UART_REG_MCR 0x18 --#define UART_REG_LSR 0x1c -+#define MT7628_CHIP_NAME1 0x20203832 -+ -+#define UART_REG_TX 0x04 -+#define UART_REG_LCR 0x0c -+#define UART_REG_LSR 0x14 -+#define UART_REG_LSR_RT2880 0x1c - - static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); -+static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); -+static int init_complete; - - static inline void uart_w32(u32 val, unsigned reg) - { -@@ -38,11 +43,46 @@ static inline u32 uart_r32(unsigned reg) - return __raw_readl(uart_membase + reg); - } - -+static inline int soc_is_mt7628(void) -+{ -+ return IS_ENABLED(CONFIG_SOC_MT7620) && -+ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); -+} -+ -+static inline void find_uart_base(void) -+{ -+ int i; -+ -+ if (!soc_is_mt7628()) -+ return; -+ -+ for (i = 0; i < 3; i++) { -+ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); -+ -+ if (!reg) -+ continue; -+ -+ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i)); -+ break; -+ } -+} -+ - void prom_putchar(unsigned char ch) - { -- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) -- ; -- uart_w32(ch, UART_REG_TX); -- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) -- ; -+ if (!init_complete) { -+ find_uart_base(); -+ init_complete = 1; -+ } -+ -+ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { -+ uart_w32(ch, UART_TX); -+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) -+ ; -+ } else { -+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0) -+ ; -+ uart_w32(ch, UART_REG_TX); -+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0) -+ ; -+ } - } diff --git a/target/linux/ramips/patches-3.18/0017-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-3.18/0017-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch deleted file mode 100644 index 6bf0401f06..0000000000 --- a/target/linux/ramips/patches-3.18/0017-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch +++ /dev/null @@ -1,99 +0,0 @@ -From f8da5caf65926d44581d4e7914b28ceab3d28a7c Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 14 Jul 2013 23:08:11 +0200 -Subject: [PATCH 17/57] MIPS: use set_mode() to enable/disable the cevt-r4k - irq - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/kernel/cevt-r4k.c | 37 +++++++++++++++++++++++++++++++------ - 1 file changed, 31 insertions(+), 6 deletions(-) - ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -29,12 +29,6 @@ static int mips_next_event(unsigned long - return res; - } - --void mips_set_clock_mode(enum clock_event_mode mode, -- struct clock_event_device *evt) --{ -- /* Nothing to do ... */ --} -- - DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); - int cp0_timer_irq_installed; - -@@ -75,9 +69,38 @@ struct irqaction c0_compare_irqaction = - .name = "timer", - }; - -+void mips_set_clock_mode(enum clock_event_mode mode, -+ struct clock_event_device *evt) -+{ -+#ifdef CONFIG_CEVT_SYSTICK_QUIRK -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: -+ if (cp0_timer_irq_installed) -+ break; -+ -+ cp0_timer_irq_installed = 1; -+ -+ setup_irq(evt->irq, &c0_compare_irqaction); -+ break; -+ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ if (!cp0_timer_irq_installed) -+ break; -+ -+ cp0_timer_irq_installed = 0; -+ remove_irq(evt->irq, &c0_compare_irqaction); -+ break; -+ -+ default: -+ pr_err("Unhandeled mips clock_mode\n"); -+ break; -+ } -+#endif -+} - - void mips_event_handler(struct clock_event_device *dev) - { -+ - } - - /* -@@ -198,12 +221,14 @@ int r4k_clockevent_init(void) - - clockevents_register_device(cd); - -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - if (cp0_timer_irq_installed) - return 0; - - cp0_timer_irq_installed = 1; - - setup_irq(irq, &c0_compare_irqaction); -+#endif - - return 0; - } ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -1,11 +1,16 @@ - if RALINK - -+config CEVT_SYSTICK_QUIRK -+ bool -+ default n -+ - config CLKEVT_RT3352 - bool - depends on SOC_RT305X || SOC_MT7620 - default y - select CLKSRC_OF - select CLKSRC_MMIO -+ select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC - bool diff --git a/target/linux/ramips/patches-3.18/0019-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch b/target/linux/ramips/patches-3.18/0019-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch deleted file mode 100644 index eff7cda72f..0000000000 --- a/target/linux/ramips/patches-3.18/0019-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch +++ /dev/null @@ -1,300 +0,0 @@ -From 9de00286e20a5f5edc419698373010f1cb6ff0ce Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:25:02 +0100 -Subject: [PATCH 19/57] MIPS: ralink: add pseudo pwm led trigger based on - timer0 - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/timer.c | 213 ++++++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 197 insertions(+), 16 deletions(-) - ---- a/arch/mips/ralink/timer.c -+++ b/arch/mips/ralink/timer.c -@@ -12,6 +12,8 @@ - #include <linux/timer.h> - #include <linux/of_gpio.h> - #include <linux/clk.h> -+#include <linux/leds.h> -+#include <linux/slab.h> - - #include <asm/mach-ralink/ralink_regs.h> - -@@ -23,16 +25,34 @@ - - #define TMR0CTL_ENABLE BIT(7) - #define TMR0CTL_MODE_PERIODIC BIT(4) --#define TMR0CTL_PRESCALER 1 -+#define TMR0CTL_PRESCALER 2 - #define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER) - #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER)) - -+struct rt_timer_gpio { -+ struct list_head list; -+ struct led_classdev *led; -+}; -+ - struct rt_timer { -- struct device *dev; -- void __iomem *membase; -- int irq; -- unsigned long timer_freq; -- unsigned long timer_div; -+ struct device *dev; -+ void __iomem *membase; -+ int irq; -+ -+ unsigned long timer_freq; -+ unsigned long timer_div; -+ -+ struct list_head gpios; -+ struct led_trigger led_trigger; -+ unsigned int duty_cycle; -+ unsigned int duty; -+ -+ unsigned int fade; -+ unsigned int fade_min; -+ unsigned int fade_max; -+ unsigned int fade_speed; -+ unsigned int fade_dir; -+ unsigned int fade_count; - }; - - static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) -@@ -48,8 +68,37 @@ static inline u32 rt_timer_r32(struct rt - static irqreturn_t rt_timer_irq(int irq, void *_rt) - { - struct rt_timer *rt = (struct rt_timer *) _rt; -+ struct rt_timer_gpio *gpio; -+ unsigned int val; - -- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); -+ if (rt->fade && (rt->fade_count++ > rt->fade_speed)) { -+ rt->fade_count = 0; -+ if (rt->duty_cycle <= rt->fade_min) -+ rt->fade_dir = 1; -+ else if (rt->duty_cycle >= rt->fade_max) -+ rt->fade_dir = 0; -+ -+ if (rt->fade_dir) -+ rt->duty_cycle += 1; -+ else -+ rt->duty_cycle -= 1; -+ -+ } -+ -+ val = rt->timer_freq / rt->timer_div; -+ if (rt->duty) -+ val *= rt->duty_cycle; -+ else -+ val *= (100 - rt->duty_cycle); -+ val /= 100; -+ -+ if (!list_empty(&rt->gpios)) -+ list_for_each_entry(gpio, &rt->gpios, list) -+ led_set_brightness(gpio->led, !!rt->duty); -+ -+ rt->duty = !rt->duty; -+ -+ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1); - rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT); - - return IRQ_HANDLED; -@@ -58,8 +107,8 @@ static irqreturn_t rt_timer_irq(int irq, - - static int rt_timer_request(struct rt_timer *rt) - { -- int err = request_irq(rt->irq, rt_timer_irq, 0, -- dev_name(rt->dev), rt); -+ int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq, -+ 0, dev_name(rt->dev), rt); - if (err) { - dev_err(rt->dev, "failed to request irq\n"); - } else { -@@ -81,8 +130,6 @@ static int rt_timer_config(struct rt_tim - else - rt->timer_div = divisor; - -- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); -- - return 0; - } - -@@ -108,11 +155,128 @@ static void rt_timer_disable(struct rt_t - rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); - } - -+static ssize_t led_fade_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct led_classdev *led_cdev = dev_get_drvdata(dev); -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ -+ return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max); -+} -+ -+static ssize_t led_fade_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct led_classdev *led_cdev = dev_get_drvdata(dev); -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ unsigned int speed = 0, min = 0, max = 0; -+ ssize_t ret = -EINVAL; -+ -+ ret = sscanf(buf, "%u %u %u", &speed, &min, &max); -+ -+ if (ret == 3) { -+ rt->fade_speed = speed; -+ rt->fade_min = min; -+ rt->fade_max = max; -+ rt->fade = 1; -+ } else { -+ rt->fade = 0; -+ } -+ -+ return size; -+} -+ -+static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store); -+ -+static ssize_t led_duty_cycle_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct led_classdev *led_cdev = dev_get_drvdata(dev); -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ -+ return sprintf(buf, "%u\n", rt->duty_cycle); -+} -+ -+static ssize_t led_duty_cycle_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct led_classdev *led_cdev = dev_get_drvdata(dev); -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ unsigned long state; -+ ssize_t ret = -EINVAL; -+ -+ ret = kstrtoul(buf, 10, &state); -+ if (ret) -+ return ret; -+ -+ if (state <= 100) -+ rt->duty_cycle = state; -+ else -+ rt->duty_cycle = 100; -+ -+ rt->fade = 0; -+ -+ return size; -+} -+ -+static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store); -+ -+static void rt_timer_trig_activate(struct led_classdev *led_cdev) -+{ -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ struct rt_timer_gpio *gpio_data; -+ int rc; -+ -+ led_cdev->trigger_data = NULL; -+ gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL); -+ if (!gpio_data) -+ return; -+ -+ rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle); -+ if (rc) -+ goto err_gpio; -+ rc = device_create_file(led_cdev->dev, &dev_attr_fade); -+ if (rc) -+ goto err_out_duty_cycle; -+ -+ led_cdev->activated = true; -+ led_cdev->trigger_data = gpio_data; -+ gpio_data->led = led_cdev; -+ list_add(&gpio_data->list, &rt->gpios); -+ led_cdev->trigger_data = gpio_data; -+ rt_timer_enable(rt); -+ return; -+ -+err_out_duty_cycle: -+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle); -+ -+err_gpio: -+ kfree(gpio_data); -+} -+ -+static void rt_timer_trig_deactivate(struct led_classdev *led_cdev) -+{ -+ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger); -+ struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data; -+ -+ if (led_cdev->activated) { -+ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle); -+ device_remove_file(led_cdev->dev, &dev_attr_fade); -+ led_cdev->activated = false; -+ } -+ -+ list_del(&gpio_data->list); -+ rt_timer_disable(rt); -+ led_set_brightness(led_cdev, LED_OFF); -+} -+ - static int rt_timer_probe(struct platform_device *pdev) - { - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ const __be32 *divisor; - struct rt_timer *rt; - struct clk *clk; -+ int ret; - - rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL); - if (!rt) { -@@ -140,12 +304,29 @@ static int rt_timer_probe(struct platfor - if (!rt->timer_freq) - return -EINVAL; - -+ rt->duty_cycle = 100; - rt->dev = &pdev->dev; - platform_set_drvdata(pdev, rt); - -- rt_timer_request(rt); -- rt_timer_config(rt, 2); -- rt_timer_enable(rt); -+ ret = rt_timer_request(rt); -+ if (ret) -+ return ret; -+ -+ divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL); -+ if (divisor) -+ rt_timer_config(rt, be32_to_cpu(*divisor)); -+ else -+ rt_timer_config(rt, 200); -+ -+ rt->led_trigger.name = "pwmtimer", -+ rt->led_trigger.activate = rt_timer_trig_activate, -+ rt->led_trigger.deactivate = rt_timer_trig_deactivate, -+ -+ ret = led_trigger_register(&rt->led_trigger); -+ if (ret) -+ return ret; -+ -+ INIT_LIST_HEAD(&rt->gpios); - - dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq); - -@@ -156,6 +337,7 @@ static int rt_timer_remove(struct platfo - { - struct rt_timer *rt = platform_get_drvdata(pdev); - -+ led_trigger_unregister(&rt->led_trigger); - rt_timer_disable(rt); - rt_timer_free(rt); - -@@ -180,6 +362,6 @@ static struct platform_driver rt_timer_d - - module_platform_driver(rt_timer_driver); - --MODULE_DESCRIPTION("Ralink RT2880 timer"); -+MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm"); - MODULE_AUTHOR("John Crispin <blogic@openwrt.org"); - MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/patches-3.18/0025-MIPS-ralink-allow-loading-irq-registers-from-the-dev.patch b/target/linux/ramips/patches-3.18/0025-MIPS-ralink-allow-loading-irq-registers-from-the-dev.patch deleted file mode 100644 index f21ca3c7de..0000000000 --- a/target/linux/ramips/patches-3.18/0025-MIPS-ralink-allow-loading-irq-registers-from-the-dev.patch +++ /dev/null @@ -1,75 +0,0 @@ -From b1cc9a15f6ead8dbd849257e42d69a5799fb7597 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Wed, 6 Aug 2014 18:24:36 +0200 -Subject: [PATCH 25/57] MIPS: ralink: allow loading irq registers from the - devicetree - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/ralink/irq.c | 33 +++++++++++++++++++++++---------- - 1 file changed, 23 insertions(+), 10 deletions(-) - ---- a/arch/mips/ralink/irq.c -+++ b/arch/mips/ralink/irq.c -@@ -20,14 +20,6 @@ - - #include "common.h" - --/* INTC register offsets */ --#define INTC_REG_STATUS0 0x00 --#define INTC_REG_STATUS1 0x04 --#define INTC_REG_TYPE 0x20 --#define INTC_REG_RAW_STATUS 0x30 --#define INTC_REG_ENABLE 0x34 --#define INTC_REG_DISABLE 0x38 -- - #define INTC_INT_GLOBAL BIT(31) - - #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) -@@ -44,16 +36,34 @@ - - #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9) - -+enum rt_intc_regs_enum { -+ INTC_REG_STATUS0 = 0, -+ INTC_REG_STATUS1, -+ INTC_REG_TYPE, -+ INTC_REG_RAW_STATUS, -+ INTC_REG_ENABLE, -+ INTC_REG_DISABLE, -+}; -+ -+static u32 rt_intc_regs[] = { -+ [INTC_REG_STATUS0] = 0x00, -+ [INTC_REG_STATUS1] = 0x04, -+ [INTC_REG_TYPE] = 0x20, -+ [INTC_REG_RAW_STATUS] = 0x30, -+ [INTC_REG_ENABLE] = 0x34, -+ [INTC_REG_DISABLE] = 0x38, -+}; -+ - static void __iomem *rt_intc_membase; - - static inline void rt_intc_w32(u32 val, unsigned reg) - { -- __raw_writel(val, rt_intc_membase + reg); -+ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]); - } - - static inline u32 rt_intc_r32(unsigned reg) - { -- return __raw_readl(rt_intc_membase + reg); -+ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]); - } - - static void ralink_intc_irq_unmask(struct irq_data *d) -@@ -134,6 +144,9 @@ static int __init intc_of_init(struct de - struct irq_domain *domain; - int irq; - -+ if (!of_property_read_u32_array(node, "ralink,intc-registers", rt_intc_regs, 6)) -+ pr_info("intc: using register map from devicetree\n"); -+ - irq = irq_of_parse_and_map(node, 0); - if (!irq) - panic("Failed to get INTC IRQ"); diff --git a/target/linux/ramips/patches-3.18/0026-MIPS-ralink-add-mt7628an-support.patch b/target/linux/ramips/patches-3.18/0026-MIPS-ralink-add-mt7628an-support.patch deleted file mode 100644 index c5c5d1a446..0000000000 --- a/target/linux/ramips/patches-3.18/0026-MIPS-ralink-add-mt7628an-support.patch +++ /dev/null @@ -1,398 +0,0 @@ -From a375beba066516ecafddebc765454ac6ec599f3d Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Wed, 6 Aug 2014 18:26:08 +0200 -Subject: [PATCH 26/57] MIPS: ralink: add mt7628an support - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/include/asm/mach-ralink/mt7620.h | 11 ++ - arch/mips/ralink/Kconfig | 2 +- - arch/mips/ralink/mt7620.c | 266 +++++++++++++++++++++++----- - 3 files changed, 232 insertions(+), 47 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -13,6 +13,13 @@ - #ifndef _MT7620_REGS_H_ - #define _MT7620_REGS_H_ - -+enum mt762x_soc_type { -+ MT762X_SOC_UNKNOWN = 0, -+ MT762X_SOC_MT7620A, -+ MT762X_SOC_MT7620N, -+ MT762X_SOC_MT7628AN, -+}; -+ - #define MT7620_SYSC_BASE 0x10000000 - - #define SYSC_REG_CHIP_NAME0 0x00 -@@ -27,6 +34,7 @@ - - #define MT7620_CHIP_NAME0 0x3637544d - #define MT7620_CHIP_NAME1 0x20203032 -+#define MT7628_CHIP_NAME1 0x20203832 - - #define SYSCFG0_XTAL_FREQ_SEL BIT(6) - -@@ -71,6 +79,9 @@ - #define SYSCFG0_DRAM_TYPE_DDR1 1 - #define SYSCFG0_DRAM_TYPE_DDR2 2 - -+#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0 -+#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1 -+ - #define MT7620_DRAM_BASE 0x0 - #define MT7620_SDRAM_SIZE_MIN 2 - #define MT7620_SDRAM_SIZE_MAX 64 ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -41,7 +41,7 @@ choice - select HW_HAS_PCI - - config SOC_MT7620 -- bool "MT7620" -+ bool "MT7620/8" - - config SOC_MT7621 - bool "MT7621" ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -42,6 +42,8 @@ - #define CLKCFG_FFRAC_MASK 0x001f - #define CLKCFG_FFRAC_USB_VAL 0x0003 - -+enum mt762x_soc_type mt762x_soc; -+ - /* does the board have sdram or ddram */ - static int dram_type; - -@@ -159,6 +161,125 @@ struct ralink_pinmux rt_gpio_pinmux = { - .uart_mask = MT7620_GPIO_MODE_UART0_MASK, - }; - -+static struct rt2880_pmx_func pwm1_grp_mt7628[] = { -+ FUNC("sdxc", 3, 19, 1), -+ FUNC("utif", 2, 19, 1), -+ FUNC("gpio", 1, 19, 1), -+ FUNC("pwm", 0, 19, 1), -+}; -+ -+static struct rt2880_pmx_func pwm0_grp_mt7628[] = { -+ FUNC("sdxc", 3, 18, 1), -+ FUNC("utif", 2, 18, 1), -+ FUNC("gpio", 1, 18, 1), -+ FUNC("pwm", 0, 18, 1), -+}; -+ -+static struct rt2880_pmx_func uart2_grp_mt7628[] = { -+ FUNC("sdxc", 3, 20, 2), -+ FUNC("pwm", 2, 20, 2), -+ FUNC("gpio", 1, 20, 2), -+ FUNC("uart2", 0, 20, 2), -+}; -+ -+static struct rt2880_pmx_func uart1_grp_mt7628[] = { -+ FUNC("sdxc", 3, 45, 2), -+ FUNC("pwm", 2, 45, 2), -+ FUNC("gpio", 1, 45, 2), -+ FUNC("uart1", 0, 45, 2), -+}; -+ -+static struct rt2880_pmx_func i2c_grp_mt7628[] = { -+ FUNC("-", 3, 4, 2), -+ FUNC("debug", 2, 4, 2), -+ FUNC("gpio", 1, 4, 2), -+ FUNC("i2c", 0, 4, 2), -+}; -+ -+static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) }; -+static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) }; -+static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; -+static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; -+ -+static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { -+ FUNC("jtag", 3, 22, 8), -+ FUNC("utif", 2, 22, 8), -+ FUNC("gpio", 1, 22, 8), -+ FUNC("sdxc", 0, 22, 8), -+}; -+ -+static struct rt2880_pmx_func uart0_grp_mt7628[] = { -+ FUNC("-", 3, 12, 2), -+ FUNC("-", 2, 12, 2), -+ FUNC("gpio", 1, 12, 2), -+ FUNC("uart0", 0, 12, 2), -+}; -+ -+static struct rt2880_pmx_func i2s_grp_mt7628[] = { -+ FUNC("antenna", 3, 0, 4), -+ FUNC("pcm", 2, 0, 4), -+ FUNC("gpio", 1, 0, 4), -+ FUNC("i2s", 0, 0, 4), -+}; -+ -+static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { -+ FUNC("-", 3, 6, 1), -+ FUNC("refclk", 2, 6, 1), -+ FUNC("gpio", 1, 6, 1), -+ FUNC("spi", 0, 6, 1), -+}; -+ -+static struct rt2880_pmx_func spis_grp_mt7628[] = { -+ FUNC("pwm", 3, 14, 4), -+ FUNC("util", 2, 14, 4), -+ FUNC("gpio", 1, 14, 4), -+ FUNC("spis", 0, 14, 4), -+}; -+ -+static struct rt2880_pmx_func gpio_grp_mt7628[] = { -+ FUNC("pcie", 3, 11, 1), -+ FUNC("refclk", 2, 11, 1), -+ FUNC("gpio", 1, 11, 1), -+ FUNC("gpio", 0, 11, 1), -+}; -+ -+#define MT7628_GPIO_MODE_MASK 0x3 -+ -+#define MT7628_GPIO_MODE_PWM1 30 -+#define MT7628_GPIO_MODE_PWM0 28 -+#define MT7628_GPIO_MODE_UART2 26 -+#define MT7628_GPIO_MODE_UART1 24 -+#define MT7628_GPIO_MODE_I2C 20 -+#define MT7628_GPIO_MODE_REFCLK 18 -+#define MT7628_GPIO_MODE_PERST 16 -+#define MT7628_GPIO_MODE_WDT 14 -+#define MT7628_GPIO_MODE_SPI 12 -+#define MT7628_GPIO_MODE_SDMODE 10 -+#define MT7628_GPIO_MODE_UART0 8 -+#define MT7628_GPIO_MODE_I2S 6 -+#define MT7628_GPIO_MODE_CS1 4 -+#define MT7628_GPIO_MODE_SPIS 2 -+#define MT7628_GPIO_MODE_GPIO 0 -+ -+static struct rt2880_pmx_group mt7628an_pinmux_data[] = { -+ GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1), -+ GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0), -+ GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2), -+ GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1), -+ GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C), -+ GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), -+ GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), -+ GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), -+ GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), -+ GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SDMODE), -+ GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART0), -+ GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2S), -+ GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1), -+ GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS), -+ GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO), -+ { 0 } -+}; -+ - static __init u32 - mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) - { -@@ -309,29 +430,42 @@ void __init ralink_clk_init(void) - - xtal_rate = mt7620_get_xtal_rate(); - -- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); -- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); -- -- cpu_rate = mt7620_get_cpu_rate(pll_rate); -- dram_rate = mt7620_get_dram_rate(pll_rate); -- sys_rate = mt7620_get_sys_rate(cpu_rate); -- periph_rate = mt7620_get_periph_rate(xtal_rate); -- - #define RFMT(label) label ":%lu.%03luMHz " - #define RINT(x) ((x) / 1000000) - #define RFRAC(x) (((x) / 1000) % 1000) - -- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), -- RINT(xtal_rate), RFRAC(xtal_rate), -- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), -- RINT(pll_rate), RFRAC(pll_rate)); -+ if (mt762x_soc == MT762X_SOC_MT7628AN) { -+ if (xtal_rate == MHZ(40)) -+ cpu_rate = MHZ(580); -+ else -+ cpu_rate = MHZ(575); -+ dram_rate = sys_rate = cpu_rate / 3; -+ periph_rate = MHZ(40); -+ -+ ralink_clk_add("10000d00.uartlite", periph_rate); -+ ralink_clk_add("10000e00.uartlite", periph_rate); -+ } else { -+ cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); -+ pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); -+ -+ cpu_rate = mt7620_get_cpu_rate(pll_rate); -+ dram_rate = mt7620_get_dram_rate(pll_rate); -+ sys_rate = mt7620_get_sys_rate(cpu_rate); -+ periph_rate = mt7620_get_periph_rate(xtal_rate); -+ -+ pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), -+ RINT(xtal_rate), RFRAC(xtal_rate), -+ RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), -+ RINT(pll_rate), RFRAC(pll_rate)); -+ -+ ralink_clk_add("10000500.uart", periph_rate); -+ } - - pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), - RINT(cpu_rate), RFRAC(cpu_rate), - RINT(dram_rate), RFRAC(dram_rate), - RINT(sys_rate), RFRAC(sys_rate), - RINT(periph_rate), RFRAC(periph_rate)); -- - #undef RFRAC - #undef RINT - #undef RFMT -@@ -339,12 +473,13 @@ void __init ralink_clk_init(void) - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", periph_rate); - ralink_clk_add("10000120.watchdog", periph_rate); -- ralink_clk_add("10000500.uart", periph_rate); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", periph_rate); -+ ralink_clk_add("10000d00.uart1", periph_rate); -+ ralink_clk_add("10000e00.uart2", periph_rate); - ralink_clk_add("10180000.wmac", xtal_rate); - -- if (IS_ENABLED(CONFIG_USB)) { -+ if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) { - /* - * When the CPU goes into sleep mode, the BUS clock will be too low for - * USB to function properly -@@ -367,6 +502,52 @@ void __init ralink_of_remap(void) - panic("Failed to remap core resources"); - } - -+static __init void -+mt7620_dram_init(struct ralink_soc_info *soc_info) -+{ -+ switch (dram_type) { -+ case SYSCFG0_DRAM_TYPE_SDRAM: -+ pr_info("Board has SDRAM\n"); -+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; -+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; -+ break; -+ -+ case SYSCFG0_DRAM_TYPE_DDR1: -+ pr_info("Board has DDR1\n"); -+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; -+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; -+ break; -+ -+ case SYSCFG0_DRAM_TYPE_DDR2: -+ pr_info("Board has DDR2\n"); -+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; -+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+static __init void -+mt7628_dram_init(struct ralink_soc_info *soc_info) -+{ -+ switch (dram_type) { -+ case SYSCFG0_DRAM_TYPE_DDR1_MT7628: -+ pr_info("Board has DDR1\n"); -+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; -+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; -+ break; -+ -+ case SYSCFG0_DRAM_TYPE_DDR2_MT7628: -+ pr_info("Board has DDR2\n"); -+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; -+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; -+ break; -+ default: -+ BUG(); -+ } -+} -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); -@@ -384,18 +565,25 @@ void prom_soc_init(struct ralink_soc_inf - rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); - bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; - -- if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1) -- panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1); -- -- if (bga) { -- name = "MT7620A"; -- soc_info->compatible = "ralink,mt7620a-soc"; -- } else { -- name = "MT7620N"; -- soc_info->compatible = "ralink,mt7620n-soc"; -+ if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { -+ if (bga) { -+ mt762x_soc = MT762X_SOC_MT7620A; -+ name = "MT7620A"; -+ soc_info->compatible = "ralink,mt7620a-soc"; -+ } else { -+ mt762x_soc = MT762X_SOC_MT7620N; -+ name = "MT7620N"; -+ soc_info->compatible = "ralink,mt7620n-soc"; - #ifdef CONFIG_PCI -- panic("mt7620n is only supported for non pci kernels"); -+ panic("mt7620n is only supported for non pci kernels"); - #endif -+ } -+ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { -+ mt762x_soc = MT762X_SOC_MT7628AN; -+ name = "MT7628AN"; -+ soc_info->compatible = "ralink,mt7628an-soc"; -+ } else { -+ panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); - } - - snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, -@@ -407,28 +595,11 @@ void prom_soc_init(struct ralink_soc_inf - cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); - dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; - -- switch (dram_type) { -- case SYSCFG0_DRAM_TYPE_SDRAM: -- pr_info("Board has SDRAM\n"); -- soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; -- soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; -- break; -- -- case SYSCFG0_DRAM_TYPE_DDR1: -- pr_info("Board has DDR1\n"); -- soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; -- soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; -- break; -- -- case SYSCFG0_DRAM_TYPE_DDR2: -- pr_info("Board has DDR2\n"); -- soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; -- soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; -- break; -- default: -- BUG(); -- } - soc_info->mem_base = MT7620_DRAM_BASE; -+ if (mt762x_soc == MT762X_SOC_MT7628AN) -+ mt7628_dram_init(soc_info); -+ else -+ mt7620_dram_init(soc_info); - - pmu0 = __raw_readl(sysc + PMU0_CFG); - pmu1 = __raw_readl(sysc + PMU1_CFG); -@@ -437,4 +608,9 @@ void prom_soc_init(struct ralink_soc_inf - (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); - pr_info("Digital PMU set to %s control\n", - (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); -+ -+ if (mt762x_soc == MT762X_SOC_MT7628AN) -+ rt2880_pinmux_data = mt7628an_pinmux_data; -+ else -+ rt2880_pinmux_data = mt7620a_pinmux_data; - } diff --git a/target/linux/ramips/patches-3.18/0027-serial-ralink-adds-mt7620-serial.patch b/target/linux/ramips/patches-3.18/0027-serial-ralink-adds-mt7620-serial.patch deleted file mode 100644 index c7f59c1638..0000000000 --- a/target/linux/ramips/patches-3.18/0027-serial-ralink-adds-mt7620-serial.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 0b24e0e6bf2d9a1ca5f95446bc025dafc226998c Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 15 Mar 2013 18:16:01 +0100 -Subject: [PATCH 27/57] serial: ralink: adds mt7620 serial - -Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - drivers/tty/serial/8250/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/8250/Kconfig -+++ b/drivers/tty/serial/8250/Kconfig -@@ -297,7 +297,7 @@ config SERIAL_8250_EM - - config SERIAL_8250_RT288X - bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support" -- depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883) -+ depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620) - help - If you have a Ralink RT288x/RT305x SoC based board and want to use the - serial port, say Y to this option. The driver can handle up to 2 serial diff --git a/target/linux/ramips/patches-3.18/0028-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch b/target/linux/ramips/patches-3.18/0028-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch deleted file mode 100644 index ab60f2d549..0000000000 --- a/target/linux/ramips/patches-3.18/0028-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch +++ /dev/null @@ -1,22 +0,0 @@ -From b9ba09038dab4d824176ea2c2f2b73f49b567217 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 16 Mar 2014 04:52:01 +0000 -Subject: [PATCH 28/57] serial: ralink: the core has a size of 0x100 and not - 0x1000 - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - drivers/tty/serial/8250/8250_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/8250/8250_core.c -+++ b/drivers/tty/serial/8250/8250_core.c -@@ -2634,7 +2634,7 @@ serial8250_pm(struct uart_port *port, un - static unsigned int serial8250_port_size(struct uart_8250_port *pt) - { - if (pt->port.iotype == UPIO_AU) -- return 0x1000; -+ return 0x100; - if (is_omap1_8250(pt)) - return 0x16 << pt->port.regshift; - diff --git a/target/linux/ramips/patches-3.18/0029-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch b/target/linux/ramips/patches-3.18/0029-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch deleted file mode 100644 index ef29697e20..0000000000 --- a/target/linux/ramips/patches-3.18/0029-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 49b47dfcef1353cd28eac8f64170e75d28ce4311 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 14 Jul 2013 23:18:57 +0200 -Subject: [PATCH 29/57] serial: of: allow au1x00 and rt288x to load from OF - -In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need -to default the iotype to UPIO_AU. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - drivers/tty/serial/of_serial.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/tty/serial/of_serial.c -+++ b/drivers/tty/serial/of_serial.c -@@ -102,7 +102,10 @@ static int of_platform_serial_setup(stru - port->fifosize = prop; - - port->irq = irq_of_parse_and_map(np, 0); -- port->iotype = UPIO_MEM; -+ if (of_device_is_compatible(np, "ralink,rt2880-uart")) -+ port->iotype = UPIO_AU; -+ else -+ port->iotype = UPIO_MEM; - if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { - switch (prop) { - case 1: diff --git a/target/linux/ramips/patches-3.18/0030-pinctrl-ralink-add-pinctrl-driver.patch b/target/linux/ramips/patches-3.18/0030-pinctrl-ralink-add-pinctrl-driver.patch deleted file mode 100644 index 63e84019d9..0000000000 --- a/target/linux/ramips/patches-3.18/0030-pinctrl-ralink-add-pinctrl-driver.patch +++ /dev/null @@ -1,1404 +0,0 @@ -From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:34:05 +0100 -Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/Kconfig | 2 + - arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++- - arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++ - arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++- - arch/mips/include/asm/mach-ralink/rt3883.h | 16 +- - arch/mips/ralink/common.h | 19 -- - arch/mips/ralink/mt7620.c | 159 +++------- - arch/mips/ralink/rt288x.c | 62 ++-- - arch/mips/ralink/rt305x.c | 151 ++++----- - arch/mips/ralink/rt3883.c | 173 +++-------- - drivers/pinctrl/Kconfig | 5 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++ - 13 files changed, 764 insertions(+), 420 deletions(-) - create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h - create mode 100644 drivers/pinctrl/pinctrl-rt2880.c - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -453,6 +453,8 @@ config RALINK - select CLKDEV_LOOKUP - select ARCH_HAS_RESET_CONTROLLER - select RESET_CONTROLLER -+ select PINCTRL -+ select PINCTRL_RT2880 - - config SGI_IP22 - bool "SGI IP22 (Indy/Indigo2)" ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -90,7 +90,6 @@ enum mt762x_soc_type { - #define MT7620_DDR2_SIZE_MIN 32 - #define MT7620_DDR2_SIZE_MAX 256 - --#define MT7620_GPIO_MODE_I2C BIT(0) - #define MT7620_GPIO_MODE_UART0_SHIFT 2 - #define MT7620_GPIO_MODE_UART0_MASK 0x7 - #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) -@@ -102,16 +101,36 @@ enum mt762x_soc_type { - #define MT7620_GPIO_MODE_GPIO_UARTF 0x5 - #define MT7620_GPIO_MODE_GPIO_I2S 0x6 - #define MT7620_GPIO_MODE_GPIO 0x7 --#define MT7620_GPIO_MODE_UART1 BIT(5) --#define MT7620_GPIO_MODE_MDIO BIT(8) --#define MT7620_GPIO_MODE_RGMII1 BIT(9) --#define MT7620_GPIO_MODE_RGMII2 BIT(10) --#define MT7620_GPIO_MODE_SPI BIT(11) --#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) --#define MT7620_GPIO_MODE_WLED BIT(13) --#define MT7620_GPIO_MODE_JTAG BIT(15) --#define MT7620_GPIO_MODE_EPHY BIT(15) --#define MT7620_GPIO_MODE_WDT BIT(22) -+ -+#define MT7620_GPIO_MODE_NAND 0 -+#define MT7620_GPIO_MODE_SD 1 -+#define MT7620_GPIO_MODE_ND_SD_GPIO 2 -+#define MT7620_GPIO_MODE_ND_SD_MASK 0x3 -+#define MT7620_GPIO_MODE_ND_SD_SHIFT 18 -+ -+#define MT7620_GPIO_MODE_PCIE_RST 0 -+#define MT7620_GPIO_MODE_PCIE_REF 1 -+#define MT7620_GPIO_MODE_PCIE_GPIO 2 -+#define MT7620_GPIO_MODE_PCIE_MASK 0x3 -+#define MT7620_GPIO_MODE_PCIE_SHIFT 16 -+ -+#define MT7620_GPIO_MODE_WDT_RST 0 -+#define MT7620_GPIO_MODE_WDT_REF 1 -+#define MT7620_GPIO_MODE_WDT_GPIO 2 -+#define MT7620_GPIO_MODE_WDT_MASK 0x3 -+#define MT7620_GPIO_MODE_WDT_SHIFT 21 -+ -+#define MT7620_GPIO_MODE_I2C 0 -+#define MT7620_GPIO_MODE_UART1 5 -+#define MT7620_GPIO_MODE_MDIO 8 -+#define MT7620_GPIO_MODE_RGMII1 9 -+#define MT7620_GPIO_MODE_RGMII2 10 -+#define MT7620_GPIO_MODE_SPI 11 -+#define MT7620_GPIO_MODE_SPI_REF_CLK 12 -+#define MT7620_GPIO_MODE_WLED 13 -+#define MT7620_GPIO_MODE_JTAG 15 -+#define MT7620_GPIO_MODE_EPHY 15 -+#define MT7620_GPIO_MODE_PA 20 - - static inline int mt7620_get_eco(void) - { ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/pinmux.h -@@ -0,0 +1,53 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * publishhed by the Free Software Foundation. -+ * -+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org> -+ */ -+ -+#ifndef _RT288X_PINMUX_H__ -+#define _RT288X_PINMUX_H__ -+ -+#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count } -+#define GRP(_name, _func, _mask, _shift) \ -+ { .name = _name, .mask = _mask, .shift = _shift, \ -+ .func = _func, .gpio = _mask, \ -+ .func_count = ARRAY_SIZE(_func) } -+ -+#define GRP_G(_name, _func, _mask, _gpio, _shift) \ -+ { .name = _name, .mask = _mask, .shift = _shift, \ -+ .func = _func, .gpio = _gpio, \ -+ .func_count = ARRAY_SIZE(_func) } -+ -+struct rt2880_pmx_group; -+ -+struct rt2880_pmx_func { -+ const char *name; -+ const char value; -+ -+ int pin_first; -+ int pin_count; -+ int *pins; -+ -+ int *groups; -+ int group_count; -+ -+ int enabled; -+}; -+ -+struct rt2880_pmx_group { -+ const char *name; -+ int enabled; -+ -+ const u32 shift; -+ const char mask; -+ const char gpio; -+ -+ struct rt2880_pmx_func *func; -+ int func_count; -+}; -+ -+extern struct rt2880_pmx_group *rt2880_pinmux_data; -+ -+#endif ---- a/arch/mips/include/asm/mach-ralink/rt305x.h -+++ b/arch/mips/include/asm/mach-ralink/rt305x.h -@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void) - #define RT305X_GPIO_GE0_TXD0 40 - #define RT305X_GPIO_GE0_RXCLK 51 - --#define RT305X_GPIO_MODE_I2C BIT(0) --#define RT305X_GPIO_MODE_SPI BIT(1) - #define RT305X_GPIO_MODE_UART0_SHIFT 2 - #define RT305X_GPIO_MODE_UART0_MASK 0x7 - #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) --#define RT305X_GPIO_MODE_UARTF 0x0 --#define RT305X_GPIO_MODE_PCM_UARTF 0x1 --#define RT305X_GPIO_MODE_PCM_I2S 0x2 --#define RT305X_GPIO_MODE_I2S_UARTF 0x3 --#define RT305X_GPIO_MODE_PCM_GPIO 0x4 --#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 --#define RT305X_GPIO_MODE_GPIO_I2S 0x6 --#define RT305X_GPIO_MODE_GPIO 0x7 --#define RT305X_GPIO_MODE_UART1 BIT(5) --#define RT305X_GPIO_MODE_JTAG BIT(6) --#define RT305X_GPIO_MODE_MDIO BIT(7) --#define RT305X_GPIO_MODE_SDRAM BIT(8) --#define RT305X_GPIO_MODE_RGMII BIT(9) -+#define RT305X_GPIO_MODE_UARTF 0 -+#define RT305X_GPIO_MODE_PCM_UARTF 1 -+#define RT305X_GPIO_MODE_PCM_I2S 2 -+#define RT305X_GPIO_MODE_I2S_UARTF 3 -+#define RT305X_GPIO_MODE_PCM_GPIO 4 -+#define RT305X_GPIO_MODE_GPIO_UARTF 5 -+#define RT305X_GPIO_MODE_GPIO_I2S 6 -+#define RT305X_GPIO_MODE_GPIO 7 -+ -+#define RT305X_GPIO_MODE_I2C 0 -+#define RT305X_GPIO_MODE_SPI 1 -+#define RT305X_GPIO_MODE_UART1 5 -+#define RT305X_GPIO_MODE_JTAG 6 -+#define RT305X_GPIO_MODE_MDIO 7 -+#define RT305X_GPIO_MODE_SDRAM 8 -+#define RT305X_GPIO_MODE_RGMII 9 -+#define RT5350_GPIO_MODE_PHY_LED 14 -+#define RT5350_GPIO_MODE_SPI_CS1 21 -+#define RT3352_GPIO_MODE_LNA 18 -+#define RT3352_GPIO_MODE_PA 20 - - #define RT3352_SYSC_REG_SYSCFG0 0x010 - #define RT3352_SYSC_REG_SYSCFG1 0x014 ---- a/arch/mips/include/asm/mach-ralink/rt3883.h -+++ b/arch/mips/include/asm/mach-ralink/rt3883.h -@@ -112,8 +112,6 @@ - #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) - #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) - --#define RT3883_GPIO_MODE_I2C BIT(0) --#define RT3883_GPIO_MODE_SPI BIT(1) - #define RT3883_GPIO_MODE_UART0_SHIFT 2 - #define RT3883_GPIO_MODE_UART0_MASK 0x7 - #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) -@@ -125,11 +123,15 @@ - #define RT3883_GPIO_MODE_GPIO_UARTF 0x5 - #define RT3883_GPIO_MODE_GPIO_I2S 0x6 - #define RT3883_GPIO_MODE_GPIO 0x7 --#define RT3883_GPIO_MODE_UART1 BIT(5) --#define RT3883_GPIO_MODE_JTAG BIT(6) --#define RT3883_GPIO_MODE_MDIO BIT(7) --#define RT3883_GPIO_MODE_GE1 BIT(9) --#define RT3883_GPIO_MODE_GE2 BIT(10) -+ -+#define RT3883_GPIO_MODE_I2C 0 -+#define RT3883_GPIO_MODE_SPI 1 -+#define RT3883_GPIO_MODE_UART1 5 -+#define RT3883_GPIO_MODE_JTAG 6 -+#define RT3883_GPIO_MODE_MDIO 7 -+#define RT3883_GPIO_MODE_GE1 9 -+#define RT3883_GPIO_MODE_GE2 10 -+ - #define RT3883_GPIO_MODE_PCI_SHIFT 11 - #define RT3883_GPIO_MODE_PCI_MASK 0x7 - #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -11,25 +11,6 @@ - - #define RAMIPS_SYS_TYPE_LEN 32 - --struct ralink_pinmux_grp { -- const char *name; -- u32 mask; -- int gpio_first; -- int gpio_last; --}; -- --struct ralink_pinmux { -- struct ralink_pinmux_grp *mode; -- struct ralink_pinmux_grp *uart; -- int uart_shift; -- u32 uart_mask; -- void (*wdt_reset)(void); -- struct ralink_pinmux_grp *pci; -- int pci_shift; -- u32 pci_mask; --}; --extern struct ralink_pinmux rt_gpio_pinmux; -- - struct ralink_soc_info { - unsigned char sys_type[RAMIPS_SYS_TYPE_LEN]; - unsigned char *compatible; ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -17,6 +17,7 @@ - #include <asm/mipsregs.h> - #include <asm/mach-ralink/ralink_regs.h> - #include <asm/mach-ralink/mt7620.h> -+#include <asm/mach-ralink/pinmux.h> - - #include "common.h" - -@@ -47,118 +48,58 @@ enum mt762x_soc_type mt762x_soc; - /* does the board have sdram or ddram */ - static int dram_type; - --static struct ralink_pinmux_grp mode_mux[] = { -- { -- .name = "i2c", -- .mask = MT7620_GPIO_MODE_I2C, -- .gpio_first = 1, -- .gpio_last = 2, -- }, { -- .name = "spi", -- .mask = MT7620_GPIO_MODE_SPI, -- .gpio_first = 3, -- .gpio_last = 6, -- }, { -- .name = "uartlite", -- .mask = MT7620_GPIO_MODE_UART1, -- .gpio_first = 15, -- .gpio_last = 16, -- }, { -- .name = "wdt", -- .mask = MT7620_GPIO_MODE_WDT, -- .gpio_first = 17, -- .gpio_last = 17, -- }, { -- .name = "mdio", -- .mask = MT7620_GPIO_MODE_MDIO, -- .gpio_first = 22, -- .gpio_last = 23, -- }, { -- .name = "rgmii1", -- .mask = MT7620_GPIO_MODE_RGMII1, -- .gpio_first = 24, -- .gpio_last = 35, -- }, { -- .name = "spi refclk", -- .mask = MT7620_GPIO_MODE_SPI_REF_CLK, -- .gpio_first = 37, -- .gpio_last = 39, -- }, { -- .name = "jtag", -- .mask = MT7620_GPIO_MODE_JTAG, -- .gpio_first = 40, -- .gpio_last = 44, -- }, { -- /* shared lines with jtag */ -- .name = "ephy", -- .mask = MT7620_GPIO_MODE_EPHY, -- .gpio_first = 40, -- .gpio_last = 44, -- }, { -- .name = "nand", -- .mask = MT7620_GPIO_MODE_JTAG, -- .gpio_first = 45, -- .gpio_last = 59, -- }, { -- .name = "rgmii2", -- .mask = MT7620_GPIO_MODE_RGMII2, -- .gpio_first = 60, -- .gpio_last = 71, -- }, { -- .name = "wled", -- .mask = MT7620_GPIO_MODE_WLED, -- .gpio_first = 72, -- .gpio_last = 72, -- }, {0} -+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -+static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -+static struct rt2880_pmx_func uartf_grp[] = { -+ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), -+ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), -+ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), -+ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), -+ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), -+ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), -+ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), - }; -- --static struct ralink_pinmux_grp uart_mux[] = { -- { -- .name = "uartf", -- .mask = MT7620_GPIO_MODE_UARTF, -- .gpio_first = 7, -- .gpio_last = 14, -- }, { -- .name = "pcm uartf", -- .mask = MT7620_GPIO_MODE_PCM_UARTF, -- .gpio_first = 7, -- .gpio_last = 14, -- }, { -- .name = "pcm i2s", -- .mask = MT7620_GPIO_MODE_PCM_I2S, -- .gpio_first = 7, -- .gpio_last = 14, -- }, { -- .name = "i2s uartf", -- .mask = MT7620_GPIO_MODE_I2S_UARTF, -- .gpio_first = 7, -- .gpio_last = 14, -- }, { -- .name = "pcm gpio", -- .mask = MT7620_GPIO_MODE_PCM_GPIO, -- .gpio_first = 11, -- .gpio_last = 14, -- }, { -- .name = "gpio uartf", -- .mask = MT7620_GPIO_MODE_GPIO_UARTF, -- .gpio_first = 7, -- .gpio_last = 10, -- }, { -- .name = "gpio i2s", -- .mask = MT7620_GPIO_MODE_GPIO_I2S, -- .gpio_first = 7, -- .gpio_last = 10, -- }, { -- .name = "gpio", -- .mask = MT7620_GPIO_MODE_GPIO, -- }, {0} -+static struct rt2880_pmx_func wdt_grp[] = { -+ FUNC("wdt rst", 0, 17, 1), -+ FUNC("wdt refclk", 0, 17, 1), -+ }; -+static struct rt2880_pmx_func pcie_rst_grp[] = { -+ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), -+ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) -+}; -+static struct rt2880_pmx_func nd_sd_grp[] = { -+ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), -+ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15) - }; - --struct ralink_pinmux rt_gpio_pinmux = { -- .mode = mode_mux, -- .uart = uart_mux, -- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT, -- .uart_mask = MT7620_GPIO_MODE_UART0_MASK, -+static struct rt2880_pmx_group mt7620a_pinmux_data[] = { -+ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), -+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, -+ MT7620_GPIO_MODE_UART0_SHIFT), -+ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), -+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), -+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, -+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), -+ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO), -+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), -+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), -+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, -+ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), -+ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, -+ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), -+ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), -+ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), -+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), -+ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), -+ { 0 } - }; - - static struct rt2880_pmx_func pwm1_grp_mt7628[] = { ---- a/arch/mips/ralink/rt288x.c -+++ b/arch/mips/ralink/rt288x.c -@@ -17,46 +17,27 @@ - #include <asm/mipsregs.h> - #include <asm/mach-ralink/ralink_regs.h> - #include <asm/mach-ralink/rt288x.h> -+#include <asm/mach-ralink/pinmux.h> - - #include "common.h" - --static struct ralink_pinmux_grp mode_mux[] = { -- { -- .name = "i2c", -- .mask = RT2880_GPIO_MODE_I2C, -- .gpio_first = 1, -- .gpio_last = 2, -- }, { -- .name = "spi", -- .mask = RT2880_GPIO_MODE_SPI, -- .gpio_first = 3, -- .gpio_last = 6, -- }, { -- .name = "uartlite", -- .mask = RT2880_GPIO_MODE_UART0, -- .gpio_first = 7, -- .gpio_last = 14, -- }, { -- .name = "jtag", -- .mask = RT2880_GPIO_MODE_JTAG, -- .gpio_first = 17, -- .gpio_last = 21, -- }, { -- .name = "mdio", -- .mask = RT2880_GPIO_MODE_MDIO, -- .gpio_first = 22, -- .gpio_last = 23, -- }, { -- .name = "sdram", -- .mask = RT2880_GPIO_MODE_SDRAM, -- .gpio_first = 24, -- .gpio_last = 39, -- }, { -- .name = "pci", -- .mask = RT2880_GPIO_MODE_PCI, -- .gpio_first = 40, -- .gpio_last = 71, -- }, {0} -+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; -+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -+static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; -+ -+static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { -+ GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), -+ GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), -+ GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), -+ GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG), -+ GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO), -+ GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM), -+ GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI), -+ { 0 } - }; - - static void rt288x_wdt_reset(void) -@@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void) - rt_sysc_w32(t, SYSC_REG_CLKCFG); - } - --struct ralink_pinmux rt_gpio_pinmux = { -- .mode = mode_mux, -- .wdt_reset = rt288x_wdt_reset, --}; -- - void __init ralink_clk_init(void) - { - unsigned long cpu_rate, wmac_rate = 40000000; -@@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->mem_base = RT2880_SDRAM_BASE; - soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; - soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; -+ -+ rt2880_pinmux_data = rt2880_pinmux_data_act; - } ---- a/arch/mips/ralink/rt305x.c -+++ b/arch/mips/ralink/rt305x.c -@@ -17,90 +17,76 @@ - #include <asm/mipsregs.h> - #include <asm/mach-ralink/ralink_regs.h> - #include <asm/mach-ralink/rt305x.h> -+#include <asm/mach-ralink/pinmux.h> - - #include "common.h" - - enum rt305x_soc_type rt305x_soc; - --static struct ralink_pinmux_grp mode_mux[] = { -- { -- .name = "i2c", -- .mask = RT305X_GPIO_MODE_I2C, -- .gpio_first = RT305X_GPIO_I2C_SD, -- .gpio_last = RT305X_GPIO_I2C_SCLK, -- }, { -- .name = "spi", -- .mask = RT305X_GPIO_MODE_SPI, -- .gpio_first = RT305X_GPIO_SPI_EN, -- .gpio_last = RT305X_GPIO_SPI_CLK, -- }, { -- .name = "uartlite", -- .mask = RT305X_GPIO_MODE_UART1, -- .gpio_first = RT305X_GPIO_UART1_TXD, -- .gpio_last = RT305X_GPIO_UART1_RXD, -- }, { -- .name = "jtag", -- .mask = RT305X_GPIO_MODE_JTAG, -- .gpio_first = RT305X_GPIO_JTAG_TDO, -- .gpio_last = RT305X_GPIO_JTAG_TDI, -- }, { -- .name = "mdio", -- .mask = RT305X_GPIO_MODE_MDIO, -- .gpio_first = RT305X_GPIO_MDIO_MDC, -- .gpio_last = RT305X_GPIO_MDIO_MDIO, -- }, { -- .name = "sdram", -- .mask = RT305X_GPIO_MODE_SDRAM, -- .gpio_first = RT305X_GPIO_SDRAM_MD16, -- .gpio_last = RT305X_GPIO_SDRAM_MD31, -- }, { -- .name = "rgmii", -- .mask = RT305X_GPIO_MODE_RGMII, -- .gpio_first = RT305X_GPIO_GE0_TXD0, -- .gpio_last = RT305X_GPIO_GE0_RXCLK, -- }, {0} -+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -+static struct rt2880_pmx_func uartf_func[] = { -+ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), -+ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), -+ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), -+ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), -+ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), -+ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), -+ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), -+}; -+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -+static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; -+static struct rt2880_pmx_func rt5350_cs1_func[] = { -+ FUNC("spi_cs1", 0, 27, 1), -+ FUNC("wdg_cs1", 1, 27, 1), -+}; -+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -+static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) }; -+static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; -+static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; -+static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; -+static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; -+ -+static struct rt2880_pmx_group rt3050_pinmux_data[] = { -+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), -+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), -+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, -+ RT305X_GPIO_MODE_UART0_SHIFT), -+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), -+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), -+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), -+ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), -+ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), -+ { 0 } -+}; -+ -+static struct rt2880_pmx_group rt3352_pinmux_data[] = { -+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), -+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), -+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, -+ RT305X_GPIO_MODE_UART0_SHIFT), -+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), -+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), -+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), -+ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), -+ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), -+ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), -+ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), -+ { 0 } - }; - --static struct ralink_pinmux_grp uart_mux[] = { -- { -- .name = "uartf", -- .mask = RT305X_GPIO_MODE_UARTF, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_14, -- }, { -- .name = "pcm uartf", -- .mask = RT305X_GPIO_MODE_PCM_UARTF, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_14, -- }, { -- .name = "pcm i2s", -- .mask = RT305X_GPIO_MODE_PCM_I2S, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_14, -- }, { -- .name = "i2s uartf", -- .mask = RT305X_GPIO_MODE_I2S_UARTF, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_14, -- }, { -- .name = "pcm gpio", -- .mask = RT305X_GPIO_MODE_PCM_GPIO, -- .gpio_first = RT305X_GPIO_10, -- .gpio_last = RT305X_GPIO_14, -- }, { -- .name = "gpio uartf", -- .mask = RT305X_GPIO_MODE_GPIO_UARTF, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_10, -- }, { -- .name = "gpio i2s", -- .mask = RT305X_GPIO_MODE_GPIO_I2S, -- .gpio_first = RT305X_GPIO_7, -- .gpio_last = RT305X_GPIO_10, -- }, { -- .name = "gpio", -- .mask = RT305X_GPIO_MODE_GPIO, -- }, {0} -+static struct rt2880_pmx_group rt5350_pinmux_data[] = { -+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), -+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), -+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, -+ RT305X_GPIO_MODE_UART0_SHIFT), -+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), -+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), -+ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), -+ GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), -+ { 0 } - }; - - static void rt305x_wdt_reset(void) -@@ -114,14 +100,6 @@ static void rt305x_wdt_reset(void) - rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); - } - --struct ralink_pinmux rt_gpio_pinmux = { -- .mode = mode_mux, -- .uart = uart_mux, -- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, -- .uart_mask = RT305X_GPIO_MODE_UART0_MASK, -- .wdt_reset = rt305x_wdt_reset, --}; -- - static unsigned long rt5350_get_mem_size(void) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); -@@ -290,11 +268,14 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->mem_base = RT305X_SDRAM_BASE; - if (soc_is_rt5350()) { - soc_info->mem_size = rt5350_get_mem_size(); -+ rt2880_pinmux_data = rt5350_pinmux_data; - } else if (soc_is_rt305x() || soc_is_rt3350()) { - soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; - soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; -+ rt2880_pinmux_data = rt3050_pinmux_data; - } else if (soc_is_rt3352()) { - soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; - soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; -+ rt2880_pinmux_data = rt3352_pinmux_data; - } - } ---- a/arch/mips/ralink/rt3883.c -+++ b/arch/mips/ralink/rt3883.c -@@ -17,132 +17,50 @@ - #include <asm/mipsregs.h> - #include <asm/mach-ralink/ralink_regs.h> - #include <asm/mach-ralink/rt3883.h> -+#include <asm/mach-ralink/pinmux.h> - - #include "common.h" - --static struct ralink_pinmux_grp mode_mux[] = { -- { -- .name = "i2c", -- .mask = RT3883_GPIO_MODE_I2C, -- .gpio_first = RT3883_GPIO_I2C_SD, -- .gpio_last = RT3883_GPIO_I2C_SCLK, -- }, { -- .name = "spi", -- .mask = RT3883_GPIO_MODE_SPI, -- .gpio_first = RT3883_GPIO_SPI_CS0, -- .gpio_last = RT3883_GPIO_SPI_MISO, -- }, { -- .name = "uartlite", -- .mask = RT3883_GPIO_MODE_UART1, -- .gpio_first = RT3883_GPIO_UART1_TXD, -- .gpio_last = RT3883_GPIO_UART1_RXD, -- }, { -- .name = "jtag", -- .mask = RT3883_GPIO_MODE_JTAG, -- .gpio_first = RT3883_GPIO_JTAG_TDO, -- .gpio_last = RT3883_GPIO_JTAG_TCLK, -- }, { -- .name = "mdio", -- .mask = RT3883_GPIO_MODE_MDIO, -- .gpio_first = RT3883_GPIO_MDIO_MDC, -- .gpio_last = RT3883_GPIO_MDIO_MDIO, -- }, { -- .name = "ge1", -- .mask = RT3883_GPIO_MODE_GE1, -- .gpio_first = RT3883_GPIO_GE1_TXD0, -- .gpio_last = RT3883_GPIO_GE1_RXCLK, -- }, { -- .name = "ge2", -- .mask = RT3883_GPIO_MODE_GE2, -- .gpio_first = RT3883_GPIO_GE2_TXD0, -- .gpio_last = RT3883_GPIO_GE2_RXCLK, -- }, { -- .name = "pci", -- .mask = RT3883_GPIO_MODE_PCI, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, { -- .name = "lna a", -- .mask = RT3883_GPIO_MODE_LNA_A, -- .gpio_first = RT3883_GPIO_LNA_PE_A0, -- .gpio_last = RT3883_GPIO_LNA_PE_A2, -- }, { -- .name = "lna g", -- .mask = RT3883_GPIO_MODE_LNA_G, -- .gpio_first = RT3883_GPIO_LNA_PE_G0, -- .gpio_last = RT3883_GPIO_LNA_PE_G2, -- }, {0} -+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -+static struct rt2880_pmx_func uartf_func[] = { -+ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), -+ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), -+ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), -+ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8), -+ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4), -+ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), -+ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), - }; -- --static struct ralink_pinmux_grp uart_mux[] = { -- { -- .name = "uartf", -- .mask = RT3883_GPIO_MODE_UARTF, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_14, -- }, { -- .name = "pcm uartf", -- .mask = RT3883_GPIO_MODE_PCM_UARTF, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_14, -- }, { -- .name = "pcm i2s", -- .mask = RT3883_GPIO_MODE_PCM_I2S, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_14, -- }, { -- .name = "i2s uartf", -- .mask = RT3883_GPIO_MODE_I2S_UARTF, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_14, -- }, { -- .name = "pcm gpio", -- .mask = RT3883_GPIO_MODE_PCM_GPIO, -- .gpio_first = RT3883_GPIO_11, -- .gpio_last = RT3883_GPIO_14, -- }, { -- .name = "gpio uartf", -- .mask = RT3883_GPIO_MODE_GPIO_UARTF, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_10, -- }, { -- .name = "gpio i2s", -- .mask = RT3883_GPIO_MODE_GPIO_I2S, -- .gpio_first = RT3883_GPIO_7, -- .gpio_last = RT3883_GPIO_10, -- }, { -- .name = "gpio", -- .mask = RT3883_GPIO_MODE_GPIO, -- }, {0} -+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -+static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; -+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) }; -+static struct rt2880_pmx_func pci_func[] = { -+ FUNC("pci-dev", 0, 40, 32), -+ FUNC("pci-host2", 1, 40, 32), -+ FUNC("pci-host1", 2, 40, 32), -+ FUNC("pci-fnc", 3, 40, 32) - }; -+static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 84, 12) }; -+static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 72, 12) }; - --static struct ralink_pinmux_grp pci_mux[] = { -- { -- .name = "pci-dev", -- .mask = 0, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, { -- .name = "pci-host2", -- .mask = 1, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, { -- .name = "pci-host1", -- .mask = 2, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, { -- .name = "pci-fnc", -- .mask = 3, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, { -- .name = "pci-gpio", -- .mask = 7, -- .gpio_first = RT3883_GPIO_PCI_AD0, -- .gpio_last = RT3883_GPIO_PCI_AD31, -- }, {0} -+static struct rt2880_pmx_group rt3883_pinmux_data[] = { -+ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), -+ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), -+ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, -+ RT3883_GPIO_MODE_UART0_SHIFT), -+ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1), -+ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG), -+ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO), -+ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A), -+ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G), -+ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK, -+ RT3883_GPIO_MODE_PCI_SHIFT), -+ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1), -+ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2), -+ { 0 } - }; - - static void rt3883_wdt_reset(void) -@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void) - rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1); - } - --struct ralink_pinmux rt_gpio_pinmux = { -- .mode = mode_mux, -- .uart = uart_mux, -- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT, -- .uart_mask = RT3883_GPIO_MODE_UART0_MASK, -- .wdt_reset = rt3883_wdt_reset, -- .pci = pci_mux, -- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT, -- .pci_mask = RT3883_GPIO_MODE_PCI_MASK, --}; -- - void __init ralink_clk_init(void) - { - unsigned long cpu_rate, sys_rate; -@@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->mem_base = RT3883_SDRAM_BASE; - soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; - soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; -+ -+ rt2880_pinmux_data = rt3883_pinmux_data; - } ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -103,6 +103,11 @@ config PINCTRL_LANTIQ - select PINMUX - select PINCONF - -+config PINCTRL_RT2880 -+ bool -+ depends on RALINK -+ select PINMUX -+ - config PINCTRL_FALCON - bool - depends on SOC_FALCON ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctr - obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o - obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o - obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o -+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o - obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o - obj-$(CONFIG_PINCTRL_SIRF) += sirf/ - obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o ---- /dev/null -+++ b/drivers/pinctrl/pinctrl-rt2880.c -@@ -0,0 +1,474 @@ -+/* -+ * linux/drivers/pinctrl/pinctrl-rt2880.c -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * publishhed by the Free Software Foundation. -+ * -+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org> -+ */ -+ -+#include <linux/module.h> -+#include <linux/device.h> -+#include <linux/io.h> -+#include <linux/platform_device.h> -+#include <linux/slab.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinctrl.h> -+#include <linux/pinctrl/pinconf.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/pinctrl/consumer.h> -+#include <linux/pinctrl/machine.h> -+ -+#include <asm/mach-ralink/ralink_regs.h> -+#include <asm/mach-ralink/pinmux.h> -+#include <asm/mach-ralink/mt7620.h> -+ -+#include "core.h" -+ -+#define SYSC_REG_GPIO_MODE 0x60 -+#define SYSC_REG_GPIO_MODE2 0x64 -+ -+struct rt2880_priv { -+ struct device *dev; -+ -+ struct pinctrl_pin_desc *pads; -+ struct pinctrl_desc *desc; -+ -+ struct rt2880_pmx_func **func; -+ int func_count; -+ -+ struct rt2880_pmx_group *groups; -+ const char **group_names; -+ int group_count; -+ -+ uint8_t *gpio; -+ int max_pins; -+}; -+ -+struct rt2880_pmx_group *rt2880_pinmux_data = NULL; -+ -+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ return p->group_count; -+} -+ -+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev, -+ unsigned group) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ if (group >= p->group_count) -+ return NULL; -+ -+ return p->group_names[group]; -+} -+ -+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev, -+ unsigned group, -+ const unsigned **pins, -+ unsigned *num_pins) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ if (group >= p->group_count) -+ return -EINVAL; -+ -+ *pins = p->groups[group].func[0].pins; -+ *num_pins = p->groups[group].func[0].pin_count; -+ -+ return 0; -+} -+ -+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev, -+ struct pinctrl_map *map, unsigned num_maps) -+{ -+ int i; -+ -+ for (i = 0; i < num_maps; i++) -+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN || -+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) -+ kfree(map[i].data.configs.configs); -+ kfree(map); -+} -+ -+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev, -+ struct seq_file *s, -+ unsigned offset) -+{ -+ seq_printf(s, "ralink pio"); -+} -+ -+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev, -+ struct device_node *np, -+ struct pinctrl_map **map) -+{ -+ const char *function; -+ int func = of_property_read_string(np, "ralink,function", &function); -+ int grps = of_property_count_strings(np, "ralink,group"); -+ int i; -+ -+ if (func || !grps) -+ return; -+ -+ for (i = 0; i < grps; i++) { -+ const char *group; -+ -+ of_property_read_string_index(np, "ralink,group", i, &group); -+ -+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP; -+ (*map)->name = function; -+ (*map)->data.mux.group = group; -+ (*map)->data.mux.function = function; -+ (*map)++; -+ } -+} -+ -+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev, -+ struct device_node *np_config, -+ struct pinctrl_map **map, -+ unsigned *num_maps) -+{ -+ int max_maps = 0; -+ struct pinctrl_map *tmp; -+ struct device_node *np; -+ -+ for_each_child_of_node(np_config, np) { -+ int ret = of_property_count_strings(np, "ralink,group"); -+ -+ if (ret >= 0) -+ max_maps += ret; -+ } -+ -+ if (!max_maps) -+ return max_maps; -+ -+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL); -+ if (!*map) -+ return -ENOMEM; -+ -+ tmp = *map; -+ -+ for_each_child_of_node(np_config, np) -+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp); -+ *num_maps = max_maps; -+ -+ return 0; -+} -+ -+static const struct pinctrl_ops rt2880_pctrl_ops = { -+ .get_groups_count = rt2880_get_group_count, -+ .get_group_name = rt2880_get_group_name, -+ .get_group_pins = rt2880_get_group_pins, -+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show, -+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map, -+ .dt_free_map = rt2880_pinctrl_dt_free_map, -+}; -+ -+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ return p->func_count; -+} -+ -+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev, -+ unsigned func) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ return p->func[func]->name; -+} -+ -+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev, -+ unsigned func, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ if (p->func[func]->group_count == 1) -+ *groups = &p->group_names[p->func[func]->groups[0]]; -+ else -+ *groups = p->group_names; -+ -+ *num_groups = p->func[func]->group_count; -+ -+ return 0; -+} -+ -+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev, -+ unsigned func, -+ unsigned group) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ u32 mode = 0; -+ u32 reg = SYSC_REG_GPIO_MODE; -+ int i; -+ int shift; -+ -+ /* dont allow double use */ -+ if (p->groups[group].enabled) { -+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name); -+ return -EBUSY; -+ } -+ -+ p->groups[group].enabled = 1; -+ p->func[func]->enabled = 1; -+ -+ shift = p->groups[group].shift; -+ if (shift >= 32) { -+ shift -= 32; -+ reg = SYSC_REG_GPIO_MODE2; -+ } -+ mode = rt_sysc_r32(reg); -+ mode &= ~(p->groups[group].mask << shift); -+ -+ /* mark the pins as gpio */ -+ for (i = 0; i < p->groups[group].func[0].pin_count; i++) -+ p->gpio[p->groups[group].func[0].pins[i]] = 1; -+ -+ /* function 0 is gpio and needs special handling */ -+ if (func == 0) { -+ mode |= p->groups[group].gpio << shift; -+ } else { -+ for (i = 0; i < p->func[func]->pin_count; i++) -+ p->gpio[p->func[func]->pins[i]] = 0; -+ mode |= p->func[func]->value << shift; -+ } -+ rt_sysc_w32(mode, reg); -+ -+ return 0; -+} -+ -+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, -+ struct pinctrl_gpio_range *range, -+ unsigned pin) -+{ -+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); -+ -+ if (!p->gpio[pin]) { -+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static const struct pinmux_ops rt2880_pmx_group_ops = { -+ .get_functions_count = rt2880_pmx_func_count, -+ .get_function_name = rt2880_pmx_func_name, -+ .get_function_groups = rt2880_pmx_group_get_groups, -+ .set_mux = rt2880_pmx_group_enable, -+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable, -+}; -+ -+static struct pinctrl_desc rt2880_pctrl_desc = { -+ .owner = THIS_MODULE, -+ .name = "rt2880-pinmux", -+ .pctlops = &rt2880_pctrl_ops, -+ .pmxops = &rt2880_pmx_group_ops, -+}; -+ -+static struct rt2880_pmx_func gpio_func = { -+ .name = "gpio", -+}; -+ -+static int rt2880_pinmux_index(struct rt2880_priv *p) -+{ -+ struct rt2880_pmx_func **f; -+ struct rt2880_pmx_group *mux = p->groups; -+ int i, j, c = 0; -+ -+ /* count the mux functions */ -+ while (mux->name) { -+ p->group_count++; -+ mux++; -+ } -+ -+ /* allocate the group names array needed by the gpio function */ -+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL); -+ if (!p->group_names) -+ return -1; -+ -+ for (i = 0; i < p->group_count; i++) { -+ p->group_names[i] = p->groups[i].name; -+ p->func_count += p->groups[i].func_count; -+ } -+ -+ /* we have a dummy function[0] for gpio */ -+ p->func_count++; -+ -+ /* allocate our function and group mapping index buffers */ -+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL); -+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL); -+ if (!f || !gpio_func.groups) -+ return -1; -+ -+ /* add a backpointer to the function so it knows its group */ -+ gpio_func.group_count = p->group_count; -+ for (i = 0; i < gpio_func.group_count; i++) -+ gpio_func.groups[i] = i; -+ -+ f[c] = &gpio_func; -+ c++; -+ -+ /* add remaining functions */ -+ for (i = 0; i < p->group_count; i++) { -+ for (j = 0; j < p->groups[i].func_count; j++) { -+ f[c] = &p->groups[i].func[j]; -+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL); -+ f[c]->groups[0] = i; -+ f[c]->group_count = 1; -+ c++; -+ } -+ } -+ return 0; -+} -+ -+static int rt2880_pinmux_pins(struct rt2880_priv *p) -+{ -+ int i, j; -+ -+ /* loop over the functions and initialize the pins array. also work out the highest pin used */ -+ for (i = 0; i < p->func_count; i++) { -+ int pin; -+ -+ if (!p->func[i]->pin_count) -+ continue; -+ -+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL); -+ for (j = 0; j < p->func[i]->pin_count; j++) -+ p->func[i]->pins[j] = p->func[i]->pin_first + j; -+ -+ pin = p->func[i]->pin_first + p->func[i]->pin_count; -+ if (pin > p->max_pins) -+ p->max_pins = pin; -+ } -+ -+ /* the buffer that tells us which pins are gpio */ -+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins, -+ GFP_KERNEL); -+ /* the pads needed to tell pinctrl about our pins */ -+ p->pads = devm_kzalloc(p->dev, -+ sizeof(struct pinctrl_pin_desc) * p->max_pins, -+ GFP_KERNEL); -+ if (!p->pads || !p->gpio ) { -+ dev_err(p->dev, "Failed to allocate gpio data\n"); -+ return -ENOMEM; -+ } -+ -+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins); -+ for (i = 0; i < p->func_count; i++) { -+ if (!p->func[i]->pin_count) -+ continue; -+ -+ for (j = 0; j < p->func[i]->pin_count; j++) -+ p->gpio[p->func[i]->pins[j]] = 0; -+ } -+ -+ /* pin 0 is always a gpio */ -+ p->gpio[0] = 1; -+ -+ /* set the pads */ -+ for (i = 0; i < p->max_pins; i++) { -+ /* strlen("ioXY") + 1 = 5 */ -+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL); -+ -+ if (!name) { -+ dev_err(p->dev, "Failed to allocate pad name\n"); -+ return -ENOMEM; -+ } -+ snprintf(name, 5, "io%d", i); -+ p->pads[i].number = i; -+ p->pads[i].name = name; -+ } -+ p->desc->pins = p->pads; -+ p->desc->npins = p->max_pins; -+ -+ return 0; -+} -+ -+static int rt2880_pinmux_probe(struct platform_device *pdev) -+{ -+ struct rt2880_priv *p; -+ struct pinctrl_dev *dev; -+ struct device_node *np; -+ -+ if (!rt2880_pinmux_data) -+ return -ENOSYS; -+ -+ /* setup the private data */ -+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL); -+ if (!p) -+ return -ENOMEM; -+ -+ p->dev = &pdev->dev; -+ p->desc = &rt2880_pctrl_desc; -+ p->groups = rt2880_pinmux_data; -+ platform_set_drvdata(pdev, p); -+ -+ /* init the device */ -+ if (rt2880_pinmux_index(p)) { -+ dev_err(&pdev->dev, "failed to load index\n"); -+ return -EINVAL; -+ } -+ if (rt2880_pinmux_pins(p)) { -+ dev_err(&pdev->dev, "failed to load pins\n"); -+ return -EINVAL; -+ } -+ dev = pinctrl_register(p->desc, &pdev->dev, p); -+ if (IS_ERR(dev)) -+ return PTR_ERR(dev); -+ -+ /* finalize by adding gpio ranges for enables gpio controllers */ -+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") { -+ const __be32 *ngpio, *gpiobase; -+ struct pinctrl_gpio_range *range; -+ char *name; -+ -+ if (!of_device_is_available(np)) -+ continue; -+ -+ ngpio = of_get_property(np, "ralink,num-gpios", NULL); -+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL); -+ if (!ngpio || !gpiobase) { -+ dev_err(&pdev->dev, "failed to load chip info\n"); -+ return -EINVAL; -+ } -+ -+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL); -+ range->name = name = (char *) &range[1]; -+ sprintf(name, "pio"); -+ range->npins = __be32_to_cpu(*ngpio); -+ range->base = __be32_to_cpu(*gpiobase); -+ range->pin_base = range->base; -+ pinctrl_add_gpio_range(dev, range); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id rt2880_pinmux_match[] = { -+ { .compatible = "ralink,rt2880-pinmux" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match); -+ -+static struct platform_driver rt2880_pinmux_driver = { -+ .probe = rt2880_pinmux_probe, -+ .driver = { -+ .name = "rt2880-pinmux", -+ .owner = THIS_MODULE, -+ .of_match_table = rt2880_pinmux_match, -+ }, -+}; -+ -+int __init rt2880_pinmux_init(void) -+{ -+ return platform_driver_register(&rt2880_pinmux_driver); -+} -+ -+core_initcall_sync(rt2880_pinmux_init); diff --git a/target/linux/ramips/patches-3.18/0031-PCI-MIPS-adds-rt2880-pci-support.patch b/target/linux/ramips/patches-3.18/0031-PCI-MIPS-adds-rt2880-pci-support.patch deleted file mode 100644 index 193f1c28b4..0000000000 --- a/target/linux/ramips/patches-3.18/0031-PCI-MIPS-adds-rt2880-pci-support.patch +++ /dev/null @@ -1,319 +0,0 @@ -From 5b0bcc314005dd14eeae190948165a81eef7da1f Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:36:02 +0100 -Subject: [PATCH 31/57] PCI: MIPS: adds rt2880 pci support - -Add support for the pci found on the rt2880 SoC. - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - arch/mips/pci/Makefile | 1 + - arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++ - arch/mips/ralink/Kconfig | 1 + - 3 files changed, 283 insertions(+) - create mode 100644 arch/mips/pci/pci-rt2880.c - ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops - obj-$(CONFIG_LANTIQ) += fixup-lantiq.o - obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o - obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o -+obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o ---- /dev/null -+++ b/arch/mips/pci/pci-rt2880.c -@@ -0,0 +1,281 @@ -+/* -+ * Ralink RT288x SoC PCI register definitions -+ * -+ * Copyright (C) 2009 John Crispin <blogic@openwrt.org> -+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> -+ * -+ * Parts of this file are based on Ralink's 2.6.21 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include <linux/types.h> -+#include <linux/pci.h> -+#include <linux/io.h> -+#include <linux/init.h> -+#include <linux/module.h> -+#include <linux/of_platform.h> -+#include <linux/of_irq.h> -+#include <linux/of_pci.h> -+ -+#include <asm/mach-ralink/rt288x.h> -+ -+#define RT2880_PCI_BASE 0x00440000 -+#define RT288X_CPU_IRQ_PCI 4 -+ -+#define RT2880_PCI_MEM_BASE 0x20000000 -+#define RT2880_PCI_MEM_SIZE 0x10000000 -+#define RT2880_PCI_IO_BASE 0x00460000 -+#define RT2880_PCI_IO_SIZE 0x00010000 -+ -+#define RT2880_PCI_REG_PCICFG_ADDR 0x00 -+#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c -+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 -+#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 -+#define RT2880_PCI_REG_CONFIG_ADDR 0x20 -+#define RT2880_PCI_REG_CONFIG_DATA 0x24 -+#define RT2880_PCI_REG_MEMBASE 0x28 -+#define RT2880_PCI_REG_IOBASE 0x2c -+#define RT2880_PCI_REG_ID 0x30 -+#define RT2880_PCI_REG_CLASS 0x34 -+#define RT2880_PCI_REG_SUBID 0x38 -+#define RT2880_PCI_REG_ARBCTL 0x80 -+ -+static void __iomem *rt2880_pci_base; -+static DEFINE_SPINLOCK(rt2880_pci_lock); -+ -+static u32 rt2880_pci_reg_read(u32 reg) -+{ -+ return readl(rt2880_pci_base + reg); -+} -+ -+static void rt2880_pci_reg_write(u32 val, u32 reg) -+{ -+ writel(val, rt2880_pci_base + reg); -+} -+ -+static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, -+ unsigned int func, unsigned int where) -+{ -+ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | -+ 0x80000000); -+} -+ -+static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *val) -+{ -+ unsigned long flags; -+ u32 address; -+ u32 data; -+ -+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), -+ PCI_FUNC(devfn), where); -+ -+ spin_lock_irqsave(&rt2880_pci_lock, flags); -+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); -+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); -+ spin_unlock_irqrestore(&rt2880_pci_lock, flags); -+ -+ switch (size) { -+ case 1: -+ *val = (data >> ((where & 3) << 3)) & 0xff; -+ break; -+ case 2: -+ *val = (data >> ((where & 3) << 3)) & 0xffff; -+ break; -+ case 4: -+ *val = data; -+ break; -+ } -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 val) -+{ -+ unsigned long flags; -+ u32 address; -+ u32 data; -+ -+ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), -+ PCI_FUNC(devfn), where); -+ -+ spin_lock_irqsave(&rt2880_pci_lock, flags); -+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); -+ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); -+ -+ switch (size) { -+ case 1: -+ data = (data & ~(0xff << ((where & 3) << 3))) | -+ (val << ((where & 3) << 3)); -+ break; -+ case 2: -+ data = (data & ~(0xffff << ((where & 3) << 3))) | -+ (val << ((where & 3) << 3)); -+ break; -+ case 4: -+ data = val; -+ break; -+ } -+ -+ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA); -+ spin_unlock_irqrestore(&rt2880_pci_lock, flags); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static struct pci_ops rt2880_pci_ops = { -+ .read = rt2880_pci_config_read, -+ .write = rt2880_pci_config_write, -+}; -+ -+static struct resource rt2880_pci_mem_resource = { -+ .name = "PCI MEM space", -+ .start = RT2880_PCI_MEM_BASE, -+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource rt2880_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = RT2880_PCI_IO_BASE, -+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct pci_controller rt2880_pci_controller = { -+ .pci_ops = &rt2880_pci_ops, -+ .mem_resource = &rt2880_pci_mem_resource, -+ .io_resource = &rt2880_pci_io_resource, -+}; -+ -+static inline u32 rt2880_pci_read_u32(unsigned long reg) -+{ -+ unsigned long flags; -+ u32 address; -+ u32 ret; -+ -+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); -+ -+ spin_lock_irqsave(&rt2880_pci_lock, flags); -+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); -+ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); -+ spin_unlock_irqrestore(&rt2880_pci_lock, flags); -+ -+ return ret; -+} -+ -+static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) -+{ -+ unsigned long flags; -+ u32 address; -+ -+ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); -+ -+ spin_lock_irqsave(&rt2880_pci_lock, flags); -+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); -+ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); -+ spin_unlock_irqrestore(&rt2880_pci_lock, flags); -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ u16 cmd; -+ int irq = -1; -+ -+ if (dev->bus->number != 0) -+ return irq; -+ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 0x00: -+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); -+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); -+ break; -+ case 0x11: -+ irq = RT288X_CPU_IRQ_PCI; -+ break; -+ default: -+ printk("%s:%s[%d] trying to alloc unknown pci irq\n", -+ __FILE__, __func__, __LINE__); -+ BUG(); -+ break; -+ } -+ -+ pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14); -+ pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF); -+ pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | -+ PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY; -+ pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd); -+ pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, -+ dev->irq); -+ return irq; -+} -+ -+static int rt288x_pci_probe(struct platform_device *pdev) -+{ -+ void __iomem *io_map_base; -+ int i; -+ -+ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE); -+ -+ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE); -+ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base; -+ set_io_port_base((unsigned long) io_map_base); -+ -+ ioport_resource.start = RT2880_PCI_IO_BASE; -+ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1; -+ -+ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); -+ for(i = 0; i < 0xfffff; i++) {} -+ -+ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); -+ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); -+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); -+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); -+ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); -+ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); -+ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); -+ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); -+ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); -+ -+ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); -+ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); -+ -+ register_pci_controller(&rt2880_pci_controller); -+ return 0; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ return 0; -+} -+ -+static const struct of_device_id rt288x_pci_match[] = { -+ { .compatible = "ralink,rt288x-pci" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rt288x_pci_match); -+ -+static struct platform_driver rt288x_pci_driver = { -+ .probe = rt288x_pci_probe, -+ .driver = { -+ .name = "rt288x-pci", -+ .owner = THIS_MODULE, -+ .of_match_table = rt288x_pci_match, -+ }, -+}; -+ -+int __init pcibios_init(void) -+{ -+ int ret = platform_driver_register(&rt288x_pci_driver); -+ if (ret) -+ pr_info("rt288x-pci: Error registering platform driver!"); -+ return ret; -+} -+ -+arch_initcall(pcibios_init); ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -31,6 +31,7 @@ choice - config SOC_RT288X - bool "RT288x" - select MIPS_L1_CACHE_SHIFT_4 -+ select HW_HAS_PCI - - config SOC_RT305X - bool "RT305x" diff --git a/target/linux/ramips/patches-3.18/0038-USB-add-OHCI-EHCI-OF-binding.patch b/target/linux/ramips/patches-3.18/0038-USB-add-OHCI-EHCI-OF-binding.patch deleted file mode 100644 index a5fb5aba44..0000000000 --- a/target/linux/ramips/patches-3.18/0038-USB-add-OHCI-EHCI-OF-binding.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ffb27de4760595c356ef619c97f25722c8db28e7 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 09:49:07 +0100 -Subject: [PATCH 38/57] USB: add OHCI/EHCI OF binding - -based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963 - -Signed-off-by: John Crispin <blogic@openwrt.org> ---- - drivers/usb/Makefile | 3 ++- - drivers/usb/host/ehci-platform.c | 21 +++++++++++++++++---- - drivers/usb/host/ohci-platform.c | 37 +++++++++++++++++++++++++++++++------ - 3 files changed, 50 insertions(+), 11 deletions(-) - ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -359,6 +359,7 @@ static int ehci_platform_resume(struct d - static const struct of_device_id vt8500_ehci_ids[] = { - { .compatible = "via,vt8500-ehci", }, - { .compatible = "wm,prizm-ehci", }, -+ { .compatible = "ralink,rt3xxx-ehci", }, - { .compatible = "generic-ehci", }, - {} - }; ---- a/drivers/usb/host/ohci-platform.c -+++ b/drivers/usb/host/ohci-platform.c -@@ -342,6 +342,7 @@ static int ohci_platform_resume(struct d - #endif /* CONFIG_PM */ - - static const struct of_device_id ohci_platform_ids[] = { -+ { .compatible = "ralink,rt3xxx-ohci", }, - { .compatible = "generic-ohci", }, - { } - }; diff --git a/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch deleted file mode 100644 index 2e81e456d3..0000000000 --- a/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch +++ /dev/null @@ -1,154 +0,0 @@ ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -19,6 +19,7 @@ - #include <linux/errno.h> - #include <linux/module.h> - #include <linux/device.h> -+#include <linux/of.h> - - #include <linux/mtd/mtd.h> - #include <linux/mtd/partitions.h> -@@ -32,6 +33,7 @@ struct m25p { - struct spi_device *spi; - struct spi_nor spi_nor; - struct mtd_info mtd; -+ u16 chunk_size; - u8 command[MAX_CMD_SIZE]; - }; - -@@ -117,25 +119,14 @@ static inline unsigned int m25p80_rx_nbi - } - } - --/* -- * Read an address range from the nor chip. The address range -- * may be any size provided it is within the physical boundaries. -- */ --static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, -- size_t *retlen, u_char *buf) -+static int __m25p80_read(struct spi_nor *nor, loff_t from, size_t len, -+ size_t *retlen, u_char *buf) - { - struct m25p *flash = nor->priv; - struct spi_device *spi = flash->spi; - struct spi_transfer t[2]; - struct spi_message m; - int dummy = nor->read_dummy; -- int ret; -- -- /* Wait till previous write/erase is done. */ -- ret = nor->wait_till_ready(nor); -- if (ret) -- return ret; -- - spi_message_init(&m); - memset(t, 0, (sizeof t)); - -@@ -156,6 +147,84 @@ static int m25p80_read(struct spi_nor *n - *retlen = m.actual_length - m25p_cmdsz(nor) - dummy; - return 0; - } -+/* -+ * Read an address range from the nor chip. The address range -+ * may be any size provided it is within the physical boundaries. -+ */ -+static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, -+ size_t *retlen, u_char *buf) -+{ -+ int ret; -+ -+ /* Wait till previous write/erase is done. */ -+ ret = nor->wait_till_ready(nor); -+ if (ret) -+ return ret; -+ -+ return __m25p80_read(nor, from, len, retlen, buf); -+} -+ -+ -+static void m25p80_chunked_write(struct spi_nor *nor, loff_t _from, size_t _len, -+ size_t *_retlen, const u_char *_buf) -+{ -+ struct m25p *flash = nor->priv; -+ int chunk_size; -+ int retlen = 0; -+ -+ chunk_size = flash->chunk_size; -+ if (!chunk_size) -+ chunk_size = _len; -+ -+ if (nor->addr_width > 3) -+ chunk_size -= nor->addr_width - 3; -+ -+ while (retlen < _len) { -+ size_t len = min_t(int, chunk_size, _len - retlen); -+ const u_char *buf = _buf + retlen; -+ loff_t from = _from + retlen; -+ -+ nor->wait_till_ready(nor); -+ nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); -+ -+ m25p80_write(nor, from, len, &retlen, buf); -+ } -+ *_retlen += retlen; -+} -+ -+static int m25p80_chunked_read(struct spi_nor *nor, loff_t _from, size_t _len, -+ size_t *_retlen, u_char *_buf) -+{ -+ struct m25p *flash = nor->priv; -+ int chunk_size; -+ int ret; -+ -+ /* Wait till previous write/erase is done. */ -+ ret = nor->wait_till_ready(nor); -+ if (ret) -+ return ret; -+ -+ chunk_size = flash->chunk_size; -+ if (!chunk_size) -+ chunk_size = _len; -+ -+ *_retlen = 0; -+ -+ while (*_retlen < _len) { -+ size_t len = min_t(int, chunk_size, _len - *_retlen); -+ u_char *buf = _buf + *_retlen; -+ loff_t from = _from + *_retlen; -+ int retlen = 0; -+ int ret = __m25p80_read(nor, from, len, &retlen, buf); -+ -+ if (ret) -+ return ret; -+ -+ *_retlen += retlen; -+ } -+ -+ return 0; -+} - - static int m25p80_erase(struct spi_nor *nor, loff_t offset) - { -@@ -197,6 +266,7 @@ static int m25p_probe(struct spi_device - struct spi_nor *nor; - enum read_mode mode = SPI_NOR_NORMAL; - char *flash_name = NULL; -+ u32 val; - int ret; - - data = dev_get_platdata(&spi->dev); -@@ -244,6 +314,14 @@ static int m25p_probe(struct spi_device - if (ret) - return ret; - -+ if (spi->dev.of_node && -+ !of_property_read_u32(spi->dev.of_node, "m25p,chunked-io", &val)) { -+ dev_warn(&spi->dev, "using chunked io\n"); -+ nor->read = m25p80_chunked_read; -+ nor->write = m25p80_chunked_write; -+ flash->chunk_size = val; -+ } -+ - ppdata.of_node = spi->dev.of_node; - - return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, diff --git a/target/linux/ramips/patches-3.18/0059-USB-fix-dwc2.patch b/target/linux/ramips/patches-3.18/0059-USB-fix-dwc2.patch deleted file mode 100644 index 92e4dc00b1..0000000000 --- a/target/linux/ramips/patches-3.18/0059-USB-fix-dwc2.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/drivers/usb/dwc2/hcd.c -+++ b/drivers/usb/dwc2/hcd.c -@@ -47,6 +47,7 @@ - #include <linux/io.h> - #include <linux/slab.h> - #include <linux/usb.h> -+#include <linux/reset.h> - - #include <linux/usb/hcd.h> - #include <linux/usb/ch11.h> -@@ -2780,6 +2781,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso - - dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); - -+ device_reset(hsotg->dev); -+ - /* Detect config values from hardware */ - retval = dwc2_get_hwparams(hsotg); - diff --git a/target/linux/ramips/patches-3.18/0063-cevt-rt3352.patch b/target/linux/ramips/patches-3.18/0063-cevt-rt3352.patch deleted file mode 100644 index 749701f2e5..0000000000 --- a/target/linux/ramips/patches-3.18/0063-cevt-rt3352.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/ralink/cevt-rt3352.c -+++ b/arch/mips/ralink/cevt-rt3352.c -@@ -54,7 +54,7 @@ static int systick_next_event(unsigned l - sdev = container_of(evt, struct systick_device, dev); - count = ioread32(sdev->membase + SYSTICK_COUNT); - count = (count + delta) % SYSTICK_FREQ; -- iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE); -+ iowrite32(count, sdev->membase + SYSTICK_COMPARE); - - return 0; - } diff --git a/target/linux/ramips/patches-3.18/0064-MIPS-ralink-fix-clearing-the-illegal-access-interrup.patch b/target/linux/ramips/patches-3.18/0064-MIPS-ralink-fix-clearing-the-illegal-access-interrup.patch deleted file mode 100644 index 8153272308..0000000000 --- a/target/linux/ramips/patches-3.18/0064-MIPS-ralink-fix-clearing-the-illegal-access-interrup.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f5d9bea58b576b50cdc0d7a607646b0849ff79c4 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Mon, 25 May 2015 16:51:34 +0200 -Subject: [PATCH] MIPS: ralink: fix clearing the illegal access interrupt - -Due to a typo the illegal access interrupt is never cleared in by -the interupt handler, causing an effective deadlock on the first -illegal access. - -This was broken since the code was introduced in 5433acd81e87 ("MIPS: -ralink: add illegal access driver"), but only exposed when the Kconfig -symbol was added, thus enabling the code. - -Cc: <stable@vger.kernel.org> [3.18+] -Fixes: a7b7aad383c ("MIPS: ralink: add missing symbol for RALINK_ILL_ACC") -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/ralink/ill_acc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/ralink/ill_acc.c -+++ b/arch/mips/ralink/ill_acc.c -@@ -41,7 +41,7 @@ static irqreturn_t ill_acc_irq_handler(i - addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M, - type & ILL_ACC_LEN_M); - -- rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE); -+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE); - - return IRQ_HANDLED; - } diff --git a/target/linux/ramips/patches-3.18/0065-fix_dts_cache_issues.patch b/target/linux/ramips/patches-3.18/0065-fix_dts_cache_issues.patch deleted file mode 100644 index 520c570ee2..0000000000 --- a/target/linux/ramips/patches-3.18/0065-fix_dts_cache_issues.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -675,7 +675,6 @@ static void __init arch_mem_init(char ** - crashk_res.end - crashk_res.start + 1, - BOOTMEM_DEFAULT); - #endif -- device_tree_init(); - sparse_init(); - plat_swiotlb_setup(); - paging_init(); -@@ -784,6 +783,7 @@ void __init setup_arch(char **cmdline_p) - prefill_possible_map(); - - cpu_cache_init(); -+ device_tree_init(); - } - - unsigned long kernelsp[NR_CPUS]; diff --git a/target/linux/ramips/patches-3.18/0067-disable_illacc.patch b/target/linux/ramips/patches-3.18/0067-disable_illacc.patch deleted file mode 100644 index 590b501bf2..0000000000 --- a/target/linux/ramips/patches-3.18/0067-disable_illacc.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -13,9 +13,9 @@ config CLKEVT_RT3352 - select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC -- bool -+ bool "illegal access irq" - depends on SOC_RT305X -- default y -+ default n - - config IRQ_INTC - bool diff --git a/target/linux/ramips/patches-3.18/0068-non-pci-mt7620.patch b/target/linux/ramips/patches-3.18/0068-non-pci-mt7620.patch deleted file mode 100644 index ce56ae2002..0000000000 --- a/target/linux/ramips/patches-3.18/0068-non-pci-mt7620.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -513,9 +513,6 @@ void prom_soc_init(struct ralink_soc_inf - ralink_soc = MT762X_SOC_MT7620N; - name = "MT7620N"; - soc_info->compatible = "ralink,mt7620n-soc"; --#ifdef CONFIG_PCI -- panic("mt7620n is only supported for non pci kernels"); --#endif - } - } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - ralink_soc = MT762X_SOC_MT7628AN; diff --git a/target/linux/ramips/patches-3.18/0069-no-pm_poweroff.patch b/target/linux/ramips/patches-3.18/0069-no-pm_poweroff.patch deleted file mode 100644 index fedfe37154..0000000000 --- a/target/linux/ramips/patches-3.18/0069-no-pm_poweroff.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/mips/ralink/reset.c -+++ b/arch/mips/ralink/reset.c -@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void - { - _machine_restart = ralink_restart; - _machine_halt = ralink_halt; -- pm_power_off = ralink_halt; - - return 0; - } diff --git a/target/linux/ramips/patches-3.18/0072-mt7621-add-highmem.patch b/target/linux/ramips/patches-3.18/0072-mt7621-add-highmem.patch deleted file mode 100644 index 0a98151113..0000000000 --- a/target/linux/ramips/patches-3.18/0072-mt7621-add-highmem.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -51,6 +51,7 @@ choice - select SYS_SUPPORTS_MULTITHREADING - select SYS_SUPPORTS_SMP - select SYS_SUPPORTS_MIPS_CMP -+ select SYS_SUPPORTS_HIGHMEM - select IRQ_GIC - select HW_HAS_PCI - diff --git a/target/linux/ramips/patches-3.18/0301-mt7688-detect.patch b/target/linux/ramips/patches-3.18/0301-mt7688-detect.patch deleted file mode 100644 index 1fddf11dc3..0000000000 --- a/target/linux/ramips/patches-3.18/0301-mt7688-detect.patch +++ /dev/null @@ -1,114 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -17,6 +17,7 @@ - - #define SYSC_REG_CHIP_NAME0 0x00 - #define SYSC_REG_CHIP_NAME1 0x04 -+#define SYSC_REG_EFUSE_CFG 0x08 - #define SYSC_REG_CHIP_REV 0x0c - #define SYSC_REG_SYSTEM_CONFIG0 0x10 - #define SYSC_REG_SYSTEM_CONFIG1 0x14 ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -43,6 +43,9 @@ - #define CLKCFG_FFRAC_MASK 0x001f - #define CLKCFG_FFRAC_USB_VAL 0x0003 - -+/* EFUSE bits */ -+#define EFUSE_MT7688 0x100000 -+ - /* does the board have sdram or ddram */ - static int dram_type; - -@@ -391,7 +394,7 @@ void __init ralink_clk_init(void) - #define RINT(x) ((x) / 1000000) - #define RFRAC(x) (((x) / 1000) % 1000) - -- if (ralink_soc == MT762X_SOC_MT7628AN) { -+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { - if (xtal_rate == MHZ(40)) - cpu_rate = MHZ(580); - else -@@ -436,7 +439,8 @@ void __init ralink_clk_init(void) - ralink_clk_add("10000e00.uart2", periph_rate); - ralink_clk_add("10180000.wmac", xtal_rate); - -- if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) { -+ if (IS_ENABLED(CONFIG_USB) && -+ (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) { - /* - * When the CPU goes into sleep mode, the BUS clock will be too low for - * USB to function properly -@@ -533,8 +537,15 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->compatible = "ralink,mt7620n-soc"; - } - } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { -- ralink_soc = MT762X_SOC_MT7628AN; -- name = "MT7628AN"; -+ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); -+ -+ if (efuse & EFUSE_MT7688) { -+ ralink_soc = MT762X_SOC_MT7688; -+ name = "MT7688"; -+ } else { -+ ralink_soc = MT762X_SOC_MT7628AN; -+ name = "MT7628AN"; -+ } - soc_info->compatible = "ralink,mt7628an-soc"; - } else { - panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); -@@ -548,13 +559,13 @@ void prom_soc_init(struct ralink_soc_inf - - cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); - -- if (ralink_soc == MT762X_SOC_MT7628AN) -+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) - dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628; - else - dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; - - soc_info->mem_base = MT7620_DRAM_BASE; -- if (ralink_soc == MT762X_SOC_MT7628AN) -+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) - mt7628_dram_init(soc_info); - else - mt7620_dram_init(soc_info); -@@ -567,7 +578,7 @@ void prom_soc_init(struct ralink_soc_inf - pr_info("Digital PMU set to %s control\n", - (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - -- if (ralink_soc == MT762X_SOC_MT7628AN) -+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) - rt2880_pinmux_data = mt7628an_pinmux_data; - else - rt2880_pinmux_data = mt7620a_pinmux_data; ---- a/arch/mips/include/asm/mach-ralink/ralink_regs.h -+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h -@@ -24,6 +24,7 @@ enum ralink_soc_type { - MT762X_SOC_MT7620N, - MT762X_SOC_MT7621AT, - MT762X_SOC_MT7628AN, -+ MT762X_SOC_MT7688, - }; - extern enum ralink_soc_type ralink_soc; - ---- a/drivers/net/ethernet/ralink/esw_rt3052.c -+++ b/drivers/net/ethernet/ralink/esw_rt3052.c -@@ -611,7 +611,7 @@ static void esw_hw_init(struct rt305x_es - rt305x_mii_write(esw, 0, 29, 0x598b); - /* select local register */ - rt305x_mii_write(esw, 0, 31, 0x8000); -- } else if (ralink_soc == MT762X_SOC_MT7628AN) { -+ } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { - int i; - // u32 phy_val; - u32 val; -@@ -1042,7 +1042,7 @@ esw_get_port_tr_badgood(struct switch_de - int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; - u32 reg; - -- if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN)) -+ if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688)) - return -EINVAL; - - if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) diff --git a/target/linux/ramips/patches-3.18/0302-mt762x-vendor-id.patch b/target/linux/ramips/patches-3.18/0302-mt762x-vendor-id.patch deleted file mode 100644 index ca56f5cb49..0000000000 --- a/target/linux/ramips/patches-3.18/0302-mt762x-vendor-id.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -552,7 +552,7 @@ void prom_soc_init(struct ralink_soc_inf - } - - snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, -- "Ralink %s ver:%u eco:%u", -+ "MediaTek %s ver:%u eco:%u", - name, - (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, - (rev & CHIP_REV_ECO_MASK)); ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -185,7 +185,7 @@ void prom_soc_init(struct ralink_soc_inf - rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); - - snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, -- "Mediatek %s ver:%u eco:%u", -+ "MediaTek %s ver:%u eco:%u", - name, - (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, - (rev & CHIP_REV_ECO_MASK)); diff --git a/target/linux/ramips/patches-3.18/0304-baud_250000.patch b/target/linux/ramips/patches-3.18/0304-baud_250000.patch deleted file mode 100644 index 6a364c06c6..0000000000 --- a/target/linux/ramips/patches-3.18/0304-baud_250000.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/drivers/tty/serial/serial_core.c -+++ b/drivers/tty/serial/serial_core.c -@@ -356,6 +356,9 @@ uart_get_baud_rate(struct uart_port *por - else if (flags == UPF_SPD_WARP) - altbaud = 460800; - -+ if (tty_termios_baud_rate(termios) == 2500000) -+ return 250000; -+ - for (try = 0; try < 2; try++) { - baud = tty_termios_baud_rate(termios); - diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch index 23d32681bf..504c572b52 100644 --- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch +++ b/target/linux/ramips/patches-4.3/0001-arch-mips-ralink-add-mt7621-support.patch @@ -1,27 +1,30 @@ -From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001 +From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> -Date: Sun, 27 Jul 2014 10:57:40 +0100 -Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support +Date: Mon, 7 Dec 2015 17:08:31 +0100 +Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support Signed-off-by: John Crispin <blogic@openwrt.org> --- - arch/mips/include/asm/gic.h | 4 + arch/mips/include/asm/mach-ralink/irq.h | 9 + arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++ + arch/mips/kernel/mips-cm.c | 4 +- arch/mips/kernel/vmlinux.lds.S | 1 + arch/mips/ralink/Kconfig | 18 ++ arch/mips/ralink/Makefile | 7 +- arch/mips/ralink/Platform | 5 + - arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++ + arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++ arch/mips/ralink/malta-amon.c | 81 +++++++++ - arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++ - 10 files changed, 617 insertions(+), 1 deletion(-) + arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++ + 10 files changed, 638 insertions(+), 3 deletions(-) create mode 100644 arch/mips/include/asm/mach-ralink/irq.h create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h create mode 100644 arch/mips/ralink/irq-gic.c create mode 100644 arch/mips/ralink/malta-amon.c create mode 100644 arch/mips/ralink/mt7621.c +diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h +new file mode 100644 +index 0000000..4321865 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/irq.h @@ -0,0 +1,9 @@ @@ -34,6 +37,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#include_next <irq.h> + +#endif +diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h +new file mode 100644 +index 0000000..21c8dc2 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -0,0 +1,39 @@ @@ -76,6 +82,30 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) + +#endif +diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c +index b8ceee5..b97de1d 100644 +--- a/arch/mips/kernel/mips-cm.c ++++ b/arch/mips/kernel/mips-cm.c +@@ -232,7 +232,7 @@ int mips_cm_probe(void) + write_gcr_base(base_reg); + + /* disable CM regions */ +- write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); ++/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); +@@ -240,7 +240,7 @@ int mips_cm_probe(void) + write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); + write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK); + write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); +- ++*/ + /* probe for an L2-only sync region */ + mips_cm_probe_l2sync(); + +diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S +index 07d32a4..86c6284 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -51,6 +51,7 @@ SECTIONS @@ -86,6 +116,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> TEXT_TEXT SCHED_TEXT LOCK_TEXT +diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig +index e9bc8c9..d078e61 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -12,6 +12,11 @@ config RALINK_ILL_ACC @@ -100,9 +132,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> choice prompt "Ralink SoC selection" default SOC_RT305X -@@ -33,6 +38,15 @@ choice +@@ -34,6 +39,15 @@ choice config SOC_MT7620 - bool "MT7620" + bool "MT7620/8" + config SOC_MT7621 + bool "MT7621" @@ -116,7 +148,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> endchoice choice -@@ -64,6 +78,10 @@ choice +@@ -65,6 +79,10 @@ choice depends on SOC_MT7620 select BUILTIN_DTB @@ -127,6 +159,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> endchoice endif +diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile +index a6c9d00..ca501db 100644 --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile @@ -6,16 +6,21 @@ @@ -152,9 +186,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform +index 6d9c8c4..6095fcc 100644 --- a/arch/mips/ralink/Platform +++ b/arch/mips/ralink/Platform -@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr +@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt # load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620 @@ -163,6 +199,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +# +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621 +diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c +new file mode 100644 +index 0000000..f1c541b --- /dev/null +++ b/arch/mips/ralink/irq-gic.c @@ -0,0 +1,268 @@ @@ -434,6 +473,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +{ + of_irq_init(of_irq_ids); +} +diff --git a/arch/mips/ralink/malta-amon.c b/arch/mips/ralink/malta-amon.c +new file mode 100644 +index 0000000..1e47844 --- /dev/null +++ b/arch/mips/ralink/malta-amon.c @@ -0,0 +1,81 @@ @@ -518,6 +560,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + smp_rmb(); /* Target will be updating flags soon */ + pr_debug("launch: cpu%d gone!\n", cpu); +} +diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c +new file mode 100644 +index 0000000..c28743b --- /dev/null +++ b/arch/mips/ralink/mt7621.c @@ -0,0 +1,209 @@ @@ -708,7 +753,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); + + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, -+ "Mediatek %s ver:%u eco:%u", ++ "MediaTek %s ver:%u eco:%u", + name, + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, + (rev & CHIP_REV_ECO_MASK)); @@ -730,23 +775,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + if (!register_vsmp_smp_ops()) + return; +} ---- a/arch/mips/kernel/mips-cm.c -+++ b/arch/mips/kernel/mips-cm.c -@@ -105,7 +105,7 @@ int mips_cm_probe(void) - write_gcr_base(base_reg); - - /* disable CM regions */ -- write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); -+/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK); - write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); - write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK); - write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); -@@ -113,7 +113,7 @@ int mips_cm_probe(void) - write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); - write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK); - write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK); -- -+*/ - /* probe for an L2-only sync region */ - mips_cm_probe_l2sync(); - +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0013-MIPS-ralink-add-MT7621-defconfig.patch b/target/linux/ramips/patches-4.3/0002-MIPS-ralink-add-MT7621-defconfig.patch index daf27c168d..3bb7e2f2e4 100644 --- a/target/linux/ramips/patches-3.18/0013-MIPS-ralink-add-MT7621-defconfig.patch +++ b/target/linux/ramips/patches-4.3/0002-MIPS-ralink-add-MT7621-defconfig.patch @@ -1,7 +1,7 @@ -From 8f92eac5ace0f834ec069b4bb8e9ad38f162de0e Mon Sep 17 00:00:00 2001 +From c96f2cc4d5f6e1bb11f3e7e04a7e21503a214d7c Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 27 Jan 2014 13:12:41 +0000 -Subject: [PATCH 13/57] MIPS: ralink: add MT7621 defconfig +Subject: [PATCH 02/53] MIPS: ralink: add MT7621 defconfig Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -9,6 +9,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> 1 file changed, 197 insertions(+) create mode 100644 arch/mips/configs/mt7621_defconfig +diff --git a/arch/mips/configs/mt7621_defconfig b/arch/mips/configs/mt7621_defconfig +new file mode 100644 +index 0000000..7719471 --- /dev/null +++ b/arch/mips/configs/mt7621_defconfig @@ -0,0 +1,197 @@ @@ -209,3 +212,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +CONFIG_CRC32_SARWATE=y +# CONFIG_XZ_DEC_X86 is not set +CONFIG_AVERAGE=y +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0003-MIPS-ralink-cleanup-early_printk.patch b/target/linux/ramips/patches-4.3/0003-MIPS-ralink-cleanup-early_printk.patch new file mode 100644 index 0000000000..e2b2ba5e00 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0003-MIPS-ralink-cleanup-early_printk.patch @@ -0,0 +1,66 @@ +From 4d805af8246efdc330d6af9a8bd10ce892327598 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Fri, 24 Jan 2014 17:01:17 +0100 +Subject: [PATCH 03/53] MIPS: ralink: cleanup early_printk + +Add support for the new MT7621/8 SoC and kill ifdefs. +Cleanup some whitespace error while we are at it. + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/early_printk.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c +index 255d695..c04ee53 100644 +--- a/arch/mips/ralink/early_printk.c ++++ b/arch/mips/ralink/early_printk.c +@@ -25,11 +25,13 @@ + #define MT7628_CHIP_NAME1 0x20203832 + + #define UART_REG_TX 0x04 ++#define UART_REG_LCR 0x0c + #define UART_REG_LSR 0x14 + #define UART_REG_LSR_RT2880 0x1c + + static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); + static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); ++static int init_complete; + + static inline void uart_w32(u32 val, unsigned reg) + { +@@ -47,8 +49,31 @@ static inline int soc_is_mt7628(void) + (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); + } + ++static inline void find_uart_base(void) ++{ ++ int i; ++ ++ if (!soc_is_mt7628()) ++ return; ++ ++ for (i = 0; i < 3; i++) { ++ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); ++ ++ if (!reg) ++ continue; ++ ++ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i)); ++ break; ++ } ++} ++ + void prom_putchar(unsigned char ch) + { ++ if (!init_complete) { ++ find_uart_base(); ++ init_complete = 1; ++ } ++ + if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { + uart_w32(ch, UART_TX); + while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0016-MIPS-ralink-add-MT7621-pcie-driver.patch b/target/linux/ramips/patches-4.3/0004-MIPS-ralink-add-MT7621-pcie-driver.patch index 2154e8a319..b605c5efda 100644 --- a/target/linux/ramips/patches-3.18/0016-MIPS-ralink-add-MT7621-pcie-driver.patch +++ b/target/linux/ramips/patches-4.3/0004-MIPS-ralink-add-MT7621-pcie-driver.patch @@ -1,25 +1,25 @@ -From 95d7eb13a864ef666cea7f0e86349e86d80d28ce Mon Sep 17 00:00:00 2001 +From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 16 Mar 2014 05:22:39 +0000 -Subject: [PATCH 16/57] MIPS: ralink: add MT7621 pcie driver +Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver Signed-off-by: John Crispin <blogic@openwrt.org> --- arch/mips/pci/Makefile | 1 + - arch/mips/pci/pci-mt7621.c | 797 ++++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 798 insertions(+) + arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 814 insertions(+) create mode 100644 arch/mips/pci/pci-mt7621.c --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile -@@ -42,6 +42,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1 +@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o --- /dev/null +++ b/arch/mips/pci/pci-mt7621.c @@ -0,0 +1,813 @@ @@ -97,12 +97,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + +#define RALINK_PCI_CONFIG_ADDR 0x20 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 -+#define SURFBOARDINT_PCIE0 12 /* PCIE0 */ ++#define SURFBOARDINT_PCIE0 11 /* PCIE0 */ +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2 -+#define SURFBOARDINT_PCIE1 32 /* PCIE1 */ -+#define SURFBOARDINT_PCIE2 33 /* PCIE2 */ ++#define SURFBOARDINT_PCIE1 31 /* PCIE1 */ ++#define SURFBOARDINT_PCIE2 32 /* PCIE2 */ +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) +#define RALINK_PCIE0_RST (1<<24) diff --git a/target/linux/ramips/patches-4.3/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-4.3/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch new file mode 100644 index 0000000000..fe918e6fd3 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch @@ -0,0 +1,88 @@ +From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 14 Jul 2013 23:08:11 +0200 +Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k + irq + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/Kconfig | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig +index d078e61..c2778f2 100644 +--- a/arch/mips/ralink/Kconfig ++++ b/arch/mips/ralink/Kconfig +@@ -1,11 +1,16 @@ + if RALINK + ++config CEVT_SYSTICK_QUIRK ++ bool ++ default n ++ + config CLKEVT_RT3352 + bool + depends on SOC_RT305X || SOC_MT7620 + default y + select CLKSRC_OF + select CLKSRC_MMIO ++ select CEVT_SYSTICK_QUIRK + + config RALINK_ILL_ACC + bool +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -15,6 +15,26 @@ + #include <asm/time.h> + #include <asm/cevt-r4k.h> + ++static int mips_state_oneshot(struct clock_event_device *evt) ++{ ++ if (!cp0_timer_irq_installed) { ++ cp0_timer_irq_installed = 1; ++ setup_irq(evt->irq, &c0_compare_irqaction); ++ } ++ ++ return 0; ++} ++ ++static int mips_state_shutdown(struct clock_event_device *evt) ++{ ++ if (cp0_timer_irq_installed) { ++ cp0_timer_irq_installed = 0; ++ remove_irq(evt->irq, &c0_compare_irqaction); ++ } ++ ++ return 0; ++} ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -208,18 +228,21 @@ + cd->rating = 300; + cd->irq = irq; + cd->cpumask = cpumask_of(cpu); ++ cd->set_state_shutdown = mips_state_shutdown; ++ cd->set_state_oneshot = mips_state_oneshot; + cd->set_next_event = mips_next_event; + cd->event_handler = mips_event_handler; + + clockevents_register_device(cd); + ++#ifndef CONFIG_CEVT_SYSTICK_QUIRK + if (cp0_timer_irq_installed) + return 0; + + cp0_timer_irq_installed = 1; + + setup_irq(irq, &c0_compare_irqaction); +- ++#endif + return 0; + } + +-- +1.7.10.4 + + diff --git a/target/linux/ramips/patches-3.18/0021-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-4.3/0006-MIPS-ralink-add-cpu-frequency-scaling.patch index 0e567cb2f0..afdc65a3c8 100644 --- a/target/linux/ramips/patches-3.18/0021-MIPS-ralink-add-cpu-frequency-scaling.patch +++ b/target/linux/ramips/patches-4.3/0006-MIPS-ralink-add-cpu-frequency-scaling.patch @@ -1,16 +1,18 @@ -From e76ecd496c9b074ab21b17f12494d823a407e89a Mon Sep 17 00:00:00 2001 +From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 28 Jul 2013 16:26:41 +0200 -Subject: [PATCH 21/57] MIPS: ralink: add cpu frequency scaling +Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling This feature will break udelay() and cause the delay loop to have longer delays when the frequency is scaled causing a performance hit. Signed-off-by: John Crispin <blogic@openwrt.org> --- - arch/mips/ralink/cevt-rt3352.c | 36 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) + arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) +diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c +index a8e70a9..b36888c 100644 --- a/arch/mips/ralink/cevt-rt3352.c +++ b/arch/mips/ralink/cevt-rt3352.c @@ -29,6 +29,10 @@ @@ -24,18 +26,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org> struct systick_device { void __iomem *membase; struct clock_event_device dev; -@@ -36,6 +40,8 @@ struct systick_device { +@@ -36,9 +40,26 @@ struct systick_device { int freq_scale; }; +static void (*systick_freq_scaling)(struct systick_device *sdev, int status); + - static void systick_set_clock_mode(enum clock_event_mode mode, - struct clock_event_device *evt); - -@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio - .dev_id = &systick.dev, - }; + static int systick_set_oneshot(struct clock_event_device *evt); + static int systick_shutdown(struct clock_event_device *evt); +static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) +{ @@ -52,25 +50,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG); +} + - static void systick_set_clock_mode(enum clock_event_mode mode, + static int systick_next_event(unsigned long delta, struct clock_event_device *evt) { -@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum - sdev->irq_requested = 1; - iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, - systick.membase + SYSTICK_CONFIG); -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 1); - break; +@@ -99,6 +120,9 @@ static int systick_shutdown(struct clock_event_device *evt) + sdev->irq_requested = 0; + iowrite32(0, systick.membase + SYSTICK_CONFIG); + ++ if (systick_freq_scaling) ++ systick_freq_scaling(sdev, 0); ++ + return 0; + } + +@@ -114,15 +138,29 @@ static int systick_set_oneshot(struct clock_event_device *evt) + iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, + systick.membase + SYSTICK_CONFIG); - case CLOCK_EVT_MODE_SHUTDOWN: -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 0); - if (sdev->irq_requested) - free_irq(systick.dev.irq, &systick_irqaction); - sdev->irq_requested = 0; -@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum - } ++ if (systick_freq_scaling) ++ systick_freq_scaling(sdev, 1); ++ + return 0; } +static const struct of_device_id systick_match[] = { @@ -93,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> systick_irqaction.name = np->name; systick.dev.name = np->name; clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0022-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch b/target/linux/ramips/patches-4.3/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch index 96617e8e65..6b09c0e894 100644 --- a/target/linux/ramips/patches-3.18/0022-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch +++ b/target/linux/ramips/patches-4.3/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch @@ -1,21 +1,26 @@ -From ec26251ea980b1ee88733f178a4e86e3c70fd244 Mon Sep 17 00:00:00 2001 +From 67b7bff0fd364c194e653f69baa623ba2141bd4c Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 4 Aug 2014 18:46:02 +0200 -Subject: [PATCH 22/57] MIPS: ralink: copy the commandline from the devicetree +Subject: [PATCH 07/53] MIPS: ralink: copy the commandline from the devicetree Signed-off-by: John Crispin <blogic@openwrt.org> --- arch/mips/ralink/of.c | 2 ++ 1 file changed, 2 insertions(+) +diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c +index 0d30dcd..da85bbf 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c -@@ -74,6 +74,8 @@ void __init plat_mem_setup(void) - */ - __dt_setup_arch(__dtb_start); +@@ -76,6 +76,8 @@ void __init plat_mem_setup(void) + + strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); + strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); + of_scan_flat_dt(early_init_dt_find_memory, NULL); if (memory_dtb) of_scan_flat_dt(early_init_dt_scan_memory, NULL); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch b/target/linux/ramips/patches-4.3/0008-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch index f3dead3859..6fa90f245e 100644 --- a/target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch +++ b/target/linux/ramips/patches-4.3/0008-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch @@ -1,7 +1,7 @@ -From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001 +From 0fd52df8bce3be9edbc195b120bc9a68f970d9e5 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 4 Aug 2014 20:43:25 +0200 -Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency +Subject: [PATCH 08/53] MIPS: ralink: mt7620: fix usb issue during frequency scaling If the USB HCD is running and the cpu is scaled too low, then the USB stops @@ -15,11 +15,13 @@ Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 2ea5ff6..33a7e42 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c -@@ -36,6 +36,12 @@ - #define PMU1_CFG 0x8C - #define DIG_SW_SEL BIT(25) +@@ -40,6 +40,12 @@ + /* is this a MT7620 or a MT7628 */ + enum mt762x_soc_type mt762x_soc; +/* clock scaling */ +#define CLKCFG_FDIV_MASK 0x1f00 @@ -30,7 +32,7 @@ Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency /* does the board have sdram or ddram */ static int dram_type; -@@ -337,6 +343,19 @@ void __init ralink_clk_init(void) +@@ -423,6 +429,19 @@ void __init ralink_clk_init(void) ralink_clk_add("10000b00.spi", sys_rate); ralink_clk_add("10000c00.uartlite", periph_rate); ralink_clk_add("10180000.wmac", xtal_rate); @@ -50,3 +52,6 @@ Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency } void __init ralink_of_remap(void) +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-4.3/0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch index c20a5df55e..2f03f1d496 100644 --- a/target/linux/ramips/patches-3.18/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch +++ b/target/linux/ramips/patches-4.3/0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch @@ -1,26 +1,44 @@ -From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001 +From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> -Date: Sat, 18 May 2013 22:06:15 +0200 -Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver +Date: Mon, 7 Dec 2015 17:11:12 +0100 +Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver Signed-off-by: John Crispin <blogic@openwrt.org> --- - arch/mips/pci/Makefile | 1 + - arch/mips/pci/pci-mt7620.c | 363 +++++++++++++++++++++++++++++++++++++++++++ - arch/mips/ralink/Kconfig | 1 + - 3 files changed, 365 insertions(+) + arch/mips/include/asm/mach-ralink/mt7620.h | 1 + + arch/mips/pci/Makefile | 1 + + arch/mips/pci/pci-mt7620.c | 396 ++++++++++++++++++++++++++++ + arch/mips/ralink/Kconfig | 1 + + 4 files changed, 399 insertions(+) create mode 100644 arch/mips/pci/pci-mt7620.c +diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h +index 1976fb8..72e64fa 100644 +--- a/arch/mips/include/asm/mach-ralink/mt7620.h ++++ b/arch/mips/include/asm/mach-ralink/mt7620.h +@@ -19,6 +19,7 @@ enum mt762x_soc_type { + MT762X_SOC_MT7620N, + MT762X_SOC_MT7628AN, + }; ++extern enum mt762x_soc_type mt762x_soc; + + #define MT7620_SYSC_BASE 0x10000000 + +diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile +index 04e61c3..ccbdc90 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile -@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops +@@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o + obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o obj-$(CONFIG_LANTIQ) += fixup-lantiq.o obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o - obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o +obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o + obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o +diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c +new file mode 100644 +index 0000000..780e4e9 --- /dev/null +++ b/arch/mips/pci/pci-mt7620.c @@ -0,0 +1,396 @@ @@ -420,6 +438,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +} + +arch_initcall(mt7620_pci_init); +diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig +index c2778f2..2aa5e42 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -43,6 +43,7 @@ choice @@ -430,13 +450,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> config SOC_MT7621 bool "MT7621" ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -19,6 +19,7 @@ enum mt762x_soc_type { - MT762X_SOC_MT7620N, - MT762X_SOC_MT7628AN, - }; -+extern enum mt762x_soc_type mt762x_soc; - - #define MT7620_SYSC_BASE 0x10000000 - +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0051-SPI-ralink-add-Ralink-SoC-spi-clocks.patch b/target/linux/ramips/patches-4.3/0010-arch-mips-ralink-add-spi1-clocks.patch index bca872fea4..e2a7d821ef 100644 --- a/target/linux/ramips/patches-3.18/0051-SPI-ralink-add-Ralink-SoC-spi-clocks.patch +++ b/target/linux/ramips/patches-4.3/0010-arch-mips-ralink-add-spi1-clocks.patch @@ -1,23 +1,43 @@ +From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 27 Jul 2014 09:49:07 +0100 +Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks + +based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963 + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 1 + + arch/mips/ralink/rt305x.c | 1 + + arch/mips/ralink/rt3883.c | 1 + + 3 files changed, 3 insertions(+) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 33a7e42..0ba49a1 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c -@@ -415,6 +415,7 @@ void __init ralink_clk_init(void) +@@ -427,6 +427,7 @@ void __init ralink_clk_init(void) ralink_clk_add("10000100.timer", periph_rate); ralink_clk_add("10000120.watchdog", periph_rate); ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000b40.spi", sys_rate); ralink_clk_add("10000c00.uartlite", periph_rate); - ralink_clk_add("10000d00.uart1", periph_rate); - ralink_clk_add("10000e00.uart2", periph_rate); + ralink_clk_add("10180000.wmac", xtal_rate); + +diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c +index c40776a..eeb747a 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c -@@ -201,6 +201,7 @@ void __init ralink_clk_init(void) +@@ -202,6 +202,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("sys", sys_rate); ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000b40.spi", sys_rate); ralink_clk_add("10000100.timer", wdt_rate); ralink_clk_add("10000120.watchdog", wdt_rate); ralink_clk_add("10000500.uart", uart_rate); +diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c +index 86a535c..26827bc 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -109,6 +109,7 @@ void __init ralink_clk_init(void) @@ -28,3 +48,6 @@ ralink_clk_add("10000c00.uartlite", 40000000); ralink_clk_add("10100000.ethernet", sys_rate); ralink_clk_add("10180000.wmac", 40000000); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0060-soc_type.patch b/target/linux/ramips/patches-4.3/0011-arch-mips-ralink-unify-soc-detection.patch index 41cc1208c3..bee7ce3b28 100644 --- a/target/linux/ramips/patches-3.18/0060-soc_type.patch +++ b/target/linux/ramips/patches-4.3/0011-arch-mips-ralink-unify-soc-detection.patch @@ -1,3 +1,19 @@ +From 22ee5168a5dfeda748cabd0bbf728d6bdc6b925b Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:12:38 +0100 +Subject: [PATCH 11/53] arch: mips: ralink: unify soc detection + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/include/asm/mach-ralink/mt7620.h | 8 -------- + arch/mips/include/asm/mach-ralink/ralink_regs.h | 14 ++++++++++++++ + arch/mips/include/asm/mach-ralink/rt305x.h | 21 ++++++--------------- + arch/mips/ralink/prom.c | 5 ++++- + arch/mips/ralink/rt305x.c | 12 +++++------- + 5 files changed, 29 insertions(+), 31 deletions(-) + +diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h +index 72e64fa..0ef882b 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -13,14 +13,6 @@ @@ -15,6 +31,8 @@ #define MT7620_SYSC_BASE 0x10000000 #define SYSC_REG_CHIP_NAME0 0x00 +diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h +index bd93014..8fcbd0f 100644 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h @@ -13,6 +13,20 @@ @@ -38,6 +56,8 @@ extern __iomem void *rt_sysc_membase; extern __iomem void *rt_memc_membase; +diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h +index 96f731b..2eea793 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -13,25 +13,16 @@ @@ -90,76 +110,27 @@ } #define RT305X_SYSC_BASE 0x10000000 ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -43,8 +43,6 @@ - #define CLKCFG_FFRAC_MASK 0x001f - #define CLKCFG_FFRAC_USB_VAL 0x0003 +diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c +index 09419f6..d0978d5 100644 +--- a/arch/mips/ralink/prom.c ++++ b/arch/mips/ralink/prom.c +@@ -15,10 +15,13 @@ + #include <asm/bootinfo.h> + #include <asm/addrspace.h> --enum mt762x_soc_type mt762x_soc; -- - /* does the board have sdram or ddram */ - static int dram_type; - -@@ -375,7 +373,7 @@ void __init ralink_clk_init(void) - #define RINT(x) ((x) / 1000000) - #define RFRAC(x) (((x) / 1000) % 1000) - -- if (mt762x_soc == MT762X_SOC_MT7628AN) { -+ if (ralink_soc == MT762X_SOC_MT7628AN) { - if (xtal_rate == MHZ(40)) - cpu_rate = MHZ(580); - else -@@ -420,7 +418,7 @@ void __init ralink_clk_init(void) - ralink_clk_add("10000e00.uart2", periph_rate); - ralink_clk_add("10180000.wmac", xtal_rate); - -- if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) { -+ if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) { - /* - * When the CPU goes into sleep mode, the BUS clock will be too low for - * USB to function properly -@@ -508,11 +506,11 @@ void prom_soc_init(struct ralink_soc_inf - - if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { - if (bga) { -- mt762x_soc = MT762X_SOC_MT7620A; -+ ralink_soc = MT762X_SOC_MT7620A; - name = "MT7620A"; - soc_info->compatible = "ralink,mt7620a-soc"; - } else { -- mt762x_soc = MT762X_SOC_MT7620N; -+ ralink_soc = MT762X_SOC_MT7620N; - name = "MT7620N"; - soc_info->compatible = "ralink,mt7620n-soc"; - #ifdef CONFIG_PCI -@@ -520,7 +518,7 @@ void prom_soc_init(struct ralink_soc_inf - #endif - } - } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { -- mt762x_soc = MT762X_SOC_MT7628AN; -+ ralink_soc = MT762X_SOC_MT7628AN; - name = "MT7628AN"; - soc_info->compatible = "ralink,mt7628an-soc"; - } else { -@@ -537,7 +535,7 @@ void prom_soc_init(struct ralink_soc_inf - dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; - - soc_info->mem_base = MT7620_DRAM_BASE; -- if (mt762x_soc == MT762X_SOC_MT7628AN) -+ if (ralink_soc == MT762X_SOC_MT7628AN) - mt7628_dram_init(soc_info); - else - mt7620_dram_init(soc_info); -@@ -550,7 +548,7 @@ void prom_soc_init(struct ralink_soc_inf - pr_info("Digital PMU set to %s control\n", - (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - -- if (mt762x_soc == MT762X_SOC_MT7628AN) -+ if (ralink_soc == MT762X_SOC_MT7628AN) - rt2880_pinmux_data = mt7628an_pinmux_data; - else - rt2880_pinmux_data = mt7620a_pinmux_data; ++#include <asm/mach-ralink/ralink_regs.h> ++ + #include "common.h" + + struct ralink_soc_info soc_info; +-struct rt2880_pmx_group *rt2880_pinmux_data = NULL; ++enum ralink_soc_type ralink_soc; ++EXPORT_SYMBOL_GPL(ralink_soc); + + const char *get_system_type(void) + { +diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c +index eeb747a..51f33a5 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -21,8 +21,6 @@ @@ -171,7 +142,7 @@ static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; static struct rt2880_pmx_func uartf_func[] = { -@@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf +@@ -236,24 +234,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info) icache_sets = (read_c0_config1() >> 22) & 7; if (icache_sets == 1) { @@ -201,29 +172,6 @@ name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; } else { ---- a/arch/mips/ralink/prom.c -+++ b/arch/mips/ralink/prom.c -@@ -15,9 +15,13 @@ - #include <asm/bootinfo.h> - #include <asm/addrspace.h> - -+#include <asm/mach-ralink/ralink_regs.h> -+ - #include "common.h" - - struct ralink_soc_info soc_info; -+enum ralink_soc_type ralink_soc; -+EXPORT_SYMBOL_GPL(ralink_soc); - - const char *get_system_type(void) - { ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -193,6 +193,7 @@ void prom_soc_init(struct ralink_soc_inf - soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; - soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; - soc_info->mem_base = MT7621_DRAM_BASE; -+ ralink_soc = MT762X_SOC_MT7621AT; - - rt2880_pinmux_data = mt7621_pinmux_data; - +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0012-arch-mips-fix-clock-jitter.patch b/target/linux/ramips/patches-4.3/0012-arch-mips-fix-clock-jitter.patch new file mode 100644 index 0000000000..58983f0c2f --- /dev/null +++ b/target/linux/ramips/patches-4.3/0012-arch-mips-fix-clock-jitter.patch @@ -0,0 +1,26 @@ +From 2a7f11a3a569159e97b7c5134c4d1f3f5b253637 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:14:42 +0100 +Subject: [PATCH 12/53] arch: mips: fix clock jitter + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/cevt-rt3352.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c +index b36888c..cecf44f 100644 +--- a/arch/mips/ralink/cevt-rt3352.c ++++ b/arch/mips/ralink/cevt-rt3352.c +@@ -69,7 +69,7 @@ static int systick_next_event(unsigned long delta, + sdev = container_of(evt, struct systick_device, dev); + count = ioread32(sdev->membase + SYSTICK_COUNT); + count = (count + delta) % SYSTICK_FREQ; +- iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE); ++ iowrite32(count, sdev->membase + SYSTICK_COMPARE); + + return 0; + } +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0013-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-4.3/0013-owrt-hack-fix-mt7688-cache-issue.patch new file mode 100644 index 0000000000..cb51fe69e6 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0013-owrt-hack-fix-mt7688-cache-issue.patch @@ -0,0 +1,33 @@ +From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:15:32 +0100 +Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/kernel/setup.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c +index 4795151..75bde36 100644 +--- a/arch/mips/kernel/setup.c ++++ b/arch/mips/kernel/setup.c +@@ -681,7 +681,6 @@ static void __init arch_mem_init(char **cmdline_p) + crashk_res.end - crashk_res.start + 1, + BOOTMEM_DEFAULT); + #endif +- device_tree_init(); + sparse_init(); + plat_swiotlb_setup(); + paging_init(); +@@ -791,6 +790,7 @@ void __init setup_arch(char **cmdline_p) + prefill_possible_map(); + + cpu_cache_init(); ++ device_tree_init(); + } + + unsigned long kernelsp[NR_CPUS]; +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0066-cevt.patch b/target/linux/ramips/patches-4.3/0014-arch-mips-cleanup-cevt-rt3352.patch index 9eb6cb612b..d6410505c7 100644 --- a/target/linux/ramips/patches-3.18/0066-cevt.patch +++ b/target/linux/ramips/patches-4.3/0014-arch-mips-cleanup-cevt-rt3352.patch @@ -1,8 +1,29 @@ +From e6ed424c36458aff8738fb1fbb0141196678058a Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:17:23 +0100 +Subject: [PATCH 14/53] arch: mips: cleanup cevt-rt3352 + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/cevt-rt3352.c | 85 ++++++++++++++++++++++++++-------------- + 1 file changed, 56 insertions(+), 29 deletions(-) + +diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c +index cecf44f..424635c 100644 --- a/arch/mips/ralink/cevt-rt3352.c +++ b/arch/mips/ralink/cevt-rt3352.c -@@ -45,18 +45,33 @@ static void (*systick_freq_scaling)(stru - static void systick_set_clock_mode(enum clock_event_mode mode, - struct clock_event_device *evt); +@@ -52,7 +52,7 @@ static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) + + sdev->freq_scale = status; + +- pr_info("%s: %s autosleep mode\n", systick.dev.name, ++ pr_info("%s: %s autosleep mode\n", sdev->dev.name, + (status) ? ("enable") : ("disable")); + if (status) + rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG); +@@ -60,18 +60,33 @@ static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) + rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG); + } +static inline unsigned int read_count(struct systick_device *sdev) +{ @@ -39,7 +60,7 @@ } static void systick_event_handler(struct clock_event_device *dev) -@@ -66,20 +81,25 @@ static void systick_event_handler(struct +@@ -81,20 +96,25 @@ static void systick_event_handler(struct clock_event_device *dev) static irqreturn_t systick_interrupt(int irq, void *dev_id) { @@ -47,12 +68,12 @@ + int ret = 0; + struct clock_event_device *cdev; + struct systick_device *sdev; - -- dev->event_handler(dev); ++ + if (read_c0_cause() & STATUSF_IP7) { + cdev = (struct clock_event_device *) dev_id; + sdev = container_of(cdev, struct systick_device, dev); -+ + +- dev->event_handler(dev); + /* Clear Count/Compare Interrupt */ + write_compare(sdev, read_compare(sdev)); + cdev->event_handler(cdev); @@ -69,28 +90,23 @@ - * cevt-r4k uses 300, make sure systick - * gets used if available - */ -- .rating = 310, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = systick_next_event, - .set_mode = systick_set_clock_mode, -@@ -126,13 +146,14 @@ static void systick_set_clock_mode(enum - systick_freq_scaling(sdev, 1); - break; - -+ case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - if (systick_freq_scaling) - systick_freq_scaling(sdev, 0); - if (sdev->irq_requested) -- free_irq(systick.dev.irq, &systick_irqaction); -+ remove_irq(systick.dev.irq, &systick_irqaction); - sdev->irq_requested = 0; -- iowrite32(0, systick.membase + SYSTICK_CONFIG); -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); - break; - - default: -@@ -142,38 +163,45 @@ static void systick_set_clock_mode(enum +- .rating = 310, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = systick_next_event, + .set_state_shutdown = systick_shutdown, +@@ -116,9 +136,9 @@ static int systick_shutdown(struct clock_event_device *evt) + sdev = container_of(evt, struct systick_device, dev); + + if (sdev->irq_requested) +- free_irq(systick.dev.irq, &systick_irqaction); ++ remove_irq(systick.dev.irq, &systick_irqaction); + sdev->irq_requested = 0; +- iowrite32(0, systick.membase + SYSTICK_CONFIG); ++ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); + + if (systick_freq_scaling) + systick_freq_scaling(sdev, 0); +@@ -145,38 +165,45 @@ static int systick_set_oneshot(struct clock_event_device *evt) } static const struct of_device_id systick_match[] = { @@ -149,3 +165,6 @@ pr_info("%s: running - mult: %d, shift: %d\n", np->name, systick.dev.mult, systick.dev.shift); } +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-4.3/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch new file mode 100644 index 0000000000..ea04175482 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch @@ -0,0 +1,30 @@ +From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:18:05 +0100 +Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by + default + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig +index 2aa5e42..84cf692 100644 +--- a/arch/mips/ralink/Kconfig ++++ b/arch/mips/ralink/Kconfig +@@ -13,9 +13,9 @@ config CLKEVT_RT3352 + select CEVT_SYSTICK_QUIRK + + config RALINK_ILL_ACC +- bool ++ bool "illegal access irq" + depends on SOC_RT305X +- default y ++ default n + + config IRQ_INTC + bool +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0016-arch-mips-ralink-remove-non-PCI-check.patch b/target/linux/ramips/patches-4.3/0016-arch-mips-ralink-remove-non-PCI-check.patch new file mode 100644 index 0000000000..57cc092ef9 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0016-arch-mips-ralink-remove-non-PCI-check.patch @@ -0,0 +1,27 @@ +From 3c146f6123a73cb6c7d21269b5ada8ccb272a988 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:18:41 +0100 +Subject: [PATCH 16/53] arch: mips: ralink: remove non-PCI check + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 0ba49a1..794a7c7 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -526,9 +526,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + mt762x_soc = MT762X_SOC_MT7620N; + name = "MT7620N"; + soc_info->compatible = "ralink,mt7620n-soc"; +-#ifdef CONFIG_PCI +- panic("mt7620n is only supported for non pci kernels"); +-#endif + } + } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { + mt762x_soc = MT762X_SOC_MT7628AN; +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0017-arch-mips-ralink-do-not-set-pm_poweroff.patch b/target/linux/ramips/patches-4.3/0017-arch-mips-ralink-do-not-set-pm_poweroff.patch new file mode 100644 index 0000000000..636edad8c8 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0017-arch-mips-ralink-do-not-set-pm_poweroff.patch @@ -0,0 +1,25 @@ +From 145fcd145e0adb10531bb2e8c9f919b0606dff4d Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:19:15 +0100 +Subject: [PATCH 17/53] arch: mips: ralink: do not set pm_poweroff + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/reset.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c +index 55c7ec5..ee26d45 100644 +--- a/arch/mips/ralink/reset.c ++++ b/arch/mips/ralink/reset.c +@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void) + { + _machine_restart = ralink_restart; + _machine_halt = ralink_halt; +- pm_power_off = ralink_halt; + + return 0; + } +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0070-pci-reset.patch b/target/linux/ramips/patches-4.3/0018-arch-mips-ralink-reset-pci-prior-to-reboot.patch index 6055731822..dbd3db0106 100644 --- a/target/linux/ramips/patches-3.18/0070-pci-reset.patch +++ b/target/linux/ramips/patches-4.3/0018-arch-mips-ralink-reset-pci-prior-to-reboot.patch @@ -1,3 +1,15 @@ +From d3c1e72c755cf67427b5d410039a096520d6537f Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:19:55 +0100 +Subject: [PATCH 18/53] arch: mips: ralink: reset pci prior to reboot + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/reset.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c +index ee26d45..ee117c4 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -11,6 +11,7 @@ @@ -33,3 +45,6 @@ local_irq_disable(); rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); unreachable(); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0071-mt7621-add-cpu-feature-overrides.patch b/target/linux/ramips/patches-4.3/0019-arch-mips-ralink-add-mt7621-cpu-feature-overrides.patch index f6f94f0383..9e7e3e30d9 100644 --- a/target/linux/ramips/patches-3.18/0071-mt7621-add-cpu-feature-overrides.patch +++ b/target/linux/ramips/patches-4.3/0019-arch-mips-ralink-add-mt7621-cpu-feature-overrides.patch @@ -1,3 +1,17 @@ +From 43372c2be9fcf68bc40c322039c75893ce4e982c Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:20:47 +0100 +Subject: [PATCH 19/53] arch: mips: ralink: add mt7621 cpu-feature-overrides + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + .../asm/mach-ralink/mt7621/cpu-feature-overrides.h | 65 ++++++++++++++++++++ + 1 file changed, 65 insertions(+) + create mode 100644 arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h + +diff --git a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h +new file mode 100644 +index 0000000..15db1b3 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h @@ -0,0 +1,65 @@ @@ -66,3 +80,6 @@ +#define cpu_has_userlocal 1 + +#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */ +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0300-mt7628_fixes.patch b/target/linux/ramips/patches-4.3/0020-arch-mips-ralink-mt7628-fixes.patch index 443e07afed..0b5cb04cfb 100644 --- a/target/linux/ramips/patches-3.18/0300-mt7628_fixes.patch +++ b/target/linux/ramips/patches-4.3/0020-arch-mips-ralink-mt7628-fixes.patch @@ -1,11 +1,23 @@ +From 0315355131c46c42164a4b180363bc79728f7015 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:27:15 +0100 +Subject: [PATCH 20/53] arch: mips: ralink: mt7628 fixes + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 76 +++++++++++++++++++++++++++++---------------- + 1 file changed, 50 insertions(+), 26 deletions(-) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 794a7c7..41b4a3e 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c -@@ -101,28 +101,28 @@ static struct rt2880_pmx_group mt7620a_p +@@ -104,28 +104,28 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = { }; static struct rt2880_pmx_func pwm1_grp_mt7628[] = { -- FUNC("sdxc", 3, 19, 1), -+ FUNC("sdxc d6", 3, 19, 1), +- FUNC("sdcx", 3, 19, 1), ++ FUNC("sdcx d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), - FUNC("pwm", 0, 19, 1), @@ -13,8 +25,8 @@ }; static struct rt2880_pmx_func pwm0_grp_mt7628[] = { -- FUNC("sdxc", 3, 18, 1), -+ FUNC("sdxc d7", 3, 18, 1), +- FUNC("sdcx", 3, 18, 1), ++ FUNC("sdcx d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), - FUNC("pwm", 0, 18, 1), @@ -22,20 +34,20 @@ }; static struct rt2880_pmx_func uart2_grp_mt7628[] = { -- FUNC("sdxc", 3, 20, 2), -+ FUNC("sdxc d5 d4", 3, 20, 2), +- FUNC("sdcx", 3, 20, 2), ++ FUNC("sdcx d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), + FUNC("uart", 0, 20, 2), }; static struct rt2880_pmx_func uart1_grp_mt7628[] = { -- FUNC("sdxc", 3, 45, 2), +- FUNC("sdcx", 3, 45, 2), + FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -@@ -165,7 +165,7 @@ static struct rt2880_pmx_func spi_cs1_gr + FUNC("uart", 0, 45, 2), +@@ -168,7 +168,7 @@ static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), @@ -44,7 +56,7 @@ }; static struct rt2880_pmx_func spis_grp_mt7628[] = { -@@ -182,27 +182,43 @@ static struct rt2880_pmx_func gpio_grp_m +@@ -185,28 +185,44 @@ static struct rt2880_pmx_func gpio_grp_mt7628[] = { FUNC("gpio", 0, 11, 1), }; @@ -100,23 +112,25 @@ +#define MT7628_GPIO_MODE_GPIO 0 static struct rt2880_pmx_group mt7628an_pinmux_data[] = { -- GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1), -- GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0), -+ GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1), -+ GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C), -@@ -216,6 +232,8 @@ static struct rt2880_pmx_group mt7628an_ - GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO), -+ GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_WLED_AN), -+ GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_WLED_KN), + GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_PWM1), +- GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, ++ GRP_G("pmw0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_UART2), +@@ -230,6 +246,10 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = { + 1, MT7628_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_GPIO), ++ GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, ++ 1, MT7628_GPIO_MODE_WLED_AN), ++ GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, ++ 1, MT7628_GPIO_MODE_WLED_KN), { 0 } }; -@@ -529,7 +547,11 @@ void prom_soc_init(struct ralink_soc_inf +@@ -542,7 +562,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); @@ -128,4 +142,7 @@ + dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; soc_info->mem_base = MT7620_DRAM_BASE; - if (ralink_soc == MT762X_SOC_MT7628AN) + if (mt762x_soc == MT762X_SOC_MT7628AN) +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch b/target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch new file mode 100644 index 0000000000..5aae36088f --- /dev/null +++ b/target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch @@ -0,0 +1,99 @@ +From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:29:00 +0100 +Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/include/asm/mach-ralink/mt7620.h | 1 + + arch/mips/include/asm/mach-ralink/ralink_regs.h | 1 + + arch/mips/ralink/mt7620.c | 21 ++++++++++++++++----- + 3 files changed, 18 insertions(+), 5 deletions(-) + +diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h +index 0ef882b..455d406 100644 +--- a/arch/mips/include/asm/mach-ralink/mt7620.h ++++ b/arch/mips/include/asm/mach-ralink/mt7620.h +@@ -17,6 +17,7 @@ + + #define SYSC_REG_CHIP_NAME0 0x00 + #define SYSC_REG_CHIP_NAME1 0x04 ++#define SYSC_REG_EFUSE_CFG 0x08 + #define SYSC_REG_CHIP_REV 0x0c + #define SYSC_REG_SYSTEM_CONFIG0 0x10 + #define SYSC_REG_SYSTEM_CONFIG1 0x14 +diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h +index 8fcbd0f..69fbcec 100644 +--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h ++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h +@@ -24,6 +24,7 @@ enum ralink_soc_type { + MT762X_SOC_MT7620N, + MT762X_SOC_MT7621AT, + MT762X_SOC_MT7628AN, ++ MT762X_SOC_MT7688, + }; + extern enum ralink_soc_type ralink_soc; + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 41b4a3e..6975ed8 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc; + #define CLKCFG_FFRAC_MASK 0x001f + #define CLKCFG_FFRAC_USB_VAL 0x0003 + ++/* EFUSE bits */ ++#define EFUSE_MT7688 0x100000 ++ + /* does the board have sdram or ddram */ + static int dram_type; + +@@ -407,7 +410,7 @@ void __init ralink_clk_init(void) + #define RINT(x) ((x) / 1000000) + #define RFRAC(x) (((x) / 1000) % 1000) + +- if (mt762x_soc == MT762X_SOC_MT7628AN) { ++ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) { + if (xtal_rate == MHZ(40)) + cpu_rate = MHZ(580); + else +@@ -451,7 +454,8 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000c00.uartlite", periph_rate); + ralink_clk_add("10180000.wmac", xtal_rate); + +- if (IS_ENABLED(CONFIG_USB)) { ++ if (IS_ENABLED(CONFIG_USB) && ++ (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) { + /* + * When the CPU goes into sleep mode, the BUS clock will be too low for + * USB to function properly +@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + soc_info->compatible = "ralink,mt7620n-soc"; + } + } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { +- mt762x_soc = MT762X_SOC_MT7628AN; +- name = "MT7628AN"; ++ u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); ++ ++ if (efuse & EFUSE_MT7688) { ++ mt762x_soc = MT762X_SOC_MT7688; ++ name = "MT7688"; ++ } else { ++ mt762x_soc = MT762X_SOC_MT7628AN; ++ name = "MT7628AN"; ++ } + soc_info->compatible = "ralink,mt7628an-soc"; + } else { + panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); +@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + pr_info("Digital PMU set to %s control\n", + (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); + +- if (mt762x_soc == MT762X_SOC_MT7628AN) ++ if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) + rt2880_pinmux_data = mt7628an_pinmux_data; + else + rt2880_pinmux_data = mt7620a_pinmux_data; +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0022-arch-mips-ralink-proper-vendor-id-srtring.patch b/target/linux/ramips/patches-4.3/0022-arch-mips-ralink-proper-vendor-id-srtring.patch new file mode 100644 index 0000000000..97f8de3e42 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0022-arch-mips-ralink-proper-vendor-id-srtring.patch @@ -0,0 +1,26 @@ +From 2e5d90398aacde3e46dfd87e6f716b00a0ffcd83 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:30:11 +0100 +Subject: [PATCH 22/53] arch: mips: ralink: proper vendor id srtring + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 6975ed8..da734e2 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -567,7 +567,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + } + + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, +- "Ralink %s ver:%u eco:%u", ++ "MediaTek %s ver:%u eco:%u", + name, + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, + (rev & CHIP_REV_ECO_MASK)); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0023-arch-mips-ralink-unify-soc-id.patch b/target/linux/ramips/patches-4.3/0023-arch-mips-ralink-unify-soc-id.patch new file mode 100644 index 0000000000..3e5d04a259 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0023-arch-mips-ralink-unify-soc-id.patch @@ -0,0 +1,90 @@ +From 4ede4fbb485d0a88839df1f02371fc00755db636 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:31:41 +0100 +Subject: [PATCH 23/53] arch: mips: ralink: unify soc id + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 19 ++++++++----------- + 1 file changed, 8 insertions(+), 11 deletions(-) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index da734e2..db99e9c 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -37,9 +37,6 @@ + #define PMU1_CFG 0x8C + #define DIG_SW_SEL BIT(25) + +-/* is this a MT7620 or a MT7628 */ +-enum mt762x_soc_type mt762x_soc; +- + /* clock scaling */ + #define CLKCFG_FDIV_MASK 0x1f00 + #define CLKCFG_FDIV_USB_VAL 0x0300 +@@ -410,7 +407,7 @@ void __init ralink_clk_init(void) + #define RINT(x) ((x) / 1000000) + #define RFRAC(x) (((x) / 1000) % 1000) + +- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) { ++ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) { + if (xtal_rate == MHZ(40)) + cpu_rate = MHZ(580); + else +@@ -455,7 +452,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("10180000.wmac", xtal_rate); + + if (IS_ENABLED(CONFIG_USB) && +- (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) { ++ (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) { + /* + * When the CPU goes into sleep mode, the BUS clock will be too low for + * USB to function properly +@@ -543,11 +540,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + + if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { + if (bga) { +- mt762x_soc = MT762X_SOC_MT7620A; ++ ralink_soc = MT762X_SOC_MT7620A; + name = "MT7620A"; + soc_info->compatible = "ralink,mt7620a-soc"; + } else { +- mt762x_soc = MT762X_SOC_MT7620N; ++ ralink_soc = MT762X_SOC_MT7620N; + name = "MT7620N"; + soc_info->compatible = "ralink,mt7620n-soc"; + } +@@ -555,10 +552,10 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); + + if (efuse & EFUSE_MT7688) { +- mt762x_soc = MT762X_SOC_MT7688; ++ ralink_soc = MT762X_SOC_MT7688; + name = "MT7688"; + } else { +- mt762x_soc = MT762X_SOC_MT7628AN; ++ ralink_soc = MT762X_SOC_MT7628AN; + name = "MT7628AN"; + } + soc_info->compatible = "ralink,mt7628an-soc"; +@@ -580,7 +577,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; + + soc_info->mem_base = MT7620_DRAM_BASE; +- if (mt762x_soc == MT762X_SOC_MT7628AN) ++ if (ralink_soc == MT762X_SOC_MT7628AN) + mt7628_dram_init(soc_info); + else + mt7620_dram_init(soc_info); +@@ -593,7 +590,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) + pr_info("Digital PMU set to %s control\n", + (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); + +- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) ++ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) + rt2880_pinmux_data = mt7628an_pinmux_data; + else + rt2880_pinmux_data = mt7620a_pinmux_data; +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0030-GPIO-add-named-gpio-exports.patch b/target/linux/ramips/patches-4.3/0024-GPIO-add-named-gpio-exports.patch index 855da68285..e15aabd669 100644 --- a/target/linux/ramips/patches-3.18/0030-GPIO-add-named-gpio-exports.patch +++ b/target/linux/ramips/patches-4.3/0024-GPIO-add-named-gpio-exports.patch @@ -1,28 +1,30 @@ -From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 +From 4267880319bc1a2270d352e0ded6d6386242a7ef Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 30/36] GPIO: add named gpio exports +Subject: [PATCH 24/53] GPIO: add named gpio exports Signed-off-by: John Crispin <blogic@openwrt.org> --- drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ - drivers/gpio/gpiolib.c | 11 +++++-- - include/asm-generic/gpio.h | 5 +++ + drivers/gpio/gpiolib-sysfs.c | 10 +++++- + include/asm-generic/gpio.h | 6 ++++ include/linux/gpio/consumer.h | 8 +++++ - 4 files changed, 90 insertions(+), 2 deletions(-) + 4 files changed, 91 insertions(+), 1 deletion(-) +diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c +index fa6e3c8..c3f34c0 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c -@@ -22,6 +22,8 @@ - #include <linux/of_gpio.h> +@@ -23,6 +23,8 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/slab.h> + #include <linux/gpio/machine.h> +#include <linux/init.h> +#include <linux/platform_device.h> #include "gpiolib.h" -@@ -316,3 +318,69 @@ void of_gpiochip_remove(struct gpio_chip +@@ -450,3 +452,69 @@ void of_gpiochip_remove(struct gpio_chip *chip) gpiochip_remove_pin_ranges(chip); of_node_put(chip->of_node); } @@ -92,9 +94,46 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe); +} +device_initcall(of_gpio_export_init); +diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c +index b57ed8e..0df781d 100644 +--- a/drivers/gpio/gpiolib-sysfs.c ++++ b/drivers/gpio/gpiolib-sysfs.c +@@ -544,7 +544,7 @@ static struct class gpio_class = { + * + * Returns zero on success, else an error. + */ +-int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) + { + struct gpio_chip *chip; + struct gpiod_data *data; +@@ -604,6 +604,8 @@ int gpiod_export(struct gpio_desc *desc, bool direction_may_change) + offset = gpio_chip_hwgpio(desc); + if (chip->names && chip->names[offset]) + ioname = chip->names[offset]; ++ if (name) ++ ioname = name; + + dev = device_create_with_groups(&gpio_class, chip->dev, + MKDEV(0, 0), data, gpio_groups, +@@ -625,6 +627,12 @@ err_unlock: + gpiod_dbg(desc, "%s: status %d\n", __func__, status); + return status; + } ++EXPORT_SYMBOL_GPL(__gpiod_export); ++ ++int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++{ ++ return __gpiod_export(desc, direction_may_change, NULL); ++} + EXPORT_SYMBOL_GPL(gpiod_export); + + static int match_export(struct device *dev, const void *desc) +diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h +index 40ec143..dcb07ab 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h -@@ -123,6 +123,12 @@ static inline int gpio_export(unsigned g +@@ -122,6 +122,12 @@ static inline int gpio_export(unsigned gpio, bool direction_may_change) return gpiod_export(gpio_to_desc(gpio), direction_may_change); } @@ -107,9 +146,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> static inline int gpio_export_link(struct device *dev, const char *name, unsigned gpio) { +diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h +index 14cac67..8097374 100644 --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h -@@ -323,6 +323,7 @@ static inline int desc_to_gpio(const str +@@ -426,6 +426,7 @@ static inline struct gpio_desc *devm_get_gpiod_from_child( #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) @@ -117,7 +158,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> int gpiod_export(struct gpio_desc *desc, bool direction_may_change); int gpiod_export_link(struct device *dev, const char *name, struct gpio_desc *desc); -@@ -331,6 +332,13 @@ void gpiod_unexport(struct gpio_desc *de +@@ -433,6 +434,13 @@ void gpiod_unexport(struct gpio_desc *desc); #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ @@ -131,36 +172,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> static inline int gpiod_export(struct gpio_desc *desc, bool direction_may_change) { ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -517,7 +517,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - unsigned long flags; -@@ -566,6 +566,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (desc->chip->names && desc->chip->names[offset]) - ioname = desc->chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, desc->chip->dev, - MKDEV(0, 0), desc, gpio_groups, -@@ -602,6 +604,12 @@ fail_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *data) +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0025-pinctrl-ralink-add-pinctrl-driver.patch b/target/linux/ramips/patches-4.3/0025-pinctrl-ralink-add-pinctrl-driver.patch new file mode 100644 index 0000000000..76a2ea13f4 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0025-pinctrl-ralink-add-pinctrl-driver.patch @@ -0,0 +1,538 @@ +From 7adbe9a88c33c6e362a10b109d963b5500a21f00 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 27 Jul 2014 09:34:05 +0100 +Subject: [PATCH 25/53] pinctrl: ralink: add pinctrl driver + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/Kconfig | 2 + + drivers/pinctrl/Kconfig | 5 + + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/pinctrl-rt2880.c | 474 ++++++++++++++++++++++++++++++++++++++ + 4 files changed, 482 insertions(+) + create mode 100644 drivers/pinctrl/pinctrl-rt2880.c + +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index e3aa5b0..0098bff 100644 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -557,6 +557,8 @@ config RALINK + select CLKDEV_LOOKUP + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER ++ select PINCTRL ++ select PINCTRL_RT2880 + + config SGI_IP22 + bool "SGI IP22 (Indy/Indigo2)" +diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig +index 84dd2ed..d016935 100644 +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -103,6 +103,11 @@ config PINCTRL_LPC18XX + help + Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU). + ++config PINCTRL_RT2880 ++ bool ++ depends on RALINK ++ select PINMUX ++ + config PINCTRL_FALCON + bool + depends on SOC_FALCON +diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile +index cad077c..0c86632 100644 +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MESON) += meson/ + obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o + obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o + obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o ++obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o + obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o + obj-$(CONFIG_PINCTRL_SIRF) += sirf/ + obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o +diff --git a/drivers/pinctrl/pinctrl-rt2880.c b/drivers/pinctrl/pinctrl-rt2880.c +new file mode 100644 +index 0000000..fe0af77 +--- /dev/null ++++ b/drivers/pinctrl/pinctrl-rt2880.c +@@ -0,0 +1,474 @@ ++/* ++ * linux/drivers/pinctrl/pinctrl-rt2880.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * publishhed by the Free Software Foundation. ++ * ++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/device.h> ++#include <linux/io.h> ++#include <linux/platform_device.h> ++#include <linux/slab.h> ++#include <linux/of.h> ++#include <linux/pinctrl/pinctrl.h> ++#include <linux/pinctrl/pinconf.h> ++#include <linux/pinctrl/pinmux.h> ++#include <linux/pinctrl/consumer.h> ++#include <linux/pinctrl/machine.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++#include <asm/mach-ralink/pinmux.h> ++#include <asm/mach-ralink/mt7620.h> ++ ++#include "core.h" ++ ++#define SYSC_REG_GPIO_MODE 0x60 ++#define SYSC_REG_GPIO_MODE2 0x64 ++ ++struct rt2880_priv { ++ struct device *dev; ++ ++ struct pinctrl_pin_desc *pads; ++ struct pinctrl_desc *desc; ++ ++ struct rt2880_pmx_func **func; ++ int func_count; ++ ++ struct rt2880_pmx_group *groups; ++ const char **group_names; ++ int group_count; ++ ++ uint8_t *gpio; ++ int max_pins; ++}; ++ ++struct rt2880_pmx_group *rt2880_pinmux_data = NULL; ++ ++static int rt2880_get_group_count(struct pinctrl_dev *pctrldev) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ return p->group_count; ++} ++ ++static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev, ++ unsigned group) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ if (group >= p->group_count) ++ return NULL; ++ ++ return p->group_names[group]; ++} ++ ++static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev, ++ unsigned group, ++ const unsigned **pins, ++ unsigned *num_pins) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ if (group >= p->group_count) ++ return -EINVAL; ++ ++ *pins = p->groups[group].func[0].pins; ++ *num_pins = p->groups[group].func[0].pin_count; ++ ++ return 0; ++} ++ ++static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev, ++ struct pinctrl_map *map, unsigned num_maps) ++{ ++ int i; ++ ++ for (i = 0; i < num_maps; i++) ++ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN || ++ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) ++ kfree(map[i].data.configs.configs); ++ kfree(map); ++} ++ ++static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev, ++ struct seq_file *s, ++ unsigned offset) ++{ ++ seq_printf(s, "ralink pio"); ++} ++ ++static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev, ++ struct device_node *np, ++ struct pinctrl_map **map) ++{ ++ const char *function; ++ int func = of_property_read_string(np, "ralink,function", &function); ++ int grps = of_property_count_strings(np, "ralink,group"); ++ int i; ++ ++ if (func || !grps) ++ return; ++ ++ for (i = 0; i < grps; i++) { ++ const char *group; ++ ++ of_property_read_string_index(np, "ralink,group", i, &group); ++ ++ (*map)->type = PIN_MAP_TYPE_MUX_GROUP; ++ (*map)->name = function; ++ (*map)->data.mux.group = group; ++ (*map)->data.mux.function = function; ++ (*map)++; ++ } ++} ++ ++static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev, ++ struct device_node *np_config, ++ struct pinctrl_map **map, ++ unsigned *num_maps) ++{ ++ int max_maps = 0; ++ struct pinctrl_map *tmp; ++ struct device_node *np; ++ ++ for_each_child_of_node(np_config, np) { ++ int ret = of_property_count_strings(np, "ralink,group"); ++ ++ if (ret >= 0) ++ max_maps += ret; ++ } ++ ++ if (!max_maps) ++ return max_maps; ++ ++ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL); ++ if (!*map) ++ return -ENOMEM; ++ ++ tmp = *map; ++ ++ for_each_child_of_node(np_config, np) ++ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp); ++ *num_maps = max_maps; ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops rt2880_pctrl_ops = { ++ .get_groups_count = rt2880_get_group_count, ++ .get_group_name = rt2880_get_group_name, ++ .get_group_pins = rt2880_get_group_pins, ++ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show, ++ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map, ++ .dt_free_map = rt2880_pinctrl_dt_free_map, ++}; ++ ++static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ return p->func_count; ++} ++ ++static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev, ++ unsigned func) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ return p->func[func]->name; ++} ++ ++static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev, ++ unsigned func, ++ const char * const **groups, ++ unsigned * const num_groups) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ if (p->func[func]->group_count == 1) ++ *groups = &p->group_names[p->func[func]->groups[0]]; ++ else ++ *groups = p->group_names; ++ ++ *num_groups = p->func[func]->group_count; ++ ++ return 0; ++} ++ ++static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev, ++ unsigned func, ++ unsigned group) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ u32 mode = 0; ++ u32 reg = SYSC_REG_GPIO_MODE; ++ int i; ++ int shift; ++ ++ /* dont allow double use */ ++ if (p->groups[group].enabled) { ++ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name); ++ return -EBUSY; ++ } ++ ++ p->groups[group].enabled = 1; ++ p->func[func]->enabled = 1; ++ ++ shift = p->groups[group].shift; ++ if (shift >= 32) { ++ shift -= 32; ++ reg = SYSC_REG_GPIO_MODE2; ++ } ++ mode = rt_sysc_r32(reg); ++ mode &= ~(p->groups[group].mask << shift); ++ ++ /* mark the pins as gpio */ ++ for (i = 0; i < p->groups[group].func[0].pin_count; i++) ++ p->gpio[p->groups[group].func[0].pins[i]] = 1; ++ ++ /* function 0 is gpio and needs special handling */ ++ if (func == 0) { ++ mode |= p->groups[group].gpio << shift; ++ } else { ++ for (i = 0; i < p->func[func]->pin_count; i++) ++ p->gpio[p->func[func]->pins[i]] = 0; ++ mode |= p->func[func]->value << shift; ++ } ++ rt_sysc_w32(mode, reg); ++ ++ return 0; ++} ++ ++static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, ++ struct pinctrl_gpio_range *range, ++ unsigned pin) ++{ ++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev); ++ ++ if (!p->gpio[pin]) { ++ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct pinmux_ops rt2880_pmx_group_ops = { ++ .get_functions_count = rt2880_pmx_func_count, ++ .get_function_name = rt2880_pmx_func_name, ++ .get_function_groups = rt2880_pmx_group_get_groups, ++ .set_mux = rt2880_pmx_group_enable, ++ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable, ++}; ++ ++static struct pinctrl_desc rt2880_pctrl_desc = { ++ .owner = THIS_MODULE, ++ .name = "rt2880-pinmux", ++ .pctlops = &rt2880_pctrl_ops, ++ .pmxops = &rt2880_pmx_group_ops, ++}; ++ ++static struct rt2880_pmx_func gpio_func = { ++ .name = "gpio", ++}; ++ ++static int rt2880_pinmux_index(struct rt2880_priv *p) ++{ ++ struct rt2880_pmx_func **f; ++ struct rt2880_pmx_group *mux = p->groups; ++ int i, j, c = 0; ++ ++ /* count the mux functions */ ++ while (mux->name) { ++ p->group_count++; ++ mux++; ++ } ++ ++ /* allocate the group names array needed by the gpio function */ ++ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL); ++ if (!p->group_names) ++ return -1; ++ ++ for (i = 0; i < p->group_count; i++) { ++ p->group_names[i] = p->groups[i].name; ++ p->func_count += p->groups[i].func_count; ++ } ++ ++ /* we have a dummy function[0] for gpio */ ++ p->func_count++; ++ ++ /* allocate our function and group mapping index buffers */ ++ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL); ++ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL); ++ if (!f || !gpio_func.groups) ++ return -1; ++ ++ /* add a backpointer to the function so it knows its group */ ++ gpio_func.group_count = p->group_count; ++ for (i = 0; i < gpio_func.group_count; i++) ++ gpio_func.groups[i] = i; ++ ++ f[c] = &gpio_func; ++ c++; ++ ++ /* add remaining functions */ ++ for (i = 0; i < p->group_count; i++) { ++ for (j = 0; j < p->groups[i].func_count; j++) { ++ f[c] = &p->groups[i].func[j]; ++ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL); ++ f[c]->groups[0] = i; ++ f[c]->group_count = 1; ++ c++; ++ } ++ } ++ return 0; ++} ++ ++static int rt2880_pinmux_pins(struct rt2880_priv *p) ++{ ++ int i, j; ++ ++ /* loop over the functions and initialize the pins array. also work out the highest pin used */ ++ for (i = 0; i < p->func_count; i++) { ++ int pin; ++ ++ if (!p->func[i]->pin_count) ++ continue; ++ ++ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL); ++ for (j = 0; j < p->func[i]->pin_count; j++) ++ p->func[i]->pins[j] = p->func[i]->pin_first + j; ++ ++ pin = p->func[i]->pin_first + p->func[i]->pin_count; ++ if (pin > p->max_pins) ++ p->max_pins = pin; ++ } ++ ++ /* the buffer that tells us which pins are gpio */ ++ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins, ++ GFP_KERNEL); ++ /* the pads needed to tell pinctrl about our pins */ ++ p->pads = devm_kzalloc(p->dev, ++ sizeof(struct pinctrl_pin_desc) * p->max_pins, ++ GFP_KERNEL); ++ if (!p->pads || !p->gpio ) { ++ dev_err(p->dev, "Failed to allocate gpio data\n"); ++ return -ENOMEM; ++ } ++ ++ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins); ++ for (i = 0; i < p->func_count; i++) { ++ if (!p->func[i]->pin_count) ++ continue; ++ ++ for (j = 0; j < p->func[i]->pin_count; j++) ++ p->gpio[p->func[i]->pins[j]] = 0; ++ } ++ ++ /* pin 0 is always a gpio */ ++ p->gpio[0] = 1; ++ ++ /* set the pads */ ++ for (i = 0; i < p->max_pins; i++) { ++ /* strlen("ioXY") + 1 = 5 */ ++ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL); ++ ++ if (!name) { ++ dev_err(p->dev, "Failed to allocate pad name\n"); ++ return -ENOMEM; ++ } ++ snprintf(name, 5, "io%d", i); ++ p->pads[i].number = i; ++ p->pads[i].name = name; ++ } ++ p->desc->pins = p->pads; ++ p->desc->npins = p->max_pins; ++ ++ return 0; ++} ++ ++static int rt2880_pinmux_probe(struct platform_device *pdev) ++{ ++ struct rt2880_priv *p; ++ struct pinctrl_dev *dev; ++ struct device_node *np; ++ ++ if (!rt2880_pinmux_data) ++ return -ENOSYS; ++ ++ /* setup the private data */ ++ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL); ++ if (!p) ++ return -ENOMEM; ++ ++ p->dev = &pdev->dev; ++ p->desc = &rt2880_pctrl_desc; ++ p->groups = rt2880_pinmux_data; ++ platform_set_drvdata(pdev, p); ++ ++ /* init the device */ ++ if (rt2880_pinmux_index(p)) { ++ dev_err(&pdev->dev, "failed to load index\n"); ++ return -EINVAL; ++ } ++ if (rt2880_pinmux_pins(p)) { ++ dev_err(&pdev->dev, "failed to load pins\n"); ++ return -EINVAL; ++ } ++ dev = pinctrl_register(p->desc, &pdev->dev, p); ++ if (IS_ERR(dev)) ++ return PTR_ERR(dev); ++ ++ /* finalize by adding gpio ranges for enables gpio controllers */ ++ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") { ++ const __be32 *ngpio, *gpiobase; ++ struct pinctrl_gpio_range *range; ++ char *name; ++ ++ if (!of_device_is_available(np)) ++ continue; ++ ++ ngpio = of_get_property(np, "ralink,num-gpios", NULL); ++ gpiobase = of_get_property(np, "ralink,gpio-base", NULL); ++ if (!ngpio || !gpiobase) { ++ dev_err(&pdev->dev, "failed to load chip info\n"); ++ return -EINVAL; ++ } ++ ++ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL); ++ range->name = name = (char *) &range[1]; ++ sprintf(name, "pio"); ++ range->npins = __be32_to_cpu(*ngpio); ++ range->base = __be32_to_cpu(*gpiobase); ++ range->pin_base = range->base; ++ pinctrl_add_gpio_range(dev, range); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id rt2880_pinmux_match[] = { ++ { .compatible = "ralink,rt2880-pinmux" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rt2880_pinmux_match); ++ ++static struct platform_driver rt2880_pinmux_driver = { ++ .probe = rt2880_pinmux_probe, ++ .driver = { ++ .name = "rt2880-pinmux", ++ .owner = THIS_MODULE, ++ .of_match_table = rt2880_pinmux_match, ++ }, ++}; ++ ++int __init rt2880_pinmux_init(void) ++{ ++ return platform_driver_register(&rt2880_pinmux_driver); ++} ++ ++core_initcall_sync(rt2880_pinmux_init); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0046-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-4.3/0026-DT-Add-documentation-for-gpio-ralink.patch index 4c869eb858..f6b60e90af 100644 --- a/target/linux/ramips/patches-3.18/0046-DT-Add-documentation-for-gpio-ralink.patch +++ b/target/linux/ramips/patches-4.3/0026-DT-Add-documentation-for-gpio-ralink.patch @@ -1,7 +1,7 @@ -From 6827bd971fc4f323fc91e4506771a13b827c49a3 Mon Sep 17 00:00:00 2001 +From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 28 Jul 2013 19:45:30 +0200 -Subject: [PATCH 46/57] DT: Add documentation for gpio-ralink +Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink Describe gpio-ralink binding. @@ -14,6 +14,9 @@ Cc: linux-gpio@vger.kernel.org 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt +diff --git a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt +new file mode 100644 +index 0000000..b4acf02 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt @@ -0,0 +1,40 @@ @@ -57,3 +60,6 @@ Cc: linux-gpio@vger.kernel.org + 30 34 ]; + + }; +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0047-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-4.3/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch index a742e0b10d..cc09987eec 100644 --- a/target/linux/ramips/patches-3.18/0047-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch +++ b/target/linux/ramips/patches-4.3/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch @@ -1,7 +1,7 @@ -From 4b23ed96930650076caa524ffdde898cb937bdaa Mon Sep 17 00:00:00 2001 +From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 4 Aug 2014 20:36:29 +0200 -Subject: [PATCH 47/57] GPIO: MIPS: ralink: add gpio driver for ralink SoC +Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC Add gpio driver for Ralink SoC. This driver makes the gpio core on RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work. @@ -10,14 +10,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org --- - arch/mips/include/asm/mach-ralink/gpio.h | 24 +++ + arch/mips/include/asm/mach-ralink/gpio.h | 24 ++ drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-ralink.c | 345 ++++++++++++++++++++++++++++++ - 4 files changed, 376 insertions(+) + drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++ + 4 files changed, 386 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h create mode 100644 drivers/gpio/gpio-ralink.c +diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h +new file mode 100644 +index 0000000..f68ee16 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/gpio.h @@ -0,0 +1,24 @@ @@ -45,9 +48,11 @@ Cc: linux-gpio@vger.kernel.org +#define gpio_to_irq __gpio_to_irq + +#endif /* __ASM_MACH_RALINK_GPIO_H */ +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +index 8949b3f..4a3e7df 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig -@@ -288,6 +288,12 @@ config GPIO_SCH311X +@@ -404,6 +404,12 @@ config GPIO_SCH311X To compile this driver as a module, choose M here: the module will be called gpio-sch311x. @@ -60,9 +65,11 @@ Cc: linux-gpio@vger.kernel.org config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +index f79a7c4..13448d78 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile -@@ -67,6 +67,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85 +@@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o @@ -70,6 +77,9 @@ Cc: linux-gpio@vger.kernel.org obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o +diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c +new file mode 100644 +index 0000000..2be9b8a --- /dev/null +++ b/drivers/gpio/gpio-ralink.c @@ -0,0 +1,355 @@ @@ -428,3 +438,6 @@ Cc: linux-gpio@vger.kernel.org +} + +subsys_initcall(ralink_gpio_init); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0048-GPIO-ralink-add-mt7621-gpio-controller.patch b/target/linux/ramips/patches-4.3/0028-GPIO-ralink-add-mt7621-gpio-controller.patch index 429af73b39..9e16aa3c4d 100644 --- a/target/linux/ramips/patches-3.18/0048-GPIO-ralink-add-mt7621-gpio-controller.patch +++ b/target/linux/ramips/patches-4.3/0028-GPIO-ralink-add-mt7621-gpio-controller.patch @@ -1,20 +1,22 @@ -From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001 +From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 11:00:32 +0100 -Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller +Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller Signed-off-by: John Crispin <blogic@openwrt.org> --- arch/mips/Kconfig | 3 + - drivers/gpio/Kconfig | 6 ++ + drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-mt7621.c | 177 ++++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 187 insertions(+) + drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 364 insertions(+) create mode 100644 drivers/gpio/gpio-mt7621.c +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index 0098bff..94ea345 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -455,6 +455,9 @@ config RALINK +@@ -559,6 +559,9 @@ config RALINK select RESET_CONTROLLER select PINCTRL select PINCTRL_RT2880 @@ -24,11 +26,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org> config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +index 4a3e7df..13f860c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig -@@ -898,6 +898,12 @@ config GPIO_BCM_KONA +@@ -269,6 +269,12 @@ config GPIO_MB86S7X help - Turn on GPIO support for Broadcom "Kona" chips. + Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs. +config GPIO_MT7621 + bool "Mediatek GPIO Support" @@ -36,17 +40,21 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + help + Say yes here to support the Mediatek SoC GPIO device + - comment "USB GPIO expanders:" - - config GPIO_VIPERBOARD + config GPIO_MM_LANTIQ + bool "Lantiq Memory mapped GPIOs" + depends on LANTIQ && SOC_XWAY +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +index 13448d78..5563d6e 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile -@@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx - obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o +@@ -119,3 +119,4 @@ obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o + obj-$(CONFIG_GPIO_ZX) += gpio-zx.o +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o -+ +diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c +new file mode 100644 +index 0000000..7a98b94 --- /dev/null +++ b/drivers/gpio/gpio-mt7621.c @@ -0,0 +1,354 @@ @@ -404,3 +412,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +} + +subsys_initcall(mediatek_gpio_init); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-4.3/0029-phy-usb-add-ralink-phy.patch index 2448d0ab31..6bc9d1f7ea 100644 --- a/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch +++ b/target/linux/ramips/patches-4.3/0029-phy-usb-add-ralink-phy.patch @@ -1,6 +1,21 @@ +From a10fc0cb650be725157eca50e2ceb34efc281ac2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 22 Apr 2013 23:20:03 +0200 +Subject: [PATCH 29/53] phy: usb: add ralink phy + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/phy/Kconfig | 5 ++ + drivers/phy/Makefile | 1 + + drivers/phy/phy-ralink-usb.c | 175 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 181 insertions(+) + create mode 100644 drivers/phy/phy-ralink-usb.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 47da573..96ef184 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig -@@ -239,6 +239,11 @@ config PHY_XGENE +@@ -331,6 +331,11 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. @@ -12,13 +27,18 @@ config PHY_STIH407_USB tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family" depends on RESET_CONTROLLER +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index a5b18c1..8dbf6cc 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile -@@ -31,3 +31,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += - obj-$(CONFIG_PHY_XGENE) += phy-xgene.o - obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o - obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o +@@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o + obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o + obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o + obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o +diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c +new file mode 100644 +index 0000000..6c74954 --- /dev/null +++ b/drivers/phy/phy-ralink-usb.c @@ -0,0 +1,175 @@ @@ -174,7 +194,7 @@ + rsthost = devm_reset_control_get(&pdev->dev, "host"); + rstdev = devm_reset_control_get(&pdev->dev, "device"); + -+ rt_phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops, NULL); ++ rt_phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops); + if (IS_ERR(rt_phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(rt_phy); @@ -197,3 +217,6 @@ +MODULE_DESCRIPTION("Ralink USB phy driver"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); +MODULE_LICENSE("GPL v2"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0030-USB-add-OHCI-EHCI-OF-binding.patch b/target/linux/ramips/patches-4.3/0030-USB-add-OHCI-EHCI-OF-binding.patch new file mode 100644 index 0000000000..b57fe9c545 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0030-USB-add-OHCI-EHCI-OF-binding.patch @@ -0,0 +1,40 @@ +From ef42c519247f677229bcbd1ab622222b165242af Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 27 Jul 2014 09:49:07 +0100 +Subject: [PATCH 30/53] USB: add OHCI/EHCI OF binding + +based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963 + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/usb/host/ehci-platform.c | 1 + + drivers/usb/host/ohci-platform.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c +index 5c3c085..fe78568 100644 +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -379,6 +379,7 @@ static int ehci_platform_resume(struct device *dev) + static const struct of_device_id vt8500_ehci_ids[] = { + { .compatible = "via,vt8500-ehci", }, + { .compatible = "wm,prizm-ehci", }, ++ { .compatible = "ralink,rt3xxx-ehci", }, + { .compatible = "generic-ehci", }, + { .compatible = "cavium,octeon-6335-ehci", }, + {} +diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c +index c2669f18..5cf794a 100644 +--- a/drivers/usb/host/ohci-platform.c ++++ b/drivers/usb/host/ohci-platform.c +@@ -344,6 +344,7 @@ static int ohci_platform_resume(struct device *dev) + #endif /* CONFIG_PM_SLEEP */ + + static const struct of_device_id ohci_platform_ids[] = { ++ { .compatible = "ralink,rt3xxx-ohci", }, + { .compatible = "generic-ohci", }, + { .compatible = "cavium,octeon-6335-ohci", }, + { } +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0057-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-4.3/0031-uvc-add-iPassion-iP2970-support.patch index 0828cc51b1..ae004446bd 100644 --- a/target/linux/ramips/patches-3.18/0057-uvc-add-iPassion-iP2970-support.patch +++ b/target/linux/ramips/patches-4.3/0031-uvc-add-iPassion-iP2970-support.patch @@ -1,24 +1,25 @@ -From 0d3e92b4d3e2160873b610aabd46bbc4853ff82e Mon Sep 17 00:00:00 2001 +From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Thu, 19 Sep 2013 01:50:59 +0200 -Subject: [PATCH 57/57] uvc: add iPassion iP2970 support +Subject: [PATCH 31/53] uvc: add iPassion iP2970 support Signed-off-by: John Crispin <blogic@openwrt.org> --- - drivers/media/usb/uvc/uvc_driver.c | 14 ++++ + drivers/media/usb/uvc/uvc_driver.c | 12 +++ drivers/media/usb/uvc/uvc_status.c | 2 + drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++ - drivers/media/usb/uvc/uvcvideo.h | 3 + - 4 files changed, 166 insertions(+) + drivers/media/usb/uvc/uvcvideo.h | 5 +- + 4 files changed, 165 insertions(+), 1 deletion(-) +diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c +index 4b5b3e8..6808bcc 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c -@@ -2504,6 +2504,20 @@ static struct usb_device_id uvc_ids[] = +@@ -2536,6 +2536,18 @@ static struct usb_device_id uvc_ids[] = { + .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, - .driver_info = UVC_QUIRK_PROBE_MINMAX - | UVC_QUIRK_IGNORE_SELECTOR_UNIT }, -+ -+/* iPassion iP2970 */ + .driver_info = UVC_QUIRK_FORCE_Y8 }, ++ /* iPassion iP2970 */ + { .match_flags = USB_DEVICE_ID_MATCH_DEVICE + | USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x1B3B, @@ -30,13 +31,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + | UVC_QUIRK_STREAM_NO_FID + | UVC_QUIRK_MOTION + | UVC_QUIRK_SINGLE_ISO }, -+ /* Generic USB Video Class */ { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, {} +diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c +index f552ab9..7132ad4 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c -@@ -139,6 +139,7 @@ static void uvc_status_complete(struct u +@@ -139,6 +139,7 @@ static void uvc_status_complete(struct urb *urb) switch (dev->status[0] & 0x0f) { case UVC_STATUS_TYPE_CONTROL: uvc_event_control(dev, dev->status, len); @@ -44,7 +46,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> break; case UVC_STATUS_TYPE_STREAMING: -@@ -182,6 +183,7 @@ int uvc_status_init(struct uvc_device *d +@@ -182,6 +183,7 @@ int uvc_status_init(struct uvc_device *dev) } pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress); @@ -52,6 +54,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> /* For high-speed interrupt endpoints, the bInterval value is used as * an exponent of two. Some developers forgot about it. +diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c +index f839654..b30aab6 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -21,6 +21,11 @@ @@ -66,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> #include <media/v4l2-common.h> -@@ -1080,9 +1085,149 @@ static void uvc_video_decode_data(struct +@@ -1089,9 +1094,149 @@ static void uvc_video_decode_data(struct uvc_streaming *stream, } } @@ -216,7 +220,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> /* Mark the buffer as done if the EOF marker is set. */ if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) { uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n"); -@@ -1495,6 +1640,8 @@ static int uvc_init_video_isoc(struct uv +@@ -1504,6 +1649,8 @@ static int uvc_init_video_isoc(struct uvc_streaming *stream, if (npackets == 0) return -ENOMEM; @@ -225,18 +229,22 @@ Signed-off-by: John Crispin <blogic@openwrt.org> size = npackets * psize; for (i = 0; i < UVC_URBS; ++i) { +diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h +index 816dd1a..d0aa324 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h -@@ -148,6 +148,8 @@ - #define UVC_QUIRK_PROBE_DEF 0x00000100 +@@ -152,7 +152,9 @@ #define UVC_QUIRK_RESTRICT_FRAME_RATE 0x00000200 #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400 -+#define UVC_QUIRK_MOTION 0x00000800 -+#define UVC_QUIRK_SINGLE_ISO 0x00001000 - + #define UVC_QUIRK_FORCE_Y8 0x00000800 +- ++#define UVC_QUIRK_MOTION 0x00001000 ++#define UVC_QUIRK_SINGLE_ISO 0x00002000 ++ /* Format flags */ #define UVC_FMT_FLAG_COMPRESSED 0x00000001 -@@ -551,6 +553,7 @@ struct uvc_device { + #define UVC_FMT_FLAG_STREAM 0x00000002 +@@ -550,6 +552,7 @@ struct uvc_device { __u8 *status; struct input_dev *input; char input_phys[64]; @@ -244,3 +252,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> }; enum uvc_handle_state { +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0032-USB-dwc2-add-device_reset.patch b/target/linux/ramips/patches-4.3/0032-USB-dwc2-add-device_reset.patch new file mode 100644 index 0000000000..ca6821e738 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0032-USB-dwc2-add-device_reset.patch @@ -0,0 +1,34 @@ +From a758e0870c6d1e4b0272f6e7f9efa9face5534bb Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 27 Jul 2014 09:49:07 +0100 +Subject: [PATCH 32/53] USB: dwc2: add device_reset() + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/usb/dwc2/hcd.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c +index f845c41..767c93a 100644 +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -47,6 +47,7 @@ + #include <linux/io.h> + #include <linux/slab.h> + #include <linux/usb.h> ++#include <linux/reset.h> + + #include <linux/usb/hcd.h> + #include <linux/usb/ch11.h> +@@ -2841,6 +2842,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) + + retval = -ENOMEM; + ++ device_reset(hsotg->dev); ++ + hcfg = readl(hsotg->regs + HCFG); + dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); + +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0062-mt7621-add-ECHI-OCHI-XCHI-support.patch b/target/linux/ramips/patches-4.3/0033-USB-add-xhci-hooks.patch index f407578762..8f28f86556 100644 --- a/target/linux/ramips/patches-3.18/0062-mt7621-add-ECHI-OCHI-XCHI-support.patch +++ b/target/linux/ramips/patches-4.3/0033-USB-add-xhci-hooks.patch @@ -1,6 +1,49 @@ +From 71fbde37e60c11f5a715c105d25b9c6cee8dae6c Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:14:03 +0100 +Subject: [PATCH 33/53] USB: add xhci hooks + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/usb/core/hcd-pci.c | 5 + + drivers/usb/core/hub.c | 2 +- + drivers/usb/core/port.c | 10 +- + drivers/usb/host/Kconfig | 9 +- + drivers/usb/host/Makefile | 10 +- + drivers/usb/host/mtk-phy-7621.c | 445 +++++ + drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++ + drivers/usb/host/mtk-phy-ahb.c | 58 + + drivers/usb/host/mtk-phy.c | 102 ++ + drivers/usb/host/mtk-phy.h | 179 ++ + drivers/usb/host/pci-quirks.h | 2 +- + drivers/usb/host/xhci-dbg.c | 3 + + drivers/usb/host/xhci-mem.c | 11 + + drivers/usb/host/xhci-mtk-power.c | 115 ++ + drivers/usb/host/xhci-mtk-power.h | 13 + + drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++ + drivers/usb/host/xhci-mtk-scheduler.h | 77 + + drivers/usb/host/xhci-mtk.c | 265 +++ + drivers/usb/host/xhci-mtk.h | 120 ++ + drivers/usb/host/xhci-plat.c | 11 + + drivers/usb/host/xhci-ring.c | 104 ++ + drivers/usb/host/xhci.c | 209 ++- + drivers/usb/host/xhci.h | 39 + + 23 files changed, 5257 insertions(+), 11 deletions(-) + create mode 100644 drivers/usb/host/mtk-phy-7621.c + create mode 100644 drivers/usb/host/mtk-phy-7621.h + create mode 100644 drivers/usb/host/mtk-phy-ahb.c + create mode 100644 drivers/usb/host/mtk-phy.c + create mode 100644 drivers/usb/host/mtk-phy.h + create mode 100644 drivers/usb/host/xhci-mtk-power.c + create mode 100644 drivers/usb/host/xhci-mtk-power.h + create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c + create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h + create mode 100644 drivers/usb/host/xhci-mtk.c + create mode 100644 drivers/usb/host/xhci-mtk.h + --- a/drivers/usb/core/hcd-pci.c +++ b/drivers/usb/core/hcd-pci.c -@@ -214,8 +214,13 @@ int usb_hcd_pci_probe(struct pci_dev *de +@@ -214,8 +214,13 @@ goto disable_pci; } @@ -16,7 +59,7 @@ /* EHCI, OHCI */ --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -1286,7 +1286,7 @@ static void hub_quiesce(struct usb_hub * +@@ -1287,7 +1287,7 @@ if (type != HUB_SUSPEND) { /* Disconnect all the children */ for (i = 0; i < hdev->maxchild; ++i) { @@ -27,7 +70,7 @@ } --- a/drivers/usb/core/port.c +++ b/drivers/usb/core/port.c -@@ -480,8 +480,10 @@ void usb_hub_remove_port_device(struct u +@@ -480,8 +480,10 @@ struct usb_port *port_dev = hub->ports[port1 - 1]; struct usb_port *peer; @@ -44,7 +87,7 @@ } --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig -@@ -41,6 +41,13 @@ config USB_XHCI_PLATFORM +@@ -41,6 +41,13 @@ If unsure, say N. @@ -58,7 +101,7 @@ config USB_XHCI_MVEBU tristate "xHCI support for Marvell Armada 375/38x" select USB_XHCI_PLATFORM -@@ -596,7 +603,7 @@ endif # USB_OHCI_HCD +@@ -590,7 +597,7 @@ config USB_UHCI_HCD tristate "UHCI HCD (most Intel and VIA) support" @@ -69,7 +112,7 @@ accessing the USB hardware in the PC (which is also called the USB --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile -@@ -16,7 +16,12 @@ xhci-hcd-y := xhci.o xhci-mem.o +@@ -14,7 +14,12 @@ xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o xhci-hcd-y += xhci-trace.o @@ -82,18 +125,17 @@ ifneq ($(CONFIG_USB_XHCI_MVEBU), ) xhci-plat-hcd-y += xhci-mvebu.o endif -@@ -26,9 +31,14 @@ endif +@@ -24,11 +29,10 @@ obj-$(CONFIG_USB_WHCI_HCD) += whci/ +-ifneq ($(CONFIG_USB), ) +ifndef CONFIG_USB_MT7621_XHCI_PLATFORM - obj-$(CONFIG_PCI) += pci-quirks.o -+endif - -+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM - obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o -+endif -+ + obj-$(CONFIG_PCI) += pci-quirks.o ++ obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o + endif +- +-obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o @@ -3792,7 +3834,7 @@ --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c -@@ -67,6 +67,9 @@ static struct xhci_segment *xhci_segment +@@ -67,6 +67,9 @@ static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) { @@ -3802,7 +3844,7 @@ if (seg->trbs) { dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); seg->trbs = NULL; -@@ -1475,9 +1478,17 @@ int xhci_endpoint_init(struct xhci_hcd * +@@ -1471,9 +1474,17 @@ max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11; } @@ -5038,7 +5080,7 @@ +#endif --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c -@@ -33,6 +33,13 @@ static void xhci_plat_quirks(struct devi +@@ -43,6 +43,13 @@ * dev struct in order to setup MSI */ xhci->quirks |= XHCI_PLAT; @@ -5052,7 +5094,7 @@ } /* called during probe() after chip reset completes */ -@@ -79,7 +86,11 @@ static int xhci_plat_probe(struct platfo +@@ -89,7 +96,11 @@ driver = &xhci_plat_hc_driver; @@ -5066,7 +5108,7 @@ --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -254,16 +254,20 @@ static void inc_enq(struct xhci_hcd *xhc +@@ -254,16 +254,20 @@ static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, unsigned int num_trbs) { @@ -5087,7 +5129,7 @@ return 1; } -@@ -2810,6 +2814,7 @@ static int prepare_ring(struct xhci_hcd +@@ -2869,6 +2873,7 @@ next = ring->enqueue; while (last_trb(xhci, ring, ring->enq_seg, next)) { @@ -5095,7 +5137,7 @@ /* If we're not dealing with 0.95 hardware or isoc rings * on AMD 0.96 host, clear the chain bit. */ -@@ -2819,6 +2824,9 @@ static int prepare_ring(struct xhci_hcd +@@ -2878,6 +2883,9 @@ next->link.control &= cpu_to_le32(~TRB_CHAIN); else next->link.control |= cpu_to_le32(TRB_CHAIN); @@ -5105,7 +5147,7 @@ wmb(); next->link.control ^= cpu_to_le32(TRB_CYCLE); -@@ -2949,6 +2957,9 @@ static void giveback_first_trb(struct xh +@@ -3008,6 +3016,9 @@ start_trb->field[3] |= cpu_to_le32(start_cycle); else start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); @@ -5115,7 +5157,7 @@ xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); } -@@ -3004,6 +3015,29 @@ static u32 xhci_td_remainder(unsigned in +@@ -3063,6 +3074,29 @@ return (remainder >> 10) << 17; } @@ -5145,7 +5187,7 @@ /* * For xHCI 1.0 host controllers, TD size is the number of max packet sized * packets remaining in the TD (*not* including this TRB). -@@ -3161,6 +3195,7 @@ static int queue_bulk_sg_tx(struct xhci_ +@@ -3220,6 +3254,7 @@ } /* Set the TRB length, TD size, and interrupter fields. */ @@ -5153,7 +5195,7 @@ if (xhci->hci_version < 0x100) { remainder = xhci_td_remainder( urb->transfer_buffer_length - -@@ -3170,6 +3205,12 @@ static int queue_bulk_sg_tx(struct xhci_ +@@ -3229,6 +3264,12 @@ trb_buff_len, total_packet_count, urb, num_trbs - 1); } @@ -5166,7 +5208,7 @@ length_field = TRB_LEN(trb_buff_len) | remainder | TRB_INTR_TARGET(0); -@@ -3234,6 +3275,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3293,6 +3334,9 @@ int running_total, trb_buff_len, ret; unsigned int total_packet_count; u64 addr; @@ -5176,7 +5218,7 @@ if (urb->num_sgs) return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); -@@ -3258,6 +3302,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3317,6 +3361,25 @@ num_trbs++; running_total += TRB_MAX_BUFF_SIZE; } @@ -5202,7 +5244,7 @@ ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, urb->stream_id, -@@ -3334,6 +3397,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3393,6 +3456,7 @@ field |= TRB_ISP; /* Set the TRB length, TD size, and interrupter fields. */ @@ -5210,7 +5252,7 @@ if (xhci->hci_version < 0x100) { remainder = xhci_td_remainder( urb->transfer_buffer_length - -@@ -3343,6 +3407,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3402,6 +3466,10 @@ trb_buff_len, total_packet_count, urb, num_trbs - 1); } @@ -5221,7 +5263,7 @@ length_field = TRB_LEN(trb_buff_len) | remainder | TRB_INTR_TARGET(0); -@@ -3432,7 +3500,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * +@@ -3491,7 +3559,11 @@ field |= 0x1; /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ @@ -5233,7 +5275,7 @@ if (urb->transfer_buffer_length > 0) { if (setup->bRequestType & USB_DIR_IN) field |= TRB_TX_TYPE(TRB_DATA_IN); -@@ -3456,7 +3528,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * +@@ -3515,7 +3587,12 @@ field = TRB_TYPE(TRB_DATA); length_field = TRB_LEN(urb->transfer_buffer_length) | @@ -5246,17 +5288,17 @@ TRB_INTR_TARGET(0); if (urb->transfer_buffer_length > 0) { if (setup->bRequestType & USB_DIR_IN) -@@ -3579,6 +3656,9 @@ static int xhci_queue_isoc_tx(struct xhc - u64 start_addr, addr; - int i, j; +@@ -3731,6 +3808,9 @@ bool more_trbs_coming; + struct xhci_virt_ep *xep; + +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) + int max_packet; +#endif - + xep = &xhci->devs[slot_id]->eps[ep_index]; ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; -@@ -3592,6 +3672,21 @@ static int xhci_queue_isoc_tx(struct xhc +@@ -3744,6 +3824,21 @@ start_trb = &ep_ring->enqueue->generic; start_cycle = ep_ring->cycle_state; @@ -5278,7 +5320,7 @@ urb_priv = urb->hcpriv; /* Queue the first TRB, even if it's zero-length */ for (i = 0; i < num_tds; i++) { -@@ -3663,9 +3758,13 @@ static int xhci_queue_isoc_tx(struct xhc +@@ -3828,9 +3923,13 @@ } else { td->last_trb = ep_ring->enqueue; field |= TRB_IOC; @@ -5292,7 +5334,7 @@ /* Set BEI bit except for the last td */ if (i < num_tds - 1) field |= TRB_BEI; -@@ -3680,6 +3779,7 @@ static int xhci_queue_isoc_tx(struct xhc +@@ -3845,6 +3944,7 @@ trb_buff_len = td_remain_len; /* Set the TRB length, TD size, & interrupter fields. */ @@ -5300,7 +5342,7 @@ if (xhci->hci_version < 0x100) { remainder = xhci_td_remainder( td_len - running_total); -@@ -3689,6 +3789,10 @@ static int xhci_queue_isoc_tx(struct xhc +@@ -3854,6 +3954,10 @@ total_packet_count, urb, (trbs_per_td - j - 1)); } @@ -5330,7 +5372,7 @@ #define DRIVER_AUTHOR "Sarah Sharp" #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" -@@ -46,6 +56,18 @@ static unsigned int quirks; +@@ -46,6 +56,18 @@ module_param(quirks, uint, S_IRUGO); MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); @@ -5349,7 +5391,7 @@ /* TODO: copied from ehci-hcd.c - can this be refactored? */ /* * xhci_handshake - spin reading hc until handshake completes or fails -@@ -199,7 +221,7 @@ int xhci_reset(struct xhci_hcd *xhci) +@@ -198,7 +220,7 @@ return ret; } @@ -5358,7 +5400,7 @@ static int xhci_free_msi(struct xhci_hcd *xhci) { int i; -@@ -449,6 +471,11 @@ static void compliance_mode_recovery(uns +@@ -448,6 +470,11 @@ "Attempting compliance mode recovery"); hcd = xhci->shared_hcd; @@ -5370,7 +5412,7 @@ if (hcd->state == HC_STATE_SUSPENDED) usb_hcd_resume_root_hub(hcd); -@@ -498,6 +525,9 @@ static bool xhci_compliance_mode_recover +@@ -495,6 +522,9 @@ { const char *dmi_product_name, *dmi_sys_vendor; @@ -5380,7 +5422,7 @@ dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); if (!dmi_product_name || !dmi_sys_vendor) -@@ -543,6 +573,10 @@ int xhci_init(struct usb_hcd *hcd) +@@ -540,6 +570,10 @@ xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xHCI doesn't need link TRB QUIRK"); } @@ -5391,7 +5433,7 @@ retval = xhci_mem_init(xhci, GFP_KERNEL); xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); -@@ -627,7 +661,11 @@ int xhci_run(struct usb_hcd *hcd) +@@ -624,7 +658,11 @@ "// Set the interrupt modulation register"); temp = readl(&xhci->ir_set->irq_control); temp &= ~ER_IRQ_INTERVAL_MASK; @@ -5403,7 +5445,7 @@ writel(temp, &xhci->ir_set->irq_control); /* Set the HCD state before we enable the irqs */ -@@ -652,6 +690,9 @@ int xhci_run(struct usb_hcd *hcd) +@@ -649,6 +687,9 @@ xhci_queue_vendor_command(xhci, command, 0, 0, 0, TRB_TYPE(TRB_NEC_GET_FW)); } @@ -5413,7 +5455,7 @@ xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_run for USB2 roothub"); return 0; -@@ -1648,6 +1689,14 @@ int xhci_drop_endpoint(struct usb_hcd *h +@@ -1639,6 +1680,14 @@ u32 drop_flag; u32 new_add_flags, new_drop_flags; int ret; @@ -5428,7 +5470,7 @@ ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); if (ret <= 0) -@@ -1695,6 +1744,40 @@ int xhci_drop_endpoint(struct usb_hcd *h +@@ -1688,6 +1737,40 @@ xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); @@ -5469,7 +5511,7 @@ xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", (unsigned int) ep->desc.bEndpointAddress, udev->slot_id, -@@ -1727,6 +1810,19 @@ int xhci_add_endpoint(struct usb_hcd *hc +@@ -1720,6 +1803,19 @@ u32 new_add_flags, new_drop_flags; struct xhci_virt_device *virt_dev; int ret = 0; @@ -5489,7 +5531,7 @@ ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); if (ret <= 0) { -@@ -1793,6 +1889,56 @@ int xhci_add_endpoint(struct usb_hcd *hc +@@ -1783,6 +1879,56 @@ return -ENOMEM; } @@ -5546,7 +5588,7 @@ ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); -@@ -4463,8 +4609,14 @@ static u16 xhci_call_host_update_timeout +@@ -4446,8 +4592,14 @@ u16 *timeout) { if (state == USB3_LPM_U1) @@ -5561,7 +5603,7 @@ return xhci_calculate_u2_timeout(xhci, udev, desc); return USB3_LPM_DISABLED; -@@ -4849,7 +5001,9 @@ int xhci_gen_setup(struct usb_hcd *hcd, +@@ -4839,7 +4991,9 @@ hcd->self.no_sg_constraint = 1; /* XHCI controllers don't stop the ep queue on short packets :| */ @@ -5570,9 +5612,9 @@ +#endif if (usb_hcd_is_primary_hcd(hcd)) { - xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); -@@ -4912,6 +5066,10 @@ int xhci_gen_setup(struct usb_hcd *hcd, - goto error; + xhci = hcd_to_xhci(hcd); +@@ -4900,6 +5054,10 @@ + return retval; xhci_dbg(xhci, "Reset complete\n"); +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) @@ -5582,7 +5624,7 @@ /* Set dma_mask and coherent_dma_mask to 64-bits, * if xHC supports 64-bit addressing */ if (HCC_64BIT_ADDR(xhci->hcc_params) && -@@ -5006,8 +5164,57 @@ MODULE_DESCRIPTION(DRIVER_DESC); +@@ -5005,8 +5163,57 @@ MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_LICENSE("GPL"); @@ -5633,7 +5675,7 @@ + pPlatformDev->resource = xhci_resouce; + pPlatformDev->num_resources = ARRAY_SIZE(xhci_resouce); + -+ platform_device_register(&xhci_platform_dev); ++// platform_device_register(&xhci_platform_dev); + +#endif + @@ -5647,7 +5689,7 @@ #include "pci-quirks.h" +#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM) -+#define XHC_IRQ (22 + 8) ++#define XHC_IRQ (22 + 7) +#define XHC_IO_START 0x1E1C0000 +#define XHC_IO_LENGTH 0x10000 +/* mtk scheduler bitmasks */ @@ -5664,7 +5706,7 @@ /* xHCI PCI Configuration Registers */ #define XHCI_SBRN_OFFSET (0x60) -@@ -1587,8 +1602,12 @@ struct xhci_hcd { +@@ -1597,8 +1612,12 @@ /* Compliance Mode Recovery Data */ struct timer_list comp_mode_recovery_timer; u32 port_status_u0; @@ -5676,8 +5718,8 @@ +#endif }; - /* convert between an HCD pointer and the corresponding EHCI_HCD */ -@@ -1736,6 +1755,26 @@ void xhci_urb_free_priv(struct xhci_hcd + /* Platform specific overrides to generic XHCI hc_driver ops */ +@@ -1763,6 +1782,26 @@ void xhci_free_command(struct xhci_hcd *xhci, struct xhci_command *command); @@ -5703,4 +5745,4 @@ + /* xHCI host controller glue */ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); - int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, + int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); diff --git a/target/linux/ramips/patches-3.18/0033-NET-multi-phy-support.patch b/target/linux/ramips/patches-4.3/0034-NET-multi-phy-support.patch index f6d2456bad..f163e3cbc6 100644 --- a/target/linux/ramips/patches-3.18/0033-NET-multi-phy-support.patch +++ b/target/linux/ramips/patches-4.3/0034-NET-multi-phy-support.patch @@ -1,7 +1,7 @@ -From 9c34372c25519234add1cfdfe2b69c0847f2037e Mon Sep 17 00:00:00 2001 +From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 09:38:50 +0100 -Subject: [PATCH 33/57] NET: multi phy support +Subject: [PATCH 34/53] NET: multi phy support Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -9,9 +9,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> include/linux/phy.h | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) +diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c +index adb48ab..7eb83bd 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c -@@ -838,7 +838,8 @@ void phy_state_machine(struct work_struc +@@ -843,7 +843,8 @@ void phy_state_machine(struct work_struct *work) /* If the link is down, give up on negotiation for now */ if (!phydev->link) { phydev->state = PHY_NOLINK; @@ -21,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> phydev->adjust_link(phydev->attached_dev); break; } -@@ -911,7 +912,8 @@ void phy_state_machine(struct work_struc +@@ -923,7 +924,8 @@ void phy_state_machine(struct work_struct *work) netif_carrier_on(phydev->attached_dev); } else { phydev->state = PHY_NOLINK; @@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> } phydev->adjust_link(phydev->attached_dev); -@@ -923,7 +925,8 @@ void phy_state_machine(struct work_struc +@@ -935,7 +937,8 @@ void phy_state_machine(struct work_struct *work) case PHY_HALTED: if (phydev->link) { phydev->link = 0; @@ -41,13 +43,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org> phydev->adjust_link(phydev->attached_dev); do_suspend = true; } +diff --git a/include/linux/phy.h b/include/linux/phy.h +index 4a4e3a0..a260bdc 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -363,6 +363,7 @@ struct phy_device { - struct phy_c45_device_ids c45_ids; - bool is_c45; - bool is_internal; -+ bool no_auto_carrier_off; +@@ -375,6 +375,7 @@ struct phy_device { + bool is_pseudo_fixed_link; bool has_fixups; + bool suspended; ++ bool no_auto_carrier_off; enum phy_state state; + +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch b/target/linux/ramips/patches-4.3/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch index ede6d7d476..e9f405daac 100644 --- a/target/linux/ramips/patches-3.18/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch +++ b/target/linux/ramips/patches-4.3/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch @@ -1,12 +1,19 @@ -From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001 +From 86ab021705a493a5276261953f4f2cb071df6722 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 22 Apr 2013 23:20:03 +0200 -Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver +Subject: [PATCH 35/53] NET: MIPS: add ralink SoC ethernet driver Add support for Ralink FE and ESW. Signed-off-by: John Crispin <blogic@openwrt.org> --- + arch/mips/ralink/rt305x.c | 1 + + drivers/net/ethernet/Kconfig | 1 + + drivers/net/ethernet/Makefile | 1 + + 3 files changed, 3 insertions(+) + +diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c +index 51f33a5..d7c4ba4 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -199,6 +199,7 @@ void __init ralink_clk_init(void) @@ -15,11 +22,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org> ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("sys", sys_rate); ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000b40.spi", sys_rate); ralink_clk_add("10000100.timer", wdt_rate); - ralink_clk_add("10000120.watchdog", wdt_rate); +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index 05aa759..5628f2d 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig -@@ -152,6 +152,7 @@ source "drivers/net/ethernet/packetengin +@@ -154,6 +154,7 @@ source "drivers/net/ethernet/packetengines/Kconfig" source "drivers/net/ethernet/pasemi/Kconfig" source "drivers/net/ethernet/qlogic/Kconfig" source "drivers/net/ethernet/qualcomm/Kconfig" @@ -27,13 +36,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org> source "drivers/net/ethernet/realtek/Kconfig" source "drivers/net/ethernet/renesas/Kconfig" source "drivers/net/ethernet/rdc/Kconfig" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index ddfc808..cbfe95e 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile -@@ -62,6 +62,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe +@@ -64,6 +64,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/ +obj-$(CONFIG_NET_RALINK) += ralink/ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/ - obj-$(CONFIG_SH_ETH) += renesas/ + obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0041-mtd-fix-cfi-cmdset-0002-erase-status-check.patch b/target/linux/ramips/patches-4.3/0036-mtd-fix-cfi-cmdset-0002-erase-status-check.patch index b51756dbfa..635f60475a 100644 --- a/target/linux/ramips/patches-3.18/0041-mtd-fix-cfi-cmdset-0002-erase-status-check.patch +++ b/target/linux/ramips/patches-4.3/0036-mtd-fix-cfi-cmdset-0002-erase-status-check.patch @@ -1,15 +1,17 @@ -From f0df443ca7d5d0e4d31aa6769ea12a8cf24d2cd8 Mon Sep 17 00:00:00 2001 +From 8e72a3a1be8f6328bd7ef491332ba541547b6086 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 15 Jul 2013 00:38:51 +0200 -Subject: [PATCH 41/57] mtd: fix cfi cmdset 0002 erase status check +Subject: [PATCH 36/53] mtd: fix cfi cmdset 0002 erase status check --- drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) +diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c +index c3624eb..60d960a 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -2291,7 +2291,7 @@ static int __xipram do_erase_chip(struct +@@ -2290,7 +2290,7 @@ static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) chip->erase_suspended = 0; } @@ -18,7 +20,7 @@ Subject: [PATCH 41/57] mtd: fix cfi cmdset 0002 erase status check break; if (time_after(jiffies, timeo)) { -@@ -2380,7 +2380,7 @@ static int __xipram do_erase_oneblock(st +@@ -2379,7 +2379,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, chip->erase_suspended = 0; } @@ -27,3 +29,6 @@ Subject: [PATCH 41/57] mtd: fix cfi cmdset 0002 erase status check xip_enable(map, chip, adr); break; } +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0042-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-4.3/0037-mtd-cfi-cmdset-0002-force-word-write.patch index 971738c19a..7c1ea22a6b 100644 --- a/target/linux/ramips/patches-3.18/0042-mtd-cfi-cmdset-0002-force-word-write.patch +++ b/target/linux/ramips/patches-4.3/0037-mtd-cfi-cmdset-0002-force-word-write.patch @@ -1,12 +1,14 @@ -From 39010a26a34a56a7928f9217ac23e5138c5ea952 Mon Sep 17 00:00:00 2001 +From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Mon, 15 Jul 2013 00:39:21 +0200 -Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write +Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write --- drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) +diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c +index 60d960a..a663e3b 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c @@ -40,7 +40,7 @@ @@ -28,7 +30,7 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); static void cfi_amdstd_sync (struct mtd_info *); -@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m +@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct mtd_info *mtd) } #endif @@ -36,7 +38,7 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write static void fixup_use_write_buffers(struct mtd_info *mtd) { struct map_info *map = mtd->priv; -@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru +@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(struct mtd_info *mtd) mtd->_write = cfi_amdstd_write_buffers; } } @@ -44,7 +46,7 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write /* Atmel chips don't use the same PRI format as AMD chips */ static void fixup_convert_atmel_pri(struct mtd_info *mtd) -@@ -1789,6 +1793,7 @@ static int cfi_amdstd_write_words(struct +@@ -1789,6 +1793,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, /* * FIXME: interleaved mode not tested, and probably not supported! */ @@ -52,7 +54,7 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, unsigned long adr, const u_char *buf, int len) -@@ -1917,7 +1922,6 @@ static int __xipram do_write_buffer(stru +@@ -1916,7 +1921,6 @@ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, return ret; } @@ -60,7 +62,7 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { -@@ -1992,6 +1996,7 @@ static int cfi_amdstd_write_buffers(stru +@@ -1991,6 +1995,7 @@ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, return 0; } @@ -68,3 +70,6 @@ Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write /* * Wait for the flash chip to become ready to write data +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0043-mtd-ralink-add-mt7620-nand-driver.patch b/target/linux/ramips/patches-4.3/0038-mtd-ralink-add-mt7620-nand-driver.patch index 8ee26d5182..a381e21419 100644 --- a/target/linux/ramips/patches-3.18/0043-mtd-ralink-add-mt7620-nand-driver.patch +++ b/target/linux/ramips/patches-4.3/0038-mtd-ralink-add-mt7620-nand-driver.patch @@ -1,7 +1,7 @@ -From b915fe7cd934160bfaf2cd52f03c118abcae2419 Mon Sep 17 00:00:00 2001 +From fb6e1578cd73d7d81f675e75247a676423f32412 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 17 Nov 2013 17:41:46 +0100 -Subject: [PATCH 43/57] mtd: ralink: add mt7620 nand driver +Subject: [PATCH 38/53] mtd: ralink: add mt7620 nand driver Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> create mode 100644 drivers/mtd/maps/ralink_nand.c create mode 100644 drivers/mtd/maps/ralink_nand.h +diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig +index 7c95a65..c2739db 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -399,4 +399,8 @@ config MTD_LATCH_ADDR @@ -24,6 +26,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + depends on RALINK && SOC_MT7620 + endmenu +diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile +index 141c91a..94d2aa0 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -43,3 +43,5 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o @@ -32,6 +36,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o +obj-$(CONFIG_MTD_NAND_MT7620) += ralink_nand.o + +diff --git a/drivers/mtd/maps/ralink_nand.c b/drivers/mtd/maps/ralink_nand.c +new file mode 100644 +index 0000000..64f9119 --- /dev/null +++ b/drivers/mtd/maps/ralink_nand.c @@ -0,0 +1,2136 @@ @@ -2171,6 +2178,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + + +MODULE_LICENSE("GPL"); +diff --git a/drivers/mtd/maps/ralink_nand.h b/drivers/mtd/maps/ralink_nand.h +new file mode 100644 +index 0000000..a408ae9 --- /dev/null +++ b/drivers/mtd/maps/ralink_nand.h @@ -0,0 +1,232 @@ @@ -2406,3 +2416,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + + +#endif +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0045-mtd-add-mt7621-nand-support.patch b/target/linux/ramips/patches-4.3/0039-mtd-add-mt7621-nand-support.patch index 3999f54d7a..b84e666ed7 100644 --- a/target/linux/ramips/patches-3.18/0045-mtd-add-mt7621-nand-support.patch +++ b/target/linux/ramips/patches-4.3/0039-mtd-add-mt7621-nand-support.patch @@ -1,7 +1,7 @@ -From 5db075c5dd038fbf4b5a0196e10f4f9658236372 Mon Sep 17 00:00:00 2001 +From 0e1c4e3c97b83b4e7da65b1c56f0a7d40736ac53 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 11:05:17 +0100 -Subject: [PATCH 45/57] mtd: add mt7621 nand support +Subject: [PATCH 39/53] mtd: add mt7621 nand support Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -29,11 +29,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org> create mode 100644 drivers/mtd/nand/nand_device_list.h create mode 100644 drivers/mtd/nand/partition.h +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index 3324281..76cfc97 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig -@@ -516,4 +516,10 @@ config MTD_NAND_XWAY - Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached - to the External Bus Unit (EBU). +@@ -535,4 +535,10 @@ config MTD_NAND_HISI504 + help + Enables support for NAND controller on Hisilicon SoC Hip04. +config MTK_MTD_NAND + tristate "Support for MTK SoC NAND controller" @@ -42,15 +44,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + select MTD_NAND_ECC + endif # MTD_NAND +diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile +index 075a027..ec349e3 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile -@@ -50,5 +50,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740 - obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ - obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o - obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ +@@ -54,5 +54,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ + obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o + obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ +obj-$(CONFIG_MTK_MTD_NAND) += mtk_nand.o bmt.o nand-objs := nand_base.o nand_bbt.o nand_timings.o +diff --git a/drivers/mtd/nand/bmt.c b/drivers/mtd/nand/bmt.c +new file mode 100644 +index 0000000..0462871 --- /dev/null +++ b/drivers/mtd/nand/bmt.c @@ -0,0 +1,750 @@ @@ -804,6 +811,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_AUTHOR("MediaTek"); +MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver"); +#endif +diff --git a/drivers/mtd/nand/bmt.h b/drivers/mtd/nand/bmt.h +new file mode 100644 +index 0000000..2d30ea9 --- /dev/null +++ b/drivers/mtd/nand/bmt.h @@ -0,0 +1,80 @@ @@ -887,6 +897,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +unsigned short get_mapping_block_index(int index); + +#endif // #ifndef __BMT_H__ +diff --git a/drivers/mtd/nand/dev-nand.c b/drivers/mtd/nand/dev-nand.c +new file mode 100644 +index 0000000..9fb5235 --- /dev/null +++ b/drivers/mtd/nand/dev-nand.c @@ -0,0 +1,63 @@ @@ -953,6 +966,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + return retval; +} +arch_initcall(mtk_nand_register); +diff --git a/drivers/mtd/nand/mt6575_typedefs.h b/drivers/mtd/nand/mt6575_typedefs.h +new file mode 100644 +index 0000000..a7b9647 --- /dev/null +++ b/drivers/mtd/nand/mt6575_typedefs.h @@ -0,0 +1,340 @@ @@ -1296,6 +1312,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + +#endif // _MT6575_TYPEDEFS_H + +diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c +new file mode 100644 +index 0000000..00e150c --- /dev/null +++ b/drivers/mtd/nand/mtk_nand.c @@ -0,0 +1,2304 @@ @@ -3603,6 +3622,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +module_init(mtk_nand_init); +module_exit(mtk_nand_exit); +MODULE_LICENSE("GPL"); +diff --git a/drivers/mtd/nand/mtk_nand.h b/drivers/mtd/nand/mtk_nand.h +new file mode 100644 +index 0000000..6db88c4 --- /dev/null +++ b/drivers/mtd/nand/mtk_nand.h @@ -0,0 +1,452 @@ @@ -4058,9 +4080,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +extern u32 CFG_BLOCKSIZE; +#endif +#endif +diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c +index ceb68ca..04dbc69 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c -@@ -93,7 +93,7 @@ static struct nand_ecclayout nand_oob_12 +@@ -92,7 +92,7 @@ static struct nand_ecclayout nand_oob_128 = { .length = 78} } }; @@ -4069,7 +4093,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops); -@@ -131,7 +131,7 @@ static int check_offs_len(struct mtd_inf +@@ -130,7 +130,7 @@ static int check_offs_len(struct mtd_info *mtd, * * Release chip lock and wake up anyone waiting on the device. */ @@ -4078,7 +4102,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> { struct nand_chip *chip = mtd->priv; -@@ -803,7 +803,7 @@ static void panic_nand_get_device(struct +@@ -820,7 +820,7 @@ static void panic_nand_get_device(struct nand_chip *chip, * * Get the device and lock it for exclusive access */ @@ -4087,9 +4111,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> nand_get_device(struct mtd_info *mtd, int new_state) { struct nand_chip *chip = mtd->priv; +diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c +index 63a1a36..d036b9a 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c -@@ -1372,4 +1372,23 @@ int nand_markbad_bbt(struct mtd_info *mt +@@ -1374,4 +1374,23 @@ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) return ret; } @@ -4113,6 +4139,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +} + EXPORT_SYMBOL(nand_scan_bbt); +diff --git a/drivers/mtd/nand/nand_def.h b/drivers/mtd/nand/nand_def.h +new file mode 100644 +index 0000000..82e957d --- /dev/null +++ b/drivers/mtd/nand/nand_def.h @@ -0,0 +1,123 @@ @@ -4239,6 +4268,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#include "mt6575_typedefs.h" + +#endif /* __NAND_DEF_H__ */ +diff --git a/drivers/mtd/nand/nand_device_list.h b/drivers/mtd/nand/nand_device_list.h +new file mode 100644 +index 0000000..4c36b3a --- /dev/null +++ b/drivers/mtd/nand/nand_device_list.h @@ -0,0 +1,55 @@ @@ -4297,6 +4329,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + + +#endif +diff --git a/drivers/mtd/nand/partition.h b/drivers/mtd/nand/partition.h +new file mode 100644 +index 0000000..034e1af --- /dev/null +++ b/drivers/mtd/nand/partition.h @@ -0,0 +1,115 @@ @@ -4415,3 +4450,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +//#endif +#undef RECONFIG_PARTITION_SIZE + +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0075-mtk_nand_alloc_buffer.patch b/target/linux/ramips/patches-4.3/0040-nand-add-mtk-nand-hack-hook.patch index ac20198ace..51fd8ee6a4 100644 --- a/target/linux/ramips/patches-3.18/0075-mtk_nand_alloc_buffer.patch +++ b/target/linux/ramips/patches-4.3/0040-nand-add-mtk-nand-hack-hook.patch @@ -1,38 +1,21 @@ -From patchwork Fri Nov 13 07:55:08 2015 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [OpenWrt-Devel,RFC] A patch for mt7621 nand controler. Revision 2. -From: Kirill Berezin <fyiwdt@gmail.com> -X-Patchwork-Id: 544092 -Message-Id: <CAOFwh=DZieEa4ZA0ex6G3OR2OgEeP6Fh+SSw=Zg-L0wWm1QRTA@mail.gmail.com> -To: openwrt-devel@lists.openwrt.org -Date: Fri, 13 Nov 2015 10:55:08 +0300 +From 61e17c2f864698033f4661e1fc7ba63d4d982491 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:21:55 +0100 +Subject: [PATCH 40/53] nand: add mtk-nand hack/hook -Hello, +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/mtd/nand/mtk_nand.c | 34 ++++++++++++++++++++++++++++++---- + drivers/mtd/nand/nand_base.c | 9 ++++++++- + drivers/mtd/nand/nand_device_list.h | 2 ++ + include/linux/mtd/nand.h | 4 ++++ + 4 files changed, 44 insertions(+), 5 deletions(-) -It turned out that mtk_nand driver uses some sophisticated accounting and a -general nand code must be patched. - -This patch adds required read and erase calls to a general nand code. I -used a code for re6500 released by Linksys as a reference. - -All required operations (erase, write and read) are usable. However I found -that jffs2 filesystem can be created only on top of a ubi volume. I tried -to create jffs2 directly on mtd device but pages with clean markers are -became uncorrectable. - -This patch also includes changes that I sent earlier. - -Best regards, -Kirill. - -Signed-off-by: Kirill Berezin (fyiwdt@gmail.com) - -diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c ---- a/drivers/mtd/nand/mtk_nand.c 2015-11-06 16:44:31.000000000 +0400 -+++ b/drivers/mtd/nand/mtk_nand.c 2015-11-12 10:06:20.080430855 +0400 -@@ -110,6 +110,10 @@ +diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c +index 00e150c..808e9c3 100644 +--- a/drivers/mtd/nand/mtk_nand.c ++++ b/drivers/mtd/nand/mtk_nand.c +@@ -110,6 +110,10 @@ int part_num = NUM_PARTITIONS; int manu_id; int dev_id; @@ -43,7 +26,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c static u8 local_oob_buf[NAND_MAX_OOBSIZE]; static u8 nand_badblock_offset = 0; -@@ -348,7 +352,7 @@ +@@ -348,7 +352,7 @@ mtk_nand_check_bch_error(struct mtd_info *mtd, u8 * pDataBuf, u32 u4SecIndex, u3 if (0xF == u4ErrNum) { mtd->ecc_stats.failed++; bRet = false; @@ -52,7 +35,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c } else { for (i = 0; i < ((u4ErrNum + 1) >> 1); ++i) { au4ErrBitLoc[i] = DRV_Reg32(ECC_DECEL0_REG32 + i); -@@ -1422,7 +1426,7 @@ +@@ -1422,7 +1426,7 @@ mtk_nand_erase_hw(struct mtd_info *mtd, int page) { struct nand_chip *chip = (struct nand_chip *)mtd->priv; @@ -61,7 +44,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c return chip->waitfunc(mtd, chip); } -@@ -2094,8 +2098,8 @@ +@@ -2094,8 +2098,8 @@ mtk_nand_probe(struct platform_device *pdev) nand_chip->write_page = mtk_nand_write_page; nand_chip->ecc.write_oob = mtk_nand_write_oob; nand_chip->block_markbad = mtk_nand_block_markbad; // need to add nand_get_device()/nand_release_device(). @@ -72,7 +55,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c nand_chip->ecc.read_oob = mtk_nand_read_oob; nand_chip->block_bad = mtk_nand_block_bad; -@@ -2175,6 +2179,21 @@ +@@ -2175,6 +2179,21 @@ mtk_nand_probe(struct platform_device *pdev) nand_chip->pagemask = (nand_chip->chipsize >> nand_chip->page_shift) - 1; nand_chip->phys_erase_shift = ffs(mtd->erasesize) - 1; nand_chip->chip_shift = ffs(nand_chip->chipsize) - 1;//0x1C;//ffs(nand_chip->chipsize) - 1; @@ -94,7 +77,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c nand_chip->oob_poi = nand_chip->buffers->databuf + mtd->writesize; nand_chip->badblockpos = 0; -@@ -2251,6 +2270,9 @@ +@@ -2251,6 +2270,9 @@ out: MSG(INIT, "[NFI] mtk_nand_probe fail, err = %d!\n", err); nand_release(mtd); platform_set_drvdata(pdev, NULL); @@ -104,7 +87,7 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c kfree(host); nand_disable_clock(); return err; -@@ -2261,8 +2283,12 @@ +@@ -2261,8 +2283,12 @@ mtk_nand_remove(struct platform_device *pdev) { struct mtk_nand_host *host = platform_get_drvdata(pdev); struct mtd_info *mtd = &host->mtd; @@ -117,10 +100,11 @@ diff -urNb a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c kfree(host); nand_disable_clock(); -diff -urNb a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c ---- a/drivers/mtd/nand/nand_base.c 2015-11-06 16:44:31.000000000 +0400 -+++ b/drivers/mtd/nand/nand_base.c 2015-11-09 10:24:52.931720862 +0400 -@@ -1575,6 +1575,9 @@ +diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c +index 04dbc69..c5ed6fc 100644 +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -1592,6 +1592,9 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, __func__, buf); read_retry: @@ -130,7 +114,7 @@ diff -urNb a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); /* -@@ -1593,6 +1596,7 @@ +@@ -1610,6 +1613,7 @@ read_retry: else ret = chip->ecc.read_page(mtd, chip, bufpoi, oob_required, page); @@ -138,7 +122,7 @@ diff -urNb a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c if (ret < 0) { if (use_bufpoi) /* Invalidate page cache */ -@@ -2770,8 +2774,11 @@ +@@ -2786,8 +2790,11 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, if (page <= chip->pagebuf && chip->pagebuf < (page + pages_per_block)) chip->pagebuf = -1; @@ -151,10 +135,11 @@ diff -urNb a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c /* * See if operation failed and additional status checks are -diff -urNb a/drivers/mtd/nand/nand_device_list.h b/drivers/mtd/nand/nand_device_list.h ---- a/drivers/mtd/nand/nand_device_list.h 2015-11-06 16:44:31.000000000 +0400 -+++ b/drivers/mtd/nand/nand_device_list.h 2015-11-06 11:13:26.000000000 +0400 -@@ -43,6 +43,8 @@ +diff --git a/drivers/mtd/nand/nand_device_list.h b/drivers/mtd/nand/nand_device_list.h +index 4c36b3a..267fd0c 100644 +--- a/drivers/mtd/nand/nand_device_list.h ++++ b/drivers/mtd/nand/nand_device_list.h +@@ -43,6 +43,8 @@ static const flashdev_info gen_FlashTable[]={ {0xADBC, 0x905554, 5, 16, 512, 128, 2048, 64, 0x10801011, "H9DA4GH4JJAMC", 0}, {0x01F1, 0x801D01, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "S34ML01G100TF", 0}, {0x92F1, 0x8095FF, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "F59L1G81A", 0}, @@ -163,10 +148,11 @@ diff -urNb a/drivers/mtd/nand/nand_device_list.h b/drivers/mtd/nand/nand_device_ {0xECD3, 0x519558, 5, 8, 1024, 128, 2048, 64, 0x44333, "K9K8G8000", 0}, {0xC2F1, 0x801DC2, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "MX30LF1G08AA", 0}, {0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 224, 0x00C25332, "TC58NVG3S0F", 0}, -diff -urNb a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h ---- a/include/linux/mtd/nand.h 2015-11-06 16:44:30.000000000 +0400 -+++ b/include/linux/mtd/nand.h 2015-11-09 10:18:55.704701886 +0400 -@@ -653,6 +653,10 @@ +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index 272f429..b633b84 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -671,6 +671,10 @@ struct nand_chip { int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, int data_len, const uint8_t *buf, int oob_required, int page, int cached, int raw); @@ -177,3 +163,6 @@ diff -urNb a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, int feature_addr, uint8_t *subfeature_para); int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0049-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-4.3/0041-DT-Add-documentation-for-spi-rt2880.patch index 23a6b3eadc..100465f1fa 100644 --- a/target/linux/ramips/patches-3.18/0049-DT-Add-documentation-for-spi-rt2880.patch +++ b/target/linux/ramips/patches-4.3/0041-DT-Add-documentation-for-spi-rt2880.patch @@ -1,7 +1,7 @@ -From 6ed8d03e5f4283b60dffea5c10ff1484141824e7 Mon Sep 17 00:00:00 2001 +From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Fri, 9 Aug 2013 20:12:59 +0200 -Subject: [PATCH 49/57] DT: Add documentation for spi-rt2880 +Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880 Describe the SPI master found on the MIPS based Ralink RT2880 SoC. @@ -11,6 +11,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt +diff --git a/Documentation/devicetree/bindings/spi/spi-rt2880.txt b/Documentation/devicetree/bindings/spi/spi-rt2880.txt +new file mode 100644 +index 0000000..068bc90 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt @@ -0,0 +1,28 @@ @@ -42,3 +45,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + }; + }; + +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-4.3/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch index 57986d33fe..92438ff424 100644 --- a/target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-4.3/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch @@ -1,7 +1,7 @@ -From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001 +From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 11:15:12 +0100 -Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver +Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver Add the driver needed to make SPI work on Ralink SoC. @@ -10,13 +10,15 @@ Acked-by: John Crispin <blogic@openwrt.org> --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + - drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 439 insertions(+) + drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 537 insertions(+) create mode 100644 drivers/spi/spi-rt2880.c +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 4887f31..7c592ce 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -433,6 +433,12 @@ config SPI_QUP +@@ -457,6 +457,12 @@ config SPI_QUP This driver can also be built as a module. If so, the module will be called spi_qup. @@ -29,16 +31,21 @@ Acked-by: John Crispin <blogic@openwrt.org> config SPI_S3C24XX tristate "Samsung S3C24XX series SPI" depends on ARCH_S3C24XX +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 6a7f6f9..3d690ef 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa - obj-$(CONFIG_SPI_QUP) += spi-qup.o +@@ -68,6 +68,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_SPI_RSPI) += spi-rspi.o +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o spi-s3c24xx-hw-y := spi-s3c24xx.o spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o +diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c +new file mode 100644 +index 0000000..c286c94 --- /dev/null +++ b/drivers/spi/spi-rt2880.c @@ -0,0 +1,530 @@ @@ -572,3 +579,6 @@ Acked-by: John Crispin <blogic@openwrt.org> +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>"); +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); +MODULE_LICENSE("GPL"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch b/target/linux/ramips/patches-4.3/0043-spi-add-mt7621-support.patch index 5aa119e1df..716168f101 100644 --- a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch +++ b/target/linux/ramips/patches-4.3/0043-spi-add-mt7621-support.patch @@ -1,6 +1,21 @@ +From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 27 Jul 2014 09:49:07 +0100 +Subject: [PATCH 43/53] spi: add mt7621 support + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/spi/Kconfig | 6 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 487 insertions(+) + create mode 100644 drivers/spi/spi-mt7621.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 7c592ce..2f05c85 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -439,6 +439,12 @@ config SPI_RT2880 +@@ -463,6 +463,12 @@ config SPI_RT2880 help This selects a driver for the Ralink RT288x/RT305x SPI Controller. @@ -13,16 +28,21 @@ config SPI_S3C24XX tristate "Samsung S3C24XX series SPI" depends on ARCH_S3C24XX +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 3d690ef..5389710 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70l - obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o +@@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o + obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o +diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c +new file mode 100644 +index 0000000..dedf4a1 --- /dev/null +++ b/drivers/spi/spi-mt7621.c @@ -0,0 +1,480 @@ @@ -506,3 +526,6 @@ +MODULE_DESCRIPTION("MT7621 SPI driver"); +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>"); +MODULE_LICENSE("GPL"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0052-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-4.3/0044-i2c-MIPS-adds-ralink-I2C-driver.patch index 5618652dff..f600bd570e 100644 --- a/target/linux/ramips/patches-3.18/0052-i2c-MIPS-adds-ralink-I2C-driver.patch +++ b/target/linux/ramips/patches-4.3/0044-i2c-MIPS-adds-ralink-I2C-driver.patch @@ -1,18 +1,21 @@ -From 225f36695bb07dad9510f9affd79e63f1a44a195 Mon Sep 17 00:00:00 2001 +From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 09:52:56 +0100 -Subject: [PATCH 52/57] i2c: MIPS: adds ralink I2C driver +Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver Signed-off-by: John Crispin <blogic@openwrt.org> --- .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++ drivers/i2c/busses/Kconfig | 4 + drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-ralink.c | 274 ++++++++++++++++++++ - 4 files changed, 306 insertions(+) + drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++ + 4 files changed, 359 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt create mode 100644 drivers/i2c/busses/i2c-ralink.c +diff --git a/Documentation/devicetree/bindings/i2c/i2c-ralink.txt b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt +new file mode 100644 +index 0000000..8fa8ac3 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt @@ -0,0 +1,27 @@ @@ -43,9 +46,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + }; + }; +}; +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 08b8617..53d565b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -711,6 +711,10 @@ config I2C_RK3X +@@ -803,6 +803,10 @@ config I2C_RK3X This driver can also be built as a module. If so, the module will be called i2c-rk3x. @@ -56,9 +61,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> config HAVE_S3C2410_I2C bool help +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index 6df3b30..2edd32c 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile -@@ -66,6 +66,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o +@@ -75,6 +75,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o obj-$(CONFIG_I2C_PXA) += i2c-pxa.o obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o @@ -66,6 +73,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_I2C_QUP) += i2c-qup.o obj-$(CONFIG_I2C_RIIC) += i2c-riic.o obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o +diff --git a/drivers/i2c/busses/i2c-ralink.c b/drivers/i2c/busses/i2c-ralink.c +new file mode 100644 +index 0000000..debfb18 --- /dev/null +++ b/drivers/i2c/busses/i2c-ralink.c @@ -0,0 +1,327 @@ @@ -396,3 +406,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_DESCRIPTION("Ralink I2c host driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:Ralink-I2C"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0074-i2c-MIPS-add-mt7621-I2C-driver.patch b/target/linux/ramips/patches-4.3/0045-i2c-add-mt7621-driver.patch index 9b9a72bc7b..17ff8d2bb2 100644 --- a/target/linux/ramips/patches-3.18/0074-i2c-MIPS-add-mt7621-I2C-driver.patch +++ b/target/linux/ramips/patches-4.3/0045-i2c-add-mt7621-driver.patch @@ -1,6 +1,21 @@ +From d5c54ff3d1db0a4348fa04d8e78f3bf6063e3afc Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:21:27 +0100 +Subject: [PATCH 45/53] i2c: add mt7621 driver + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/i2c/busses/Kconfig | 4 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-mt7621.c | 303 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 308 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-mt7621.c + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 53d565b..073bfe3 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -715,6 +715,10 @@ config I2C_RALINK +@@ -807,6 +807,10 @@ config I2C_RALINK tristate "Ralink I2C Controller" select OF_I2C @@ -11,9 +26,11 @@ config HAVE_S3C2410_I2C bool help +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index 2edd32c..764e16e 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile -@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o +@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o obj-$(CONFIG_I2C_PXA) += i2c-pxa.o obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o @@ -21,6 +38,9 @@ obj-$(CONFIG_I2C_QUP) += i2c-qup.o obj-$(CONFIG_I2C_RIIC) += i2c-riic.o obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o +diff --git a/drivers/i2c/busses/i2c-mt7621.c b/drivers/i2c/busses/i2c-mt7621.c +new file mode 100644 +index 0000000..646ca40 --- /dev/null +++ b/drivers/i2c/busses/i2c-mt7621.c @@ -0,0 +1,303 @@ @@ -327,3 +347,6 @@ +MODULE_DESCRIPTION("MT7621 I2c host driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:MT7621-I2C"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0053-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-4.3/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch index 2932eb6b07..dac572f336 100644 --- a/target/linux/ramips/patches-3.18/0053-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ b/target/linux/ramips/patches-4.3/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch @@ -1,7 +1,7 @@ -From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001 +From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Thu, 13 Nov 2014 19:08:40 +0100 -Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC +Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -11,10 +11,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org> drivers/mmc/host/mtk-mmc/Makefile | 42 + drivers/mmc/host/mtk-mmc/board.h | 137 ++ drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++ - drivers/mmc/host/mtk-mmc/dbg.h | 153 ++ + drivers/mmc/host/mtk-mmc/dbg.h | 156 ++ drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++ - drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++ - 9 files changed, 4740 insertions(+) + drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++ + 9 files changed, 4762 insertions(+) create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig create mode 100644 drivers/mmc/host/mtk-mmc/Makefile create mode 100644 drivers/mmc/host/mtk-mmc/board.h @@ -23,14 +23,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org> create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h create mode 100644 drivers/mmc/host/mtk-mmc/sd.c +diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig +index 8a1e349..47833d1 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig -@@ -773,3 +773,5 @@ config MMC_SUNXI - help - This selects support for the SD/MMC Host Controller on - Allwinner sunxi SoCs. +@@ -793,3 +793,5 @@ config MMC_MTK + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + +source "drivers/mmc/host/mtk-mmc/Kconfig" +diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile +index 4f3452a..69dd05f 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -2,6 +2,7 @@ @@ -41,6 +45,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_MMC_ARMMMCI) += mmci.o obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o obj-$(CONFIG_MMC_PXA) += pxamci.o +diff --git a/drivers/mmc/host/mtk-mmc/Kconfig b/drivers/mmc/host/mtk-mmc/Kconfig +new file mode 100644 +index 0000000..a58b0f3 --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/Kconfig @@ -0,0 +1,16 @@ @@ -60,6 +67,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + bool "eMMC 8-bit support" + depends on MTK_MMC && RALINK_MT7628 + +diff --git a/drivers/mmc/host/mtk-mmc/Makefile b/drivers/mmc/host/mtk-mmc/Makefile +new file mode 100644 +index 0000000..caead0b --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/Makefile @@ -0,0 +1,42 @@ @@ -105,6 +115,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + +clean: + @rm -f *.o modules.order .*.cmd +diff --git a/drivers/mmc/host/mtk-mmc/board.h b/drivers/mmc/host/mtk-mmc/board.h +new file mode 100644 +index 0000000..33bfc7b --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/board.h @@ -0,0 +1,137 @@ @@ -245,6 +258,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + +#endif /* __ARCH_ARM_MACH_BOARD_H */ + +diff --git a/drivers/mmc/host/mtk-mmc/dbg.c b/drivers/mmc/host/mtk-mmc/dbg.c +new file mode 100644 +index 0000000..4dc115b --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/dbg.c @@ -0,0 +1,347 @@ @@ -595,6 +611,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +} +EXPORT_SYMBOL_GPL(msdc_debug_proc_init); +#endif +diff --git a/drivers/mmc/host/mtk-mmc/dbg.h b/drivers/mmc/host/mtk-mmc/dbg.h +new file mode 100644 +index 0000000..e58c431 --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/dbg.h @@ -0,0 +1,156 @@ @@ -754,6 +773,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks); + +#endif +diff --git a/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/drivers/mmc/host/mtk-mmc/mt6575_sd.h +new file mode 100644 +index 0000000..e90c4f1 --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h @@ -0,0 +1,1001 @@ @@ -1758,6 +1780,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + +#endif + +diff --git a/drivers/mmc/host/mtk-mmc/sd.c b/drivers/mmc/host/mtk-mmc/sd.c +new file mode 100644 +index 0000000..d240b46 --- /dev/null +++ b/drivers/mmc/host/mtk-mmc/sd.c @@ -0,0 +1,3060 @@ @@ -4821,3 +4846,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>"); + +EXPORT_SYMBOL(msdc_6575_host); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0054-DMA-ralink-add-rt2880-dma-engine.patch b/target/linux/ramips/patches-4.3/0047-DMA-ralink-add-rt2880-dma-engine.patch index fa0f42f108..55a6b0a3d4 100644 --- a/target/linux/ramips/patches-3.18/0054-DMA-ralink-add-rt2880-dma-engine.patch +++ b/target/linux/ramips/patches-4.3/0047-DMA-ralink-add-rt2880-dma-engine.patch @@ -1,23 +1,24 @@ -From cf93418a4bd5e69f069a65da92537bd4d6191223 Mon Sep 17 00:00:00 2001 +From f1c4d9e622c800e1f38b3818f933ec7597d1ccfb Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 09:29:51 +0100 -Subject: [PATCH 54/57] DMA: ralink: add rt2880 dma engine +Subject: [PATCH 47/53] DMA: ralink: add rt2880 dma engine Signed-off-by: John Crispin <blogic@openwrt.org> --- drivers/dma/Kconfig | 6 + drivers/dma/Makefile | 1 + - drivers/dma/dmaengine.c | 26 ++ drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/dmaengine.h | 1 + - 5 files changed, 611 insertions(+) + 4 files changed, 585 insertions(+) create mode 100644 drivers/dma/ralink-gdma.c +diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig +index b458475..2d5ae4a 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig -@@ -409,6 +409,12 @@ config NBPFAXI_DMA - help - Support for "Type-AXI" NBPF DMA IPs from Renesas +@@ -40,6 +40,12 @@ config ASYNC_TX_ENABLE_CHANNEL_SWITCH + config ARCH_HAS_ASYNC_TX_FIND_CHANNEL + bool +config DMA_RALINK + tristate "RALINK DMA support" @@ -28,13 +29,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org> config DMA_ENGINE bool +diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile +index 7711a71..b33c434 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile -@@ -49,3 +49,4 @@ obj-y += xilinx/ - obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o - obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o - obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +@@ -65,5 +65,6 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o + obj-$(CONFIG_TI_EDMA) += edma.o + obj-$(CONFIG_XGENE_DMA) += xgene-dma.o + obj-$(CONFIG_ZX_DMA) += zx296702_dma.o +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o + + obj-y += xilinx/ +diff --git a/drivers/dma/ralink-gdma.c b/drivers/dma/ralink-gdma.c +new file mode 100644 +index 0000000..2c3cace --- /dev/null +++ b/drivers/dma/ralink-gdma.c @@ -0,0 +1,577 @@ @@ -615,13 +623,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); +MODULE_DESCRIPTION("GDMA4740 DMA driver"); +MODULE_LICENSE("GPLv2"); +diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h +index 7ea9184..d371bf1 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h -@@ -1058,6 +1058,7 @@ struct dma_chan *dma_request_slave_chann - const char *name); - struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); - void dma_release_channel(struct dma_chan *chan); +@@ -496,6 +496,7 @@ static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, + struct dmaengine_unmap_data * + dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); + void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); #else - static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) - { + static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, + struct dmaengine_unmap_data *unmap) +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0055-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-4.3/0048-asoc-add-mt7620-support.patch index b439b9d3b8..004eb68101 100644 --- a/target/linux/ramips/patches-3.18/0055-asoc-add-mt7620-support.patch +++ b/target/linux/ramips/patches-4.3/0048-asoc-add-mt7620-support.patch @@ -1,7 +1,7 @@ -From 241188942603dc73f62cf2553c53cae2235c9957 Mon Sep 17 00:00:00 2001 +From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 27 Jul 2014 09:31:47 +0100 -Subject: [PATCH 55/57] asoc: add mt7620 support +Subject: [PATCH 48/53] asoc: add mt7620 support Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -10,15 +10,16 @@ Signed-off-by: John Crispin <blogic@openwrt.org> sound/soc/Makefile | 1 + sound/soc/ralink/Kconfig | 15 ++ sound/soc/ralink/Makefile | 11 + - sound/soc/ralink/mt7620-i2s.c | 466 ++++++++++++++++++++++++++++++++++++++ - sound/soc/ralink/mt7620-wm8960.c | 125 ++++++++++ - sound/soc/soc-io.c | 10 - - 8 files changed, 621 insertions(+), 10 deletions(-) + sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++ + sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++ + 7 files changed, 699 insertions(+) create mode 100644 sound/soc/ralink/Kconfig create mode 100644 sound/soc/ralink/Makefile create mode 100644 sound/soc/ralink/mt7620-i2s.c create mode 100644 sound/soc/ralink/mt7620-wm8960.c +diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c +index da85bbf..371baa5 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -15,6 +15,7 @@ @@ -37,26 +38,33 @@ Signed-off-by: John Crispin <blogic@openwrt.org> __iomem void *rt_memc_membase; __iomem void *plat_of_remap_node(const char *node) +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 225bfda..76ce95c 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig -@@ -48,6 +48,7 @@ source "sound/soc/intel/Kconfig" - source "sound/soc/mxs/Kconfig" +@@ -53,6 +53,7 @@ source "sound/soc/mxs/Kconfig" source "sound/soc/pxa/Kconfig" + source "sound/soc/qcom/Kconfig" source "sound/soc/rockchip/Kconfig" +source "sound/soc/ralink/Kconfig" source "sound/soc/samsung/Kconfig" source "sound/soc/sh/Kconfig" source "sound/soc/sirf/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 134aca1..e9d8e0e 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile -@@ -25,6 +25,7 @@ obj-$(CONFIG_SND_SOC) += omap/ - obj-$(CONFIG_SND_SOC) += kirkwood/ +@@ -35,6 +35,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/ obj-$(CONFIG_SND_SOC) += pxa/ + obj-$(CONFIG_SND_SOC) += qcom/ obj-$(CONFIG_SND_SOC) += rockchip/ +obj-$(CONFIG_SND_SOC) += ralink/ obj-$(CONFIG_SND_SOC) += samsung/ obj-$(CONFIG_SND_SOC) += sh/ obj-$(CONFIG_SND_SOC) += sirf/ +diff --git a/sound/soc/ralink/Kconfig b/sound/soc/ralink/Kconfig +new file mode 100644 +index 0000000..d462622 --- /dev/null +++ b/sound/soc/ralink/Kconfig @@ -0,0 +1,15 @@ @@ -75,6 +83,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + help + Say Y if you want to add support for ASoC audio on the Qi LB60 board + a.k.a Qi Ben NanoNote. +diff --git a/sound/soc/ralink/Makefile b/sound/soc/ralink/Makefile +new file mode 100644 +index 0000000..3d79980 --- /dev/null +++ b/sound/soc/ralink/Makefile @@ -0,0 +1,11 @@ @@ -89,6 +100,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o + +obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o +diff --git a/sound/soc/ralink/mt7620-i2s.c b/sound/soc/ralink/mt7620-i2s.c +new file mode 100644 +index 0000000..2ce9b21 --- /dev/null +++ b/sound/soc/ralink/mt7620-i2s.c @@ -0,0 +1,436 @@ @@ -528,6 +542,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:mt7620-i2s"); +diff --git a/sound/soc/ralink/mt7620-wm8960.c b/sound/soc/ralink/mt7620-wm8960.c +new file mode 100644 +index 0000000..3389988 --- /dev/null +++ b/sound/soc/ralink/mt7620-wm8960.c @@ -0,0 +1,233 @@ @@ -764,3 +781,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_DESCRIPTION("Freescale i.MX WM8962 ASoC machine driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:mt7620-wm8962"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0056-watchdog-add-MT7621-support.patch b/target/linux/ramips/patches-4.3/0049-watchdog-add-MT7621-support.patch index 9a079d8e38..0d410bb28a 100644 --- a/target/linux/ramips/patches-3.18/0056-watchdog-add-MT7621-support.patch +++ b/target/linux/ramips/patches-4.3/0049-watchdog-add-MT7621-support.patch @@ -1,7 +1,7 @@ -From 6a42dd698ddf91b6e9902b17e21dc13c6ae412ff Mon Sep 17 00:00:00 2001 +From 77fe64de72317c0e090d82056e7a6a073f2972b4 Mon Sep 17 00:00:00 2001 From: John Crispin <blogic@openwrt.org> Date: Sun, 16 Mar 2014 05:24:42 +0000 -Subject: [PATCH 56/57] watchdog: add MT7621 support +Subject: [PATCH 49/53] watchdog: add MT7621 support Signed-off-by: John Crispin <blogic@openwrt.org> --- @@ -11,9 +11,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org> 3 files changed, 193 insertions(+) create mode 100644 drivers/watchdog/mt7621_wdt.c +diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig +index 79e1aa1..0710aa1 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig -@@ -1257,6 +1257,13 @@ config RALINK_WDT +@@ -1337,6 +1337,13 @@ config RALINK_WDT help Hardware driver for the Ralink SoC Watchdog Timer. @@ -27,16 +29,21 @@ Signed-off-by: John Crispin <blogic@openwrt.org> # PARISC Architecture # POWERPC Architecture +diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile +index 0c616e3..4d3b4b1 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile -@@ -143,6 +143,7 @@ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o - obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o - obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o +@@ -68,6 +68,7 @@ obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o + obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o + obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o + obj-$(CONFIG_LPC18XX_WATCHDOG) += lpc18xx_wdt.o +obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o - # PARISC Architecture - + # AVR32 Architecture + obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o +diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c +new file mode 100644 +index 0000000..ec2c897 --- /dev/null +++ b/drivers/watchdog/mt7621_wdt.c @@ -0,0 +1,185 @@ @@ -225,3 +232,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_AUTHOR("John Crispin <blogic@openwrt.org"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0303-alsa.patch b/target/linux/ramips/patches-4.3/0050-alsa-add-ralink-sdk-driver.patch index d6d489249f..1048396231 100644 --- a/target/linux/ramips/patches-3.18/0303-alsa.patch +++ b/target/linux/ramips/patches-4.3/0050-alsa-add-ralink-sdk-driver.patch @@ -1,23 +1,72 @@ +From f98ffa1f01240407e39c1b53135312db73f044c6 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:30:48 +0100 +Subject: [PATCH 50/53] alsa: add ralink sdk driver + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/codecs/Kconfig | 2 +- + sound/soc/codecs/wm8960.c | 120 +- + sound/soc/codecs/wm8960.h | 64 + + sound/soc/mtk/Kconfig | 35 + + sound/soc/mtk/Makefile | 39 + + sound/soc/mtk/i2c_wm8960.c | 492 ++++++ + sound/soc/mtk/i2c_wm8960.h | 288 ++++ + sound/soc/mtk/i2s_ctrl.c | 3524 ++++++++++++++++++++++++++++++++++++++++ + sound/soc/mtk/i2s_ctrl.h | 523 ++++++ + sound/soc/mtk/i2s_debug.c | 698 ++++++++ + sound/soc/mtk/mt76xx_i2s.c | 304 ++++ + sound/soc/mtk/mt76xx_i2s.h | 18 + + sound/soc/mtk/mt76xx_machine.c | 317 ++++ + sound/soc/mtk/mt76xx_machine.h | 21 + + sound/soc/mtk/mt76xx_pcm.c | 499 ++++++ + sound/soc/mtk/ralink_gdma.c | 918 +++++++++++ + sound/soc/mtk/ralink_gdma.h | 326 ++++ + sound/soc/soc-core.c | 3 +- + 20 files changed, 8174 insertions(+), 19 deletions(-) + create mode 100644 sound/soc/mtk/Kconfig + create mode 100644 sound/soc/mtk/Makefile + create mode 100644 sound/soc/mtk/i2c_wm8960.c + create mode 100644 sound/soc/mtk/i2c_wm8960.h + create mode 100644 sound/soc/mtk/i2s_ctrl.c + create mode 100644 sound/soc/mtk/i2s_ctrl.h + create mode 100644 sound/soc/mtk/i2s_debug.c + create mode 100644 sound/soc/mtk/mt76xx_i2s.c + create mode 100644 sound/soc/mtk/mt76xx_i2s.h + create mode 100644 sound/soc/mtk/mt76xx_machine.c + create mode 100644 sound/soc/mtk/mt76xx_machine.h + create mode 100644 sound/soc/mtk/mt76xx_pcm.c + create mode 100644 sound/soc/mtk/ralink_gdma.c + create mode 100644 sound/soc/mtk/ralink_gdma.h + +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 76ce95c..09aa2c7 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig -@@ -56,6 +56,7 @@ source "sound/soc/spear/Kconfig" - source "sound/soc/tegra/Kconfig" - source "sound/soc/txx9/Kconfig" +@@ -64,6 +64,7 @@ source "sound/soc/txx9/Kconfig" source "sound/soc/ux500/Kconfig" + source "sound/soc/xtensa/Kconfig" + source "sound/soc/zte/Kconfig" +source "sound/soc/mtk/Kconfig" # Supported codecs source "sound/soc/codecs/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index e9d8e0e..a3c6b43 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile -@@ -33,3 +33,4 @@ obj-$(CONFIG_SND_SOC) += spear/ - obj-$(CONFIG_SND_SOC) += tegra/ - obj-$(CONFIG_SND_SOC) += txx9/ +@@ -46,3 +46,4 @@ obj-$(CONFIG_SND_SOC) += txx9/ obj-$(CONFIG_SND_SOC) += ux500/ + obj-$(CONFIG_SND_SOC) += xtensa/ + obj-$(CONFIG_SND_SOC) += zte/ +obj-$(CONFIG_SND_SOC) += mtk/ +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 0c9733e..276a4c5 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig -@@ -725,7 +725,7 @@ config SND_SOC_WM8955 +@@ -816,7 +816,7 @@ config SND_SOC_WM8955 tristate config SND_SOC_WM8960 @@ -26,6 +75,316 @@ config SND_SOC_WM8961 tristate +diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c +index dbd8840..3118f5c 100644 +--- a/sound/soc/codecs/wm8960.c ++++ b/sound/soc/codecs/wm8960.c +@@ -27,6 +27,7 @@ + #include <sound/wm8960.h> + + #include "wm8960.h" ++#include "../mtk/i2c_wm8960.h" + + /* R25 - Power 1 */ + #define WM8960_VMID_MASK 0x180 +@@ -57,10 +58,10 @@ static int wm8960_set_pll(struct snd_soc_codec *codec, + * using 2 wire for device control, so we cache them instead. + */ + static const struct reg_default wm8960_reg_defaults[] = { +- { 0x0, 0x00a7 }, +- { 0x1, 0x00a7 }, +- { 0x2, 0x0000 }, +- { 0x3, 0x0000 }, ++ { 0x0, 0x002b }, ++ { 0x1, 0x002b }, ++ { 0x2, 0x00ff }, ++ { 0x3, 0x00ff }, + { 0x4, 0x0000 }, + { 0x5, 0x0008 }, + { 0x6, 0x0000 }, +@@ -92,8 +93,8 @@ static const struct reg_default wm8960_reg_defaults[] = { + { 0x25, 0x0050 }, + { 0x26, 0x0000 }, + { 0x27, 0x0000 }, +- { 0x28, 0x0000 }, +- { 0x29, 0x0000 }, ++ { 0x28, 0x007b }, ++ { 0x29, 0x007b }, + { 0x2a, 0x0040 }, + { 0x2b, 0x0000 }, + { 0x2c, 0x0000 }, +@@ -138,7 +139,15 @@ struct wm8960_priv { + struct wm8960_data pdata; + }; + ++#if 1 ++#define wm8960_reset(c) do{ \ ++ int i = 0;\ ++ snd_soc_write(c, WM8960_RESET, 0);\ ++ for(i = 0; i < 1000*HZ; i++);\ ++ }while(0) ++#else + #define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0) ++#endif + + /* enumerated controls */ + static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", +@@ -192,8 +201,8 @@ static int wm8960_get_deemph(struct snd_kcontrol *kcontrol, + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); + +- ucontrol->value.integer.value[0] = wm8960->deemph; +- return 0; ++ //ucontrol->value.integer.value[0] = wm8960->deemph; ++ return wm8960->deemph; + } + + static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, +@@ -211,6 +220,71 @@ static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, + return wm8960_set_deemph(codec); + } + ++static int wm8960_preinit(struct snd_soc_codec *codec) ++{ ++ //printk("****** %s ******\n", __func__); ++ snd_soc_write(codec, WM8960_RESET, 0); ++ mdelay(500); ++ ++ return 0; ++} ++ ++static int wm8960_postinit(struct snd_soc_codec *codec) ++{ ++ u32 data; ++ //printk("****** %s ******\n", __func__); ++ // In ++ data = snd_soc_read(codec, WM8960_POWER1); ++ snd_soc_write(codec, WM8960_POWER1, data|WM8960_PWR1_ADCL|WM8960_PWR1_ADCR|WM8960_PWR1_AINL |WM8960_PWR1_AINR|WM8960_PWR1_MICB);//0x19 ++ data = snd_soc_read(codec, WM8960_ADDCTL1); ++ snd_soc_write(codec, WM8960_ADDCTL1, data|ADDITIONAL1_DATSEL(0x01));//0x17 ++ snd_soc_write(codec, WM8960_LADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x15 ++ snd_soc_write(codec, WM8960_RADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x16 ++ snd_soc_write(codec, WM8960_LINPATH, 0x148);//0x20 ++ snd_soc_write(codec, WM8960_RINPATH, 0x148);//0x21 ++ snd_soc_write(codec, WM8960_POWER3, WM8960_PWR3_LMIC|WM8960_PWR3_RMIC);//0x2f ++ ++ // Out ++ data = snd_soc_read(codec, WM8960_POWER2); ++ snd_soc_write(codec, WM8960_POWER2, data|WM8960_PWR2_DACL|WM8960_PWR2_DACR|WM8960_PWR2_LOUT1|WM8960_PWR2_ROUT1|WM8960_PWR2_SPKL|WM8960_PWR2_SPKR);//0x1a ++ mdelay(10); ++ snd_soc_write(codec, WM8960_IFACE2, 0x40); ++ snd_soc_write(codec, WM8960_LDAC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff));//0x0a ++ snd_soc_write(codec, WM8960_RDAC, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff));//0x0b ++ snd_soc_write(codec, WM8960_LOUTMIX, 0x100);//0x22 ++ snd_soc_write(codec, WM8960_ROUTMIX, 0x100);//0x25 ++ ++ data = snd_soc_read(codec, WM8960_POWER3); ++ snd_soc_write(codec, WM8960_POWER3, data|WM8960_PWR3_ROMIX|WM8960_PWR3_LOMIX);//0x2f ++ ++ snd_soc_write(codec, WM8960_CLASSD1, 0xf7);//0x31 ++ snd_soc_write(codec, WM8960_CLASSD3, 0xad);//0x33 ++ snd_soc_write(codec, WM8960_DACCTL1, 0x000);//0x05 ++ ++ data = snd_soc_read(codec, WM8960_POWER1); ++ snd_soc_write(codec, WM8960_POWER1, data|0x1c0);//0x19 ++ ++ ++ snd_soc_write(codec, WM8960_LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(115));//0x02 ++ snd_soc_write(codec, WM8960_ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(115));//0x03 ++ ++ snd_soc_write(codec, WM8960_LINVOL, LINV_IPVU|LINV_LINVOL(110)); //LINV(0x00)=>0x12b ++ snd_soc_write(codec, WM8960_RINVOL, RINV_IPVU|RINV_RINVOL(110)); //LINV(0x01)=>0x12b ++ ++ return 0; ++} ++ ++static int wm8960_close(struct snd_soc_codec *codec) ++{ ++ snd_soc_write(codec, WM8960_DACCTL1,0x8); //0x05->0x08 ++ snd_soc_write(codec, WM8960_POWER1, 0x000); //0x19->0x000 ++ mdelay(300); ++ snd_soc_write(codec, WM8960_POWER2, 0x000); //0x1a->0x000 ++ ++ return 0; ++} ++ ++ + static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1); + static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0); + static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); +@@ -563,6 +637,7 @@ static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai, + + /* set iface */ + snd_soc_write(codec, WM8960_IFACE1, iface); ++ wm8960_postinit(codec); + return 0; + } + +@@ -809,9 +884,10 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, + ret = wm8960_configure_clocking(codec); + if (ret) + return ret; +- ++#if 0 + /* Set VMID to 2x50k */ + snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80); ++#endif + break; + + case SND_SOC_BIAS_ON: +@@ -852,12 +928,16 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, + /* Disable anti-pop features */ + snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN); + } +- ++#if 0 + /* Set VMID to 2x250k */ + snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100); ++#endif + break; + + case SND_SOC_BIAS_OFF: ++#if 1 ++ wm8960_close(codec); ++#else + /* Enable anti-pop features */ + snd_soc_write(codec, WM8960_APOP1, + WM8960_POBCTRL | WM8960_SOFT_ST | +@@ -866,6 +946,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, + /* Disable VMID and VREF, let them discharge */ + snd_soc_write(codec, WM8960_POWER1, 0); + msleep(600); ++#endif + break; + } + +@@ -1101,10 +1182,15 @@ static int wm8960_set_pll(struct snd_soc_codec *codec, + + if (pll_div.k) { + reg |= 0x20; +- ++#if 1 + snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); + snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); + snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); ++#else ++ snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); ++ snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); ++ snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); ++#endif + } + snd_soc_write(codec, WM8960_PLL1, reg); + +@@ -1150,7 +1236,11 @@ static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + snd_soc_write(codec, WM8960_PLL1, reg | div); + break; + case WM8960_DCLKDIV: ++#if 1 + reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; ++#else ++ reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; ++#endif + snd_soc_write(codec, WM8960_CLOCK2, reg | div); + break; + case WM8960_TOCLKSEL: +@@ -1285,7 +1375,7 @@ static int wm8960_i2c_probe(struct i2c_client *i2c, + { + struct wm8960_data *pdata = dev_get_platdata(&i2c->dev); + struct wm8960_priv *wm8960; +- int ret; ++ int ret - 0; + + wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv), + GFP_KERNEL); +@@ -1307,11 +1397,7 @@ static int wm8960_i2c_probe(struct i2c_client *i2c, + else if (i2c->dev.of_node) + wm8960_set_pdata_from_of(i2c, &wm8960->pdata); + +- ret = wm8960_reset(wm8960->regmap); +- if (ret != 0) { +- dev_err(&i2c->dev, "Failed to issue reset\n"); +- return ret; +- } ++ wm8960_reset(wm8960->regmap); + + if (wm8960->pdata.shared_lrclk) { + ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, +diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h +index ab3220d..5205deb 100644 +--- a/sound/soc/codecs/wm8960.h ++++ b/sound/soc/codecs/wm8960.h +@@ -111,4 +111,68 @@ + #define WM8960_OPCLK_DIV_5_5 (4 << 0) + #define WM8960_OPCLK_DIV_6 (5 << 0) + ++/* ++ * WM8960 Power management ++ */ ++#define WM8960_PWR1_VMIDSEL_DISABLED (0 << 7) ++#define WM8960_PWR1_VMIDSEL_50K (1 << 7) ++#define WM8960_PWR1_VMIDSEL_250K (2 << 7) ++#define WM8960_PWR1_VMIDSEL_5K (3 << 7) ++#define WM8960_PWR1_VREF (1 << 6) ++#define WM8960_PWR1_AINL (1 << 5) ++#define WM8960_PWR1_AINR (1 << 4) ++#define WM8960_PWR1_ADCL (1 << 3) ++#define WM8960_PWR1_ADCR (1 << 2) ++#define WM8960_PWR1_MICB (1 << 1) ++#define WM8960_PWR1_DIGENB (1 << 0) ++ ++#define WM8960_PWR2_DACL (1 << 8) ++#define WM8960_PWR2_DACR (1 << 7) ++//#define WM8960_PWR2_LOUT1 (1 << 6) ++//#define WM8960_PWR2_ROUT1 (1 << 5) ++#define WM8960_PWR2_SPKL (1 << 4) ++#define WM8960_PWR2_SPKR (1 << 3) ++//#define WM8960_PWR2_OUT3 (1 << 1) ++#define WM8960_PWR2_PLL_EN (1 << 0) ++ ++#define WM8960_PWR3_LMIC (1 << 5) ++#define WM8960_PWR3_RMIC (1 << 4) ++#define WM8960_PWR3_LOMIX (1 << 3) ++#define WM8960_PWR3_ROMIX (1 << 2) ++ ++#define LEFTGAIN 0x0a ++#define LEFTGAIN_LDVU (1 << 8) ++#define LEFTGAIN_LDACVOL(x) ((x) & 0xff) ++ ++#define RIGHTGAIN 0x0b ++#define RIGHTGAIN_RDVU (1 << 8) ++#define RIGHTGAIN_RDACVOL(x) ((x) & 0xff) ++ ++#define ADDITIONAL1_DATSEL(x) (((x) & 0x3) << 2) ++ ++#define AINTFCE1_WL_32 (3 << 2) ++#define AINTFCE1_WL_24 (2 << 2) ++#define AINTFCE1_WL_20 (1 << 2) ++#define AINTFCE1_WL_16 (0 << 2) ++#define AINTFCE1_FORMAT_I2S (2 << 0) ++ ++#define LOUT1_LO1VU (1 << 8) ++#define LOUT1_LO1ZC (1 << 7) ++#define LOUT1_LOUT1VOL(x) ((x) & 0x7f) ++ ++#define ROUT1_RO1VU (1 << 8) ++#define ROUT1_RO1ZC (1 << 7) ++#define ROUT1_ROUT1VOL(x) ((x) & 0x7f) ++ ++#define LINV_IPVU (1 << 8) /* FIXME */ ++ ++#define LINV_LINMUTE (1 << 7) ++#define LINV_LIZC (1 << 6) ++#define LINV_LINVOL(x) ((x) & 0x3f) ++ ++#define RINV_IPVU (1 << 8) /* FIXME */ ++#define RINV_RINMUTE (1 << 7) ++#define RINV_RIZC (1 << 6) ++#define RINV_RINVOL(x) ((x) & 0x3f) ++ + #endif +diff --git a/sound/soc/mtk/Kconfig b/sound/soc/mtk/Kconfig +new file mode 100644 +index 0000000..26d2531 --- /dev/null +++ b/sound/soc/mtk/Kconfig @@ -0,0 +1,35 @@ @@ -64,6 +423,9 @@ + tristate "MTK SoC I2S Support" + depends on SND_MT76XX_SOC + +diff --git a/sound/soc/mtk/Makefile b/sound/soc/mtk/Makefile +new file mode 100644 +index 0000000..00b3dff --- /dev/null +++ b/sound/soc/mtk/Makefile @@ -0,0 +1,39 @@ @@ -106,6 +468,9 @@ + + + +diff --git a/sound/soc/mtk/i2c_wm8960.c b/sound/soc/mtk/i2c_wm8960.c +new file mode 100644 +index 0000000..70f16e1 --- /dev/null +++ b/sound/soc/mtk/i2c_wm8960.c @@ -0,0 +1,492 @@ @@ -601,6 +966,9 @@ +MODULE_DESCRIPTION("WM8960 I2C client driver"); +MODULE_LICENSE("GPL"); + +diff --git a/sound/soc/mtk/i2c_wm8960.h b/sound/soc/mtk/i2c_wm8960.h +new file mode 100644 +index 0000000..c769345 --- /dev/null +++ b/sound/soc/mtk/i2c_wm8960.h @@ -0,0 +1,288 @@ @@ -892,6 +1260,9 @@ +void audiohw_bypass(void); + +#endif /* _WM875x_H */ +diff --git a/sound/soc/mtk/i2s_ctrl.c b/sound/soc/mtk/i2s_ctrl.c +new file mode 100644 +index 0000000..05034b0 --- /dev/null +++ b/sound/soc/mtk/i2s_ctrl.c @@ -0,0 +1,3524 @@ @@ -4419,6 +4790,9 @@ +#else +module_param (i2sdrv_major, int, 0); +#endif +diff --git a/sound/soc/mtk/i2s_ctrl.h b/sound/soc/mtk/i2s_ctrl.h +new file mode 100644 +index 0000000..b762c9c --- /dev/null +++ b/sound/soc/mtk/i2s_ctrl.h @@ -0,0 +1,523 @@ @@ -4945,6 +5319,713 @@ + +#endif /* __RALINK_I2S_H_ */ + +diff --git a/sound/soc/mtk/i2s_debug.c b/sound/soc/mtk/i2s_debug.c +new file mode 100644 +index 0000000..9f61b14 +--- /dev/null ++++ b/sound/soc/mtk/i2s_debug.c +@@ -0,0 +1,698 @@ ++#include <linux/init.h> ++#include <linux/version.h> ++#include <linux/module.h> ++#include <linux/kernel.h> /* printk() */ ++#include "i2s_ctrl.h" ++#include <linux/delay.h> ++#include <linux/jiffies.h> ++#include <linux/random.h> ++#include <linux/slab.h> ++#include <asm/uaccess.h> /* copy_from/to_user */ ++ ++#if defined(CONFIG_SND_RALINK_SOC) ++#include <sound/soc/mtk/mtk_audio_device.h> ++#endif ++ ++#if defined(CONFIG_I2S_WM8750) ++#include "../codec/i2c_wm8750.h" ++#endif ++#if defined(CONFIG_I2S_WM8751) ++#include "../codec/i2c_wm8751.h" ++#endif ++#if defined(CONFIG_I2S_WM8960) ++#include "i2c_wm8960.h" ++#endif ++ ++ ++//#define INTERNAL_LOOPBACK_DEBUG ++ ++extern unsigned long i2s_codec_12p288Mhz[11]; ++extern unsigned long i2s_codec_12Mhz[11]; ++#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) ++extern unsigned long i2s_inclk_int_16bit[13]; ++extern unsigned long i2s_inclk_comp_16bit[13]; ++extern unsigned long i2s_inclk_int_24bit[13]; ++extern unsigned long i2s_inclk_comp_24bit[13]; ++#else ++extern unsigned long i2s_inclk_int[11]; ++extern unsigned long i2s_inclk_comp[11]; ++#endif ++extern int i2s_pll_config_mt7621(unsigned long index); ++extern int i2s_pll_config_mt7623(unsigned long index); ++ ++#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++extern void audiohw_loopback(int fsel); ++extern void audiohw_bypass(void); ++extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r); ++extern int audiohw_set_linein_vol(int vol_l, int vol_r); ++#endif ++ ++#if defined(CONFIG_I2S_WM8960) ++extern void audiohw_codec_exlbk(void); ++#endif ++ ++unsigned long txbuffer[512] = { ++ 0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 1 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 2 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 3 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 4 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 5 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 6 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 7 ++0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, ++ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, ++ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, ++ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, ++ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, ++ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, ++ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, ++ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00 //round 8 ++ }; ++ ++int i2s_debug_cmd(unsigned int cmd, unsigned long arg) ++{ ++ unsigned long data, index; ++ unsigned long *pTable; ++ int i; ++ ++ switch(cmd) ++ { ++ case I2S_DEBUG_CLKGEN: ++ MSG("I2S_DEBUG_CLKGEN\n"); ++#if defined(CONFIG_RALINK_RT3052) ++ *(volatile unsigned long*)(0xB0000060) = 0x00000016; ++ *(volatile unsigned long*)(0xB0000030) = 0x00009E00; ++ *(volatile unsigned long*)(0xB0000A00) = 0xC0000040; ++#elif defined(CONFIG_RALINK_RT3350) ++ *(volatile unsigned long*)(0xB0000060) = 0x00000018; ++ *(volatile unsigned long*)(0xB000002C) = 0x00000100; ++ *(volatile unsigned long*)(0xB0000030) = 0x00009E00; ++ *(volatile unsigned long*)(0xB0000A00) = 0xC0000040; ++#elif defined(CONFIG_RALINK_RT3883) ++ *(volatile unsigned long*)(0xB0000060) = 0x00000018; ++ *(volatile unsigned long*)(0xB000002C) = 0x00003000; ++ *(volatile unsigned long*)(0xB0000A00) = 0xC1104040; ++ *(volatile unsigned long*)(0xB0000A24) = 0x00000027; ++ *(volatile unsigned long*)(0xB0000A20) = 0x80000020; ++#elif (defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)) || defined (CONFIG_RALINK_RT6855) ++ *(volatile unsigned long*)(0xB0000060) = 0x00000018; ++ *(volatile unsigned long*)(0xB000002C) = 0x00000300; ++ *(volatile unsigned long*)(0xB0000A00) = 0xC1104040; ++ *(volatile unsigned long*)(0xB0000A24) = 0x00000027; ++ *(volatile unsigned long*)(0xB0000A20) = 0x80000020; ++#elif defined(CONFIG_RALINK_RT6855A) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080; ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000027; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000020; ++#else ++//#error "I2S debug mode not support this Chip" ++#endif ++ break; ++ case I2S_DEBUG_INLBK: ++ MSG("I2S_DEBUG_INLBK\n"); ++#if defined(CONFIG_RALINK_MT7621) ++ switch(96000) ++ { ++ case 8000: ++ index = 0; ++ break; ++ case 11025: ++ index = 1; ++ break; ++ case 12000: ++ index = 2; ++ break; ++ case 16000: ++ index = 3; ++ break; ++ case 22050: ++ index = 4; ++ break; ++ case 24000: ++ index = 5; ++ break; ++ case 32000: ++ index = 6; ++ break; ++ case 44100: ++ index = 7; ++ break; ++ case 48000: ++ index = 8; ++ break; ++ case 88200: ++ index = 9; ++ break; ++ case 96000: ++ index = 10; ++ break; ++ case 192000: ++ index = 11; ++ break; ++ default: ++ index = 7; ++ } ++ i2s_pll_config_mt7621(index); ++#elif defined(CONFIG_ARCH_MT7623) ++ i2s_pll_config_mt7623(11); ++#endif ++ ++ ++#if defined(CONFIG_RALINK_RT3052) ++ break; ++#endif ++#if defined(CONFIG_RALINK_RT6855A) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) |= 0x00020000; ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) |= 0x00008080; ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; ++#elif defined(CONFIG_RALINK_MT7621) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000; ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000010; //GPIO purpose selection ++#elif defined(CONFIG_RALINK_MT7628) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000; ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) &= ~((0x3)<<6); //GPIO purpose selection /*FIXME*/ ++#elif defined(CONFIG_ARCH_MT7623) ++ *(volatile unsigned long*)(0xFB000034) |= 0x00020000; ++ *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule ++ ++ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<12); ++ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<12); ++ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<9); ++ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<9); ++ *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<10); ++ *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<9); ++ ++ *(volatile unsigned long*)(0xF00057F0) &= ~((0x7)<<12); ++ *(volatile unsigned long*)(0xF00057F0) |= ((0x6)<<12); ++ *(volatile unsigned long*)(0xF0005030) |= ((0x1)<<1); ++ ++ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<6); ++ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<6); ++ *(volatile unsigned long*)(0xF0005040) &= ~((0x1)<<8); ++ ++ *(volatile unsigned long*)(0xF00058F0) &= ~((0x7)<<3); ++ *(volatile unsigned long*)(0xF00058F0) |= ((0x6)<<3); ++ *(volatile unsigned long*)(0xF0005070) |= ((0x1)<<14); ++ ++ ++#else ++ *(volatile unsigned long*)(0xB0000034) |= 0x00020000; ++ *(volatile unsigned long*)(0xB0000034) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(0xB0000A00) &= 0x7FFFFFFF; //Rest I2S to default vaule ++ *(volatile unsigned long*)(0xB0000060) = 0x00000018; ++ ++#if defined(CONFIG_RALINK_RT3883) ++ *(volatile unsigned long*)(0xB000002C) = 0x00003000; ++#elif defined(CONFIG_ARCH_MT7623) ++ ++#else ++ *(volatile unsigned long*)(0xB000002C) = 0x00000300; ++#endif ++#endif ++#if defined(CONFIG_RALINK_MT7621) ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040; ++ ++ pTable = i2s_inclk_int; ++ data = pTable[index]; ++ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data; ++ i2s_outw(RALINK_I2S_BASE+0x24, data); ++ ++ pTable = i2s_inclk_comp; ++ data = pTable[index]; ++ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data; ++ i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000)); ++#elif defined(CONFIG_RALINK_MT7628) ++ index =11; /* SR: 192k */ ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040; ++ ++ pTable = i2s_inclk_int_16bit; ++ //pTable = i2s_inclk_int_24bit; ++ data = pTable[index]; ++ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data; ++ i2s_outw(RALINK_I2S_BASE+0x24, data); ++ ++ pTable = i2s_inclk_comp_16bit; ++ //pTable = i2s_inclk_comp_24bit; ++ data = pTable[index]; ++ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data; ++ i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000)); ++ mdelay(5); ++#elif defined(CONFIG_ARCH_MT7623) ++ index = 11; ++ *(volatile unsigned long*)(I2S_I2SCFG1) = 0x80000000; ++ *(volatile unsigned long*)(I2S_I2SCFG) = 0xE1104040; ++ *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x30) |= 0x00020000; ++ *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x2c) |= 0x00000080; ++ ++ pTable = i2s_inclk_int_16bit; ++ //pTable = i2s_inclk_int_24bit; ++ data = pTable[index]; ++ i2s_outw(I2S_DIVINT_CFG, data); ++ ++ pTable = i2s_inclk_comp_16bit; ++ //pTable = i2s_inclk_comp_24bit; ++ data = pTable[index]; ++ i2s_outw(I2S_DIVCOMP_CFG, (data|0x80000000)); ++ mdelay(5); ++#else ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000006; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000105; ++#endif ++ { ++ int count = 0; ++ int k=0; ++ int enable_cnt=0; ++ unsigned long param[4]; ++ unsigned long data; ++ //unsigned long data_tmp; ++ unsigned long ff_status; ++ //unsigned long* txbuffer; ++#if 0 ++ int j=0; ++ int temp = 0; ++#endif ++#if defined (INTERNAL_LOOPBACK_DEBUG) ++ int count2 = 0; ++#endif ++ memset(param, 0, 4*sizeof(unsigned long) ); ++ copy_from_user(param, (unsigned long*)arg, sizeof(long)*2); ++#if 0 ++ txbuffer = (unsigned long*)kcalloc(param[0], sizeof(unsigned long), GFP_KERNEL); ++ if(txbuffer == NULL) ++ return -1; ++#endif ++ ++ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ printk("ff status=[0x%08X]\n",(u32)ff_status); ++ ++#if 0 ++ for(i = 0; i < param[0]; i++) ++ { ++ if (i==0) ++ { ++ txbuffer[i] = 0x555A555A; ++ printk("%d: 0x%8lx\n", i, txbuffer[i]); ++ } ++ else ++ { ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14) ++ srandom32(jiffies); ++ txbuffer[i] = random32()%(0x555A555A)+1; ++ //printk("%d: 0x%8x\n", i, txbuffer[i]); ++ #else ++ //TODO:do we need to implement random32() ++ txbuffer[i] = 0x01010101; ++ #endif ++ } ++ } ++#endif ++ ++ for( i = 0 ; i < param[0] ; i ++ ) ++ { ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) ++ if((ff_status&0xFF) > 0) ++ #else ++ if((ff_status&0x0F) > 0) ++ #endif ++ { ++ *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i]; ++ mdelay(1); ++ } ++ else ++ { ++ mdelay(1); ++ printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); ++ continue; ++ } ++ ++ //if(i >= 16) ++ { ++ ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ #if defined(CONFIG_RALINK_MT7628) ++ if(((ff_status>>8)&0xFF) > 0) ++ #else ++ if(((ff_status>>4)&0x0F) > 0) ++ #endif ++ { ++ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); ++ //data_tmp = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); ++ //MSG("[0x%08X] vs [0x%08X]\n", (u32)data, (u32)data_tmp); ++ } ++ else ++ { ++ printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); ++ continue; ++ } ++ ++ if (data == txbuffer[0]) ++ { ++ k = i; ++ enable_cnt = 1; ++ } ++ if (enable_cnt==1) ++ { ++ if(data!= txbuffer[i-k]) ++ { ++ MSG("[%d][0x%08X] vs [0x%08X]\n", (i-k), (u32)data, (u32)txbuffer[i-k]); ++ } ++ else ++ { ++ //MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i-k), (u32)data , (u32)txbuffer[i-k]); ++ count++; ++ data=0; ++ } ++ } ++ ++ } ++ } ++#if 0 ++ temp = i-k; ++ for (j=0; j<k; j++) ++ { ++ ++ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) ++ if(((ff_status>>8)&0xFF) > 0) ++ #else ++ if(((ff_status>>4)&0x0F) > 0) ++ #endif ++ { ++ //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14); ++ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); ++ } ++ else ++ { ++ printk("*NO RX FREE FIFO ST=[0x%08X]\n", (u32)ff_status); ++ continue; ++ } ++ ++ if(data!= txbuffer[temp+j]) ++ { ++ MSG("[%d][0x%08X] vs [0x%08X]\n", (temp+j), (u32)data, (u32)txbuffer[temp+j]); ++ } ++ else ++ { ++ //MSG("&&[%d][0x%08X] vs [0x%08X]\n" ,(temp+j), (u32)data , (u32)txbuffer[temp+j]); ++ count++; ++ data=0; ++ } ++ if ((temp+j)==128) ++ { ++ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ //printk("[%d]FIFO ST=[0x%08X]\n", (temp+j), (u32)ff_status); ++ } ++ } ++#endif ++ ++#if defined (INTERNAL_LOOPBACK_DEBUG) ++ for( i = 0 ; i < param[0] ; i ++ ) ++ { ++ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623) ++ if((ff_status&0xFF) > 0) ++ #else ++ if((ff_status&0x0F) > 0) ++ #endif ++ { ++ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x10) = txbuffer[i]; ++ *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i]; ++ mdelay(1); ++ } ++ else ++ { ++ mdelay(1); ++ printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); ++ continue; ++ } ++ ++ //if(i >= 16) ++ { ++ ++ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); ++ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); ++ #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623) ++ if(((ff_status>>8)&0xFF) > 0) ++ #else ++ if(((ff_status>>4)&0x0F) > 0) ++ #endif ++ { ++ //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14); ++ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); ++ } ++ else ++ { ++ printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); ++ continue; ++ } ++ ++ { ++ if(data!= txbuffer[i]) ++ { ++ MSG("[%d][0x%08X] vs [0x%08X]\n", (i), (u32)data, (u32)txbuffer[i]); ++ } ++ else ++ { ++ MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i), (u32)data , (u32)txbuffer[i]); ++ count2++; ++ data=0; ++ } ++ } ++ ++ } ++ } ++ printk("Pattern match done count2=%d.\n", count2); ++#endif ++ printk("Pattern match done count=%d.\n", count); ++ ++ } ++#if defined(CONFIG_ARCH_MT7623) ++ *(volatile unsigned long*)(0xFB000034) |= 0x00020000; ++ *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF; ++ *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule ++#endif ++ ++#if !defined(CONFIG_RALINK_RT3052) ++ break; ++#endif ++ case I2S_DEBUG_EXLBK: ++ MSG("I2S_DEBUG_EXLBK\n"); ++#if !defined(CONFIG_ARCH_MT7623) ++ switch(arg) ++ { ++ case 8000: ++ index = 0; ++ break; ++ case 11025: ++ index = 1; ++ break; ++ case 12000: ++ index = 2; ++ break; ++ case 16000: ++ index = 3; ++ break; ++ case 22050: ++ index = 4; ++ break; ++ case 24000: ++ index = 5; ++ break; ++ case 32000: ++ index = 6; ++ break; ++ case 44100: ++ index = 7; ++ break; ++ case 48000: ++ index = 8; ++ break; ++ case 88200: ++ index = 9; ++ break; ++ case 96000: ++ index = 10; ++ break; ++ default: ++ index = 7; ++ } ++#if defined(CONFIG_RALINK_RT3052) ++ break; ++#endif ++#if defined(CONFIG_RALINK_RT6855A) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080; ++ //*(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; ++#else ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000018; ++#if defined(CONFIG_RALINK_RT3883) ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00003000; ++#else ++ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00000300; ++#endif ++#endif ++ ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x40000000; ++ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0x81104040; ++#if defined(CONFIG_RALINK_MT7628) ++ pTable = i2s_inclk_int_16bit; ++#else ++ pTable = i2s_inclk_int; ++#endif ++ data = (volatile unsigned long)(pTable[index]); ++ i2s_outw(I2S_DIVINT_CFG, data); ++#if defined(CONFIG_RALINK_MT7628) ++ pTable = i2s_inclk_comp_16bit; ++#else ++ pTable = i2s_inclk_comp; ++#endif ++ data = (volatile unsigned long)(pTable[index]); ++ data |= REGBIT(1, I2S_CLKDIV_EN); ++ i2s_outw(I2S_DIVCOMP_CFG, data); ++ ++ #if defined(CONFIG_I2S_MCLK_12MHZ) ++ pTable = i2s_codec_12Mhz; ++ #if defined(CONFIG_I2S_WM8960) ++ data = pTable[index]; ++ #else ++ data = pTable[index]|0x01; ++ #endif ++ #else ++ pTable = i2s_codec_12p288Mhz; ++ data = pTable[index]; ++ #endif ++ ++ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++ audiohw_preinit(); ++ #endif ++ ++ ++ #if defined (CONFIG_I2S_WM8960) ++ audiohw_postinit(1, 1, 1, 1, 0); // for codec apll enable, 16 bit word length ++ #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++ audiohw_postinit(1, 1, 1, 0); // for 16 bit word length ++ #endif ++ ++ ++ #if defined (CONFIG_I2S_WM8960) ++ audiohw_set_frequency(data, 1); // for codec apll enable ++ #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++ audiohw_set_frequency(data|0x1); ++ #endif ++ ++ ++ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++ audiohw_set_lineout_vol(1, 100, 100); ++ audiohw_set_linein_vol(100, 100); ++ #endif ++ ++ ++ #if defined(CONFIG_I2S_TXRX) ++ //audiohw_loopback(data); ++ #endif ++ #if !defined(CONFIG_RALINK_RT3052) ++ break; ++ #endif ++#endif ++ case I2S_DEBUG_CODECBYPASS: ++ #if defined(CONFIG_I2S_TXRX) ++ #if defined(CONFIG_RALINK_MT7628) ++ data = i2s_inw(RALINK_SYSCTL_BASE+0x60); ++ //data &= ~(0x3<<4); ++ data &= ~(0x3<<6); ++ data &= ~(0x3<<16); ++ data &= ~(0x1<<14); ++ i2s_outw(RALINK_SYSCTL_BASE+0x60, data); ++ ++ data = i2s_inw(RALINK_SYSCTL_BASE+0x2c); ++ data &= ~(0x07<<9); ++ i2s_outw(RALINK_SYSCTL_BASE+0x2c, data); ++ #endif ++ ++ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) ++ audiohw_bypass(); /* did not work */ ++ #endif ++ #endif ++ break; ++ case I2S_DEBUG_FMT: ++ break; ++ case I2S_DEBUG_RESET: ++ break; ++#if defined(CONFIG_I2S_WM8960) ++ case I2S_DEBUG_CODEC_EXLBK: ++ audiohw_codec_exlbk(); ++ break; ++#endif ++ default: ++ MSG("Not support this debug cmd [%d]\n", cmd); ++ break; ++ } ++ ++ return 0; ++} +diff --git a/sound/soc/mtk/mt76xx_i2s.c b/sound/soc/mtk/mt76xx_i2s.c +new file mode 100644 +index 0000000..7615b51 --- /dev/null +++ b/sound/soc/mtk/mt76xx_i2s.c @@ -0,0 +1,304 @@ @@ -5252,6 +6333,9 @@ +MODULE_DESCRIPTION("Stretch MT76xx I2S Interface"); +MODULE_LICENSE("GPL"); +#endif +diff --git a/sound/soc/mtk/mt76xx_i2s.h b/sound/soc/mtk/mt76xx_i2s.h +new file mode 100644 +index 0000000..9ae0e50 --- /dev/null +++ b/sound/soc/mtk/mt76xx_i2s.h @@ -0,0 +1,18 @@ @@ -5273,6 +6357,9 @@ + +#include "i2s_ctrl.h" +#endif /* MTK_I2S_H_ */ +diff --git a/sound/soc/mtk/mt76xx_machine.c b/sound/soc/mtk/mt76xx_machine.c +new file mode 100644 +index 0000000..00d2145 --- /dev/null +++ b/sound/soc/mtk/mt76xx_machine.c @@ -0,0 +1,317 @@ @@ -5593,6 +6680,9 @@ +module_exit(mt76xx_machine_exit); +//EXPORT_SYMBOL_GPL(mt76xx_soc_platform); +MODULE_LICENSE("GPL"); +diff --git a/sound/soc/mtk/mt76xx_machine.h b/sound/soc/mtk/mt76xx_machine.h +new file mode 100644 +index 0000000..79532b5 --- /dev/null +++ b/sound/soc/mtk/mt76xx_machine.h @@ -0,0 +1,21 @@ @@ -5617,6 +6707,9 @@ +#endif + +#endif /* MT76XX_MACHINE_H_ */ +diff --git a/sound/soc/mtk/mt76xx_pcm.c b/sound/soc/mtk/mt76xx_pcm.c +new file mode 100644 +index 0000000..1100ee0 --- /dev/null +++ b/sound/soc/mtk/mt76xx_pcm.c @@ -0,0 +1,499 @@ @@ -6119,6 +7212,9 @@ +MODULE_DESCRIPTION("MTK APSoC I2S DMA driver"); +MODULE_LICENSE("GPL"); + +diff --git a/sound/soc/mtk/ralink_gdma.c b/sound/soc/mtk/ralink_gdma.c +new file mode 100644 +index 0000000..b385f05 --- /dev/null +++ b/sound/soc/mtk/ralink_gdma.c @@ -0,0 +1,918 @@ @@ -7040,6 +8136,9 @@ +MODULE_AUTHOR("Steven Liu <steven_liu@ralinktech.com.tw>"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(MOD_VERSION); +diff --git a/sound/soc/mtk/ralink_gdma.h b/sound/soc/mtk/ralink_gdma.h +new file mode 100644 +index 0000000..95ce5f7 --- /dev/null +++ b/sound/soc/mtk/ralink_gdma.h @@ -0,0 +1,326 @@ @@ -7369,9 +8468,11 @@ + + +#endif +diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c +index 6173d15..d9c52a7 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c -@@ -1851,7 +1851,8 @@ static int soc_probe(struct platform_dev +@@ -1758,7 +1758,8 @@ static int soc_probe(struct platform_device *pdev) /* Bodge while we unpick instantiation */ card->dev = &pdev->dev; @@ -7381,1008 +8482,6 @@ } static int soc_cleanup_card_resources(struct snd_soc_card *card) ---- /dev/null -+++ b/sound/soc/mtk/i2s_debug.c -@@ -0,0 +1,698 @@ -+#include <linux/init.h> -+#include <linux/version.h> -+#include <linux/module.h> -+#include <linux/kernel.h> /* printk() */ -+#include "i2s_ctrl.h" -+#include <linux/delay.h> -+#include <linux/jiffies.h> -+#include <linux/random.h> -+#include <linux/slab.h> -+#include <asm/uaccess.h> /* copy_from/to_user */ -+ -+#if defined(CONFIG_SND_RALINK_SOC) -+#include <sound/soc/mtk/mtk_audio_device.h> -+#endif -+ -+#if defined(CONFIG_I2S_WM8750) -+#include "../codec/i2c_wm8750.h" -+#endif -+#if defined(CONFIG_I2S_WM8751) -+#include "../codec/i2c_wm8751.h" -+#endif -+#if defined(CONFIG_I2S_WM8960) -+#include "i2c_wm8960.h" -+#endif -+ -+ -+//#define INTERNAL_LOOPBACK_DEBUG -+ -+extern unsigned long i2s_codec_12p288Mhz[11]; -+extern unsigned long i2s_codec_12Mhz[11]; -+#if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) -+extern unsigned long i2s_inclk_int_16bit[13]; -+extern unsigned long i2s_inclk_comp_16bit[13]; -+extern unsigned long i2s_inclk_int_24bit[13]; -+extern unsigned long i2s_inclk_comp_24bit[13]; -+#else -+extern unsigned long i2s_inclk_int[11]; -+extern unsigned long i2s_inclk_comp[11]; -+#endif -+extern int i2s_pll_config_mt7621(unsigned long index); -+extern int i2s_pll_config_mt7623(unsigned long index); -+ -+#if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+extern void audiohw_loopback(int fsel); -+extern void audiohw_bypass(void); -+extern int audiohw_set_lineout_vol(int Aout, int vol_l, int vol_r); -+extern int audiohw_set_linein_vol(int vol_l, int vol_r); -+#endif -+ -+#if defined(CONFIG_I2S_WM8960) -+extern void audiohw_codec_exlbk(void); -+#endif -+ -+unsigned long txbuffer[512] = { -+ 0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 1 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 2 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 3 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 4 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 5 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 6 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00, //round 7 -+0x01020304, 0x05060708, 0x090a0b0c, 0x0d0e0f10, 0x11121314, 0x15161718, 0x191a1b1c, 0x1d1e1f20, -+ 0x21222324, 0x25262728, 0x292a2b2c, 0x2d2e2f30, 0x31323334, 0x35363738, 0x393a3b3c, 0x3d3e3f40, -+ 0x41424344, 0x45464748, 0x494a4b4c, 0x4d4e4f50, 0x51525354, 0x55565758, 0x595a5b5c, 0x5d5e5f60, -+ 0x61626364, 0x65666768, 0x696a6b6c, 0x6d6e6f70, 0x71727374, 0x75767778, 0x797a7b7c, 0x7d7e7f80, -+ 0x81828384, 0x85868788, 0x898a8b8c, 0x8d8e8f90, 0x91929394, 0x95969798, 0x999a9b9c, 0x9d9e9fa0, -+ 0xa1a2a3a4, 0xa5a6a7a8, 0xa9aaabac, 0xadaeafb0, 0xb1b2b3b4, 0xb5b6b7b8, 0xb9babbbc, 0xbdbebfc0, -+ 0xc1c2c3c4, 0xc5c6c7c8, 0xc9cacbcc, 0xcdcecfd0, 0xd1d2d3d4, 0xd5d6d7d8, 0xd9dadbdc, 0xdddedfe0, -+ 0xe1e2e3e4, 0xe5e6e7e8, 0xe9eaebec, 0xedeeeff0, 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fafbfc, 0xfdfeff00 //round 8 -+ }; -+ -+int i2s_debug_cmd(unsigned int cmd, unsigned long arg) -+{ -+ unsigned long data, index; -+ unsigned long *pTable; -+ int i; -+ -+ switch(cmd) -+ { -+ case I2S_DEBUG_CLKGEN: -+ MSG("I2S_DEBUG_CLKGEN\n"); -+#if defined(CONFIG_RALINK_RT3052) -+ *(volatile unsigned long*)(0xB0000060) = 0x00000016; -+ *(volatile unsigned long*)(0xB0000030) = 0x00009E00; -+ *(volatile unsigned long*)(0xB0000A00) = 0xC0000040; -+#elif defined(CONFIG_RALINK_RT3350) -+ *(volatile unsigned long*)(0xB0000060) = 0x00000018; -+ *(volatile unsigned long*)(0xB000002C) = 0x00000100; -+ *(volatile unsigned long*)(0xB0000030) = 0x00009E00; -+ *(volatile unsigned long*)(0xB0000A00) = 0xC0000040; -+#elif defined(CONFIG_RALINK_RT3883) -+ *(volatile unsigned long*)(0xB0000060) = 0x00000018; -+ *(volatile unsigned long*)(0xB000002C) = 0x00003000; -+ *(volatile unsigned long*)(0xB0000A00) = 0xC1104040; -+ *(volatile unsigned long*)(0xB0000A24) = 0x00000027; -+ *(volatile unsigned long*)(0xB0000A20) = 0x80000020; -+#elif (defined(CONFIG_RALINK_RT3352)||defined(CONFIG_RALINK_RT5350)) || defined (CONFIG_RALINK_RT6855) -+ *(volatile unsigned long*)(0xB0000060) = 0x00000018; -+ *(volatile unsigned long*)(0xB000002C) = 0x00000300; -+ *(volatile unsigned long*)(0xB0000A00) = 0xC1104040; -+ *(volatile unsigned long*)(0xB0000A24) = 0x00000027; -+ *(volatile unsigned long*)(0xB0000A20) = 0x80000020; -+#elif defined(CONFIG_RALINK_RT6855A) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080; -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000027; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000020; -+#else -+//#error "I2S debug mode not support this Chip" -+#endif -+ break; -+ case I2S_DEBUG_INLBK: -+ MSG("I2S_DEBUG_INLBK\n"); -+#if defined(CONFIG_RALINK_MT7621) -+ switch(96000) -+ { -+ case 8000: -+ index = 0; -+ break; -+ case 11025: -+ index = 1; -+ break; -+ case 12000: -+ index = 2; -+ break; -+ case 16000: -+ index = 3; -+ break; -+ case 22050: -+ index = 4; -+ break; -+ case 24000: -+ index = 5; -+ break; -+ case 32000: -+ index = 6; -+ break; -+ case 44100: -+ index = 7; -+ break; -+ case 48000: -+ index = 8; -+ break; -+ case 88200: -+ index = 9; -+ break; -+ case 96000: -+ index = 10; -+ break; -+ case 192000: -+ index = 11; -+ break; -+ default: -+ index = 7; -+ } -+ i2s_pll_config_mt7621(index); -+#elif defined(CONFIG_ARCH_MT7623) -+ i2s_pll_config_mt7623(11); -+#endif -+ -+ -+#if defined(CONFIG_RALINK_RT3052) -+ break; -+#endif -+#if defined(CONFIG_RALINK_RT6855A) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) |= 0x00020000; -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x834) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) |= 0x00008080; -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; -+#elif defined(CONFIG_RALINK_MT7621) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000; -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000010; //GPIO purpose selection -+#elif defined(CONFIG_RALINK_MT7628) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) |= 0x00020000; -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x34) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) &= ~((0x3)<<6); //GPIO purpose selection /*FIXME*/ -+#elif defined(CONFIG_ARCH_MT7623) -+ *(volatile unsigned long*)(0xFB000034) |= 0x00020000; -+ *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule -+ -+ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<12); -+ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<12); -+ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<9); -+ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<9); -+ *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<10); -+ *(volatile unsigned long*)(0xF0005040) |= ((0x1)<<9); -+ -+ *(volatile unsigned long*)(0xF00057F0) &= ~((0x7)<<12); -+ *(volatile unsigned long*)(0xF00057F0) |= ((0x6)<<12); -+ *(volatile unsigned long*)(0xF0005030) |= ((0x1)<<1); -+ -+ *(volatile unsigned long*)(0xF0005840) &= ~((0x7)<<6); -+ *(volatile unsigned long*)(0xF0005840) |= ((0x6)<<6); -+ *(volatile unsigned long*)(0xF0005040) &= ~((0x1)<<8); -+ -+ *(volatile unsigned long*)(0xF00058F0) &= ~((0x7)<<3); -+ *(volatile unsigned long*)(0xF00058F0) |= ((0x6)<<3); -+ *(volatile unsigned long*)(0xF0005070) |= ((0x1)<<14); -+ -+ -+#else -+ *(volatile unsigned long*)(0xB0000034) |= 0x00020000; -+ *(volatile unsigned long*)(0xB0000034) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(0xB0000A00) &= 0x7FFFFFFF; //Rest I2S to default vaule -+ *(volatile unsigned long*)(0xB0000060) = 0x00000018; -+ -+#if defined(CONFIG_RALINK_RT3883) -+ *(volatile unsigned long*)(0xB000002C) = 0x00003000; -+#elif defined(CONFIG_ARCH_MT7623) -+ -+#else -+ *(volatile unsigned long*)(0xB000002C) = 0x00000300; -+#endif -+#endif -+#if defined(CONFIG_RALINK_MT7621) -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040; -+ -+ pTable = i2s_inclk_int; -+ data = pTable[index]; -+ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data; -+ i2s_outw(RALINK_I2S_BASE+0x24, data); -+ -+ pTable = i2s_inclk_comp; -+ data = pTable[index]; -+ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data; -+ i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000)); -+#elif defined(CONFIG_RALINK_MT7628) -+ index =11; /* SR: 192k */ -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xc1104040; -+ -+ pTable = i2s_inclk_int_16bit; -+ //pTable = i2s_inclk_int_24bit; -+ data = pTable[index]; -+ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = data; -+ i2s_outw(RALINK_I2S_BASE+0x24, data); -+ -+ pTable = i2s_inclk_comp_16bit; -+ //pTable = i2s_inclk_comp_24bit; -+ data = pTable[index]; -+ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = data; -+ i2s_outw(RALINK_I2S_BASE+0x20, (data|0x80000000)); -+ mdelay(5); -+#elif defined(CONFIG_ARCH_MT7623) -+ index = 11; -+ *(volatile unsigned long*)(I2S_I2SCFG1) = 0x80000000; -+ *(volatile unsigned long*)(I2S_I2SCFG) = 0xE1104040; -+ *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x30) |= 0x00020000; -+ *(volatile unsigned long*)(ETHDMASYS_SYSCTL_BASE+0x2c) |= 0x00000080; -+ -+ pTable = i2s_inclk_int_16bit; -+ //pTable = i2s_inclk_int_24bit; -+ data = pTable[index]; -+ i2s_outw(I2S_DIVINT_CFG, data); -+ -+ pTable = i2s_inclk_comp_16bit; -+ //pTable = i2s_inclk_comp_24bit; -+ data = pTable[index]; -+ i2s_outw(I2S_DIVCOMP_CFG, (data|0x80000000)); -+ mdelay(5); -+#else -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x80000000; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0xC1104040; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x24) = 0x00000006; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x20) = 0x80000105; -+#endif -+ { -+ int count = 0; -+ int k=0; -+ int enable_cnt=0; -+ unsigned long param[4]; -+ unsigned long data; -+ //unsigned long data_tmp; -+ unsigned long ff_status; -+ //unsigned long* txbuffer; -+#if 0 -+ int j=0; -+ int temp = 0; -+#endif -+#if defined (INTERNAL_LOOPBACK_DEBUG) -+ int count2 = 0; -+#endif -+ memset(param, 0, 4*sizeof(unsigned long) ); -+ copy_from_user(param, (unsigned long*)arg, sizeof(long)*2); -+#if 0 -+ txbuffer = (unsigned long*)kcalloc(param[0], sizeof(unsigned long), GFP_KERNEL); -+ if(txbuffer == NULL) -+ return -1; -+#endif -+ -+ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ printk("ff status=[0x%08X]\n",(u32)ff_status); -+ -+#if 0 -+ for(i = 0; i < param[0]; i++) -+ { -+ if (i==0) -+ { -+ txbuffer[i] = 0x555A555A; -+ printk("%d: 0x%8lx\n", i, txbuffer[i]); -+ } -+ else -+ { -+ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,14) -+ srandom32(jiffies); -+ txbuffer[i] = random32()%(0x555A555A)+1; -+ //printk("%d: 0x%8x\n", i, txbuffer[i]); -+ #else -+ //TODO:do we need to implement random32() -+ txbuffer[i] = 0x01010101; -+ #endif -+ } -+ } -+#endif -+ -+ for( i = 0 ; i < param[0] ; i ++ ) -+ { -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) -+ if((ff_status&0xFF) > 0) -+ #else -+ if((ff_status&0x0F) > 0) -+ #endif -+ { -+ *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i]; -+ mdelay(1); -+ } -+ else -+ { -+ mdelay(1); -+ printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); -+ continue; -+ } -+ -+ //if(i >= 16) -+ { -+ -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ #if defined(CONFIG_RALINK_MT7628) -+ if(((ff_status>>8)&0xFF) > 0) -+ #else -+ if(((ff_status>>4)&0x0F) > 0) -+ #endif -+ { -+ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); -+ //data_tmp = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); -+ //MSG("[0x%08X] vs [0x%08X]\n", (u32)data, (u32)data_tmp); -+ } -+ else -+ { -+ printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); -+ continue; -+ } -+ -+ if (data == txbuffer[0]) -+ { -+ k = i; -+ enable_cnt = 1; -+ } -+ if (enable_cnt==1) -+ { -+ if(data!= txbuffer[i-k]) -+ { -+ MSG("[%d][0x%08X] vs [0x%08X]\n", (i-k), (u32)data, (u32)txbuffer[i-k]); -+ } -+ else -+ { -+ //MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i-k), (u32)data , (u32)txbuffer[i-k]); -+ count++; -+ data=0; -+ } -+ } -+ -+ } -+ } -+#if 0 -+ temp = i-k; -+ for (j=0; j<k; j++) -+ { -+ -+ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ #if defined(CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) -+ if(((ff_status>>8)&0xFF) > 0) -+ #else -+ if(((ff_status>>4)&0x0F) > 0) -+ #endif -+ { -+ //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14); -+ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); -+ } -+ else -+ { -+ printk("*NO RX FREE FIFO ST=[0x%08X]\n", (u32)ff_status); -+ continue; -+ } -+ -+ if(data!= txbuffer[temp+j]) -+ { -+ MSG("[%d][0x%08X] vs [0x%08X]\n", (temp+j), (u32)data, (u32)txbuffer[temp+j]); -+ } -+ else -+ { -+ //MSG("&&[%d][0x%08X] vs [0x%08X]\n" ,(temp+j), (u32)data , (u32)txbuffer[temp+j]); -+ count++; -+ data=0; -+ } -+ if ((temp+j)==128) -+ { -+ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ //printk("[%d]FIFO ST=[0x%08X]\n", (temp+j), (u32)ff_status); -+ } -+ } -+#endif -+ -+#if defined (INTERNAL_LOOPBACK_DEBUG) -+ for( i = 0 ; i < param[0] ; i ++ ) -+ { -+ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623) -+ if((ff_status&0xFF) > 0) -+ #else -+ if((ff_status&0x0F) > 0) -+ #endif -+ { -+ //*(volatile unsigned long*)(RALINK_I2S_BASE+0x10) = txbuffer[i]; -+ *(volatile unsigned long*)(I2S_TX_FIFO_WREG) = txbuffer[i]; -+ mdelay(1); -+ } -+ else -+ { -+ mdelay(1); -+ printk("[%d]NO TX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); -+ continue; -+ } -+ -+ //if(i >= 16) -+ { -+ -+ //ff_status = *(volatile unsigned long*)(RALINK_I2S_BASE+0x0C); -+ ff_status = *(volatile unsigned long*)(I2S_FF_STATUS); -+ #if defined(CONFIG_RALINK_MT7628)|| defined(CONFIG_ARCH_MT7623) -+ if(((ff_status>>8)&0xFF) > 0) -+ #else -+ if(((ff_status>>4)&0x0F) > 0) -+ #endif -+ { -+ //data = *(volatile unsigned long*)(RALINK_I2S_BASE+0x14); -+ data = *(volatile unsigned long*)(I2S_RX_FIFO_RREG); -+ } -+ else -+ { -+ printk("*[%d]NO RX FREE FIFO ST=[0x%08X]\n", i, (u32)ff_status); -+ continue; -+ } -+ -+ { -+ if(data!= txbuffer[i]) -+ { -+ MSG("[%d][0x%08X] vs [0x%08X]\n", (i), (u32)data, (u32)txbuffer[i]); -+ } -+ else -+ { -+ MSG("**[%d][0x%08X] vs [0x%08X]\n" ,(i), (u32)data , (u32)txbuffer[i]); -+ count2++; -+ data=0; -+ } -+ } -+ -+ } -+ } -+ printk("Pattern match done count2=%d.\n", count2); -+#endif -+ printk("Pattern match done count=%d.\n", count); -+ -+ } -+#if defined(CONFIG_ARCH_MT7623) -+ *(volatile unsigned long*)(0xFB000034) |= 0x00020000; -+ *(volatile unsigned long*)(0xFB000034) &= 0xFFFDFFFF; -+ *(volatile unsigned long*)(ETHDMASYS_I2S_BASE+0x0) &= 0x7FFFFFFF; //Rest I2S to default vaule -+#endif -+ -+#if !defined(CONFIG_RALINK_RT3052) -+ break; -+#endif -+ case I2S_DEBUG_EXLBK: -+ MSG("I2S_DEBUG_EXLBK\n"); -+#if !defined(CONFIG_ARCH_MT7623) -+ switch(arg) -+ { -+ case 8000: -+ index = 0; -+ break; -+ case 11025: -+ index = 1; -+ break; -+ case 12000: -+ index = 2; -+ break; -+ case 16000: -+ index = 3; -+ break; -+ case 22050: -+ index = 4; -+ break; -+ case 24000: -+ index = 5; -+ break; -+ case 32000: -+ index = 6; -+ break; -+ case 44100: -+ index = 7; -+ break; -+ case 48000: -+ index = 8; -+ break; -+ case 88200: -+ index = 9; -+ break; -+ case 96000: -+ index = 10; -+ break; -+ default: -+ index = 7; -+ } -+#if defined(CONFIG_RALINK_RT3052) -+ break; -+#endif -+#if defined(CONFIG_RALINK_RT6855A) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x860) = 0x00008080; -+ //*(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x82C) = 0x00000300; -+#else -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x60) = 0x00000018; -+#if defined(CONFIG_RALINK_RT3883) -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00003000; -+#else -+ *(volatile unsigned long*)(RALINK_SYSCTL_BASE+0x2C) = 0x00000300; -+#endif -+#endif -+ -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x18) = 0x40000000; -+ *(volatile unsigned long*)(RALINK_I2S_BASE+0x00) = 0x81104040; -+#if defined(CONFIG_RALINK_MT7628) -+ pTable = i2s_inclk_int_16bit; -+#else -+ pTable = i2s_inclk_int; -+#endif -+ data = (volatile unsigned long)(pTable[index]); -+ i2s_outw(I2S_DIVINT_CFG, data); -+#if defined(CONFIG_RALINK_MT7628) -+ pTable = i2s_inclk_comp_16bit; -+#else -+ pTable = i2s_inclk_comp; -+#endif -+ data = (volatile unsigned long)(pTable[index]); -+ data |= REGBIT(1, I2S_CLKDIV_EN); -+ i2s_outw(I2S_DIVCOMP_CFG, data); -+ -+ #if defined(CONFIG_I2S_MCLK_12MHZ) -+ pTable = i2s_codec_12Mhz; -+ #if defined(CONFIG_I2S_WM8960) -+ data = pTable[index]; -+ #else -+ data = pTable[index]|0x01; -+ #endif -+ #else -+ pTable = i2s_codec_12p288Mhz; -+ data = pTable[index]; -+ #endif -+ -+ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+ audiohw_preinit(); -+ #endif -+ -+ -+ #if defined (CONFIG_I2S_WM8960) -+ audiohw_postinit(1, 1, 1, 1, 0); // for codec apll enable, 16 bit word length -+ #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+ audiohw_postinit(1, 1, 1, 0); // for 16 bit word length -+ #endif -+ -+ -+ #if defined (CONFIG_I2S_WM8960) -+ audiohw_set_frequency(data, 1); // for codec apll enable -+ #elif defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+ audiohw_set_frequency(data|0x1); -+ #endif -+ -+ -+ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+ audiohw_set_lineout_vol(1, 100, 100); -+ audiohw_set_linein_vol(100, 100); -+ #endif -+ -+ -+ #if defined(CONFIG_I2S_TXRX) -+ //audiohw_loopback(data); -+ #endif -+ #if !defined(CONFIG_RALINK_RT3052) -+ break; -+ #endif -+#endif -+ case I2S_DEBUG_CODECBYPASS: -+ #if defined(CONFIG_I2S_TXRX) -+ #if defined(CONFIG_RALINK_MT7628) -+ data = i2s_inw(RALINK_SYSCTL_BASE+0x60); -+ //data &= ~(0x3<<4); -+ data &= ~(0x3<<6); -+ data &= ~(0x3<<16); -+ data &= ~(0x1<<14); -+ i2s_outw(RALINK_SYSCTL_BASE+0x60, data); -+ -+ data = i2s_inw(RALINK_SYSCTL_BASE+0x2c); -+ data &= ~(0x07<<9); -+ i2s_outw(RALINK_SYSCTL_BASE+0x2c, data); -+ #endif -+ -+ #if defined(CONFIG_I2S_WM8960) || defined(CONFIG_I2S_WM8750) || defined(CONFIG_I2S_WM8751) -+ audiohw_bypass(); /* did not work */ -+ #endif -+ #endif -+ break; -+ case I2S_DEBUG_FMT: -+ break; -+ case I2S_DEBUG_RESET: -+ break; -+#if defined(CONFIG_I2S_WM8960) -+ case I2S_DEBUG_CODEC_EXLBK: -+ audiohw_codec_exlbk(); -+ break; -+#endif -+ default: -+ MSG("Not support this debug cmd [%d]\n", cmd); -+ break; -+ } -+ -+ return 0; -+} ---- a/sound/soc/codecs/wm8960.c -+++ b/sound/soc/codecs/wm8960.c -@@ -26,6 +26,7 @@ - #include <sound/wm8960.h> - - #include "wm8960.h" -+#include "../mtk/i2c_wm8960.h" - - /* R25 - Power 1 */ - #define WM8960_VMID_MASK 0x180 -@@ -53,10 +54,10 @@ - * using 2 wire for device control, so we cache them instead. - */ - static const struct reg_default wm8960_reg_defaults[] = { -- { 0x0, 0x00a7 }, -- { 0x1, 0x00a7 }, -- { 0x2, 0x0000 }, -- { 0x3, 0x0000 }, -+ { 0x0, 0x002b }, -+ { 0x1, 0x002b }, -+ { 0x2, 0x00ff }, -+ { 0x3, 0x00ff }, - { 0x4, 0x0000 }, - { 0x5, 0x0008 }, - { 0x6, 0x0000 }, -@@ -88,8 +89,8 @@ static const struct reg_default wm8960_r - { 0x25, 0x0050 }, - { 0x26, 0x0000 }, - { 0x27, 0x0000 }, -- { 0x28, 0x0000 }, -- { 0x29, 0x0000 }, -+ { 0x28, 0x007b }, -+ { 0x29, 0x007b }, - { 0x2a, 0x0040 }, - { 0x2b, 0x0000 }, - { 0x2c, 0x0000 }, -@@ -127,8 +128,15 @@ struct wm8960_priv { - int playback_fs; - }; - -+#if 1 -+#define wm8960_reset(c) do{ \ -+ int i = 0;\ -+ snd_soc_write(c, WM8960_RESET, 0);\ -+ for(i = 0; i < 1000*HZ; i++);\ -+ }while(0) -+#else - #define wm8960_reset(c) snd_soc_write(c, WM8960_RESET, 0) -- -+#endif - /* enumerated controls */ - static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", - "Right Inverted", "Stereo Inversion"}; -@@ -181,8 +189,8 @@ static int wm8960_get_deemph(struct snd_ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); - -- ucontrol->value.integer.value[0] = wm8960->deemph; -- return 0; -+ //ucontrol->value.integer.value[0] = wm8960->deemph; -+ return wm8960->deemph; - } - - static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, -@@ -200,6 +208,70 @@ static int wm8960_put_deemph(struct snd_ - return wm8960_set_deemph(codec); - } - -+static int wm8960_preinit(struct snd_soc_codec *codec) -+{ -+ //printk("****** %s ******\n", __func__); -+ snd_soc_write(codec, WM8960_RESET, 0); -+ mdelay(500); -+ -+ return 0; -+} -+ -+static int wm8960_postinit(struct snd_soc_codec *codec) -+{ -+ u32 data; -+ //printk("****** %s ******\n", __func__); -+ // In -+ data = snd_soc_read(codec, WM8960_POWER1); -+ snd_soc_write(codec, WM8960_POWER1, data|WM8960_PWR1_ADCL|WM8960_PWR1_ADCR|WM8960_PWR1_AINL |WM8960_PWR1_AINR|WM8960_PWR1_MICB);//0x19 -+ data = snd_soc_read(codec, WM8960_ADDCTL1); -+ snd_soc_write(codec, WM8960_ADDCTL1, data|ADDITIONAL1_DATSEL(0x01));//0x17 -+ snd_soc_write(codec, WM8960_LADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x15 -+ snd_soc_write(codec, WM8960_RADC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xc3));//0x16 -+ snd_soc_write(codec, WM8960_LINPATH, 0x148);//0x20 -+ snd_soc_write(codec, WM8960_RINPATH, 0x148);//0x21 -+ snd_soc_write(codec, WM8960_POWER3, WM8960_PWR3_LMIC|WM8960_PWR3_RMIC);//0x2f -+ -+ // Out -+ data = snd_soc_read(codec, WM8960_POWER2); -+ snd_soc_write(codec, WM8960_POWER2, data|WM8960_PWR2_DACL|WM8960_PWR2_DACR|WM8960_PWR2_LOUT1|WM8960_PWR2_ROUT1|WM8960_PWR2_SPKL|WM8960_PWR2_SPKR);//0x1a -+ mdelay(10); -+ snd_soc_write(codec, WM8960_IFACE2, 0x40); -+ snd_soc_write(codec, WM8960_LDAC, LEFTGAIN_LDVU|LEFTGAIN_LDACVOL(0xff));//0x0a -+ snd_soc_write(codec, WM8960_RDAC, RIGHTGAIN_RDVU|RIGHTGAIN_RDACVOL(0xff));//0x0b -+ snd_soc_write(codec, WM8960_LOUTMIX, 0x100);//0x22 -+ snd_soc_write(codec, WM8960_ROUTMIX, 0x100);//0x25 -+ -+ data = snd_soc_read(codec, WM8960_POWER3); -+ snd_soc_write(codec, WM8960_POWER3, data|WM8960_PWR3_ROMIX|WM8960_PWR3_LOMIX);//0x2f -+ -+ snd_soc_write(codec, WM8960_CLASSD1, 0xf7);//0x31 -+ snd_soc_write(codec, WM8960_CLASSD3, 0xad);//0x33 -+ snd_soc_write(codec, WM8960_DACCTL1, 0x000);//0x05 -+ -+ data = snd_soc_read(codec, WM8960_POWER1); -+ snd_soc_write(codec, WM8960_POWER1, data|0x1c0);//0x19 -+ -+ -+ snd_soc_write(codec, WM8960_LOUT1, LOUT1_LO1VU|LOUT1_LO1ZC|LOUT1_LOUT1VOL(115));//0x02 -+ snd_soc_write(codec, WM8960_ROUT1, ROUT1_RO1VU|ROUT1_RO1ZC|ROUT1_ROUT1VOL(115));//0x03 -+ -+ snd_soc_write(codec, WM8960_LINVOL, LINV_IPVU|LINV_LINVOL(110)); //LINV(0x00)=>0x12b -+ snd_soc_write(codec, WM8960_RINVOL, RINV_IPVU|RINV_RINVOL(110)); //LINV(0x01)=>0x12b -+ -+ return 0; -+} -+ -+static int wm8960_close(struct snd_soc_codec *codec) -+{ -+ snd_soc_write(codec, WM8960_DACCTL1,0x8); //0x05->0x08 -+ snd_soc_write(codec, WM8960_POWER1, 0x000); //0x19->0x000 -+ mdelay(300); -+ snd_soc_write(codec, WM8960_POWER2, 0x000); //0x1a->0x000 -+ -+ return 0; -+} -+ - static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0); - static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1); - static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0); -@@ -542,6 +614,7 @@ static int wm8960_set_dai_fmt(struct snd - - /* set iface */ - snd_soc_write(codec, WM8960_IFACE1, iface); -+ wm8960_postinit(codec); - return 0; - } - -@@ -623,11 +696,16 @@ static int wm8960_set_bias_level_out3(st - break; - - case SND_SOC_BIAS_PREPARE: -+#if 0 - /* Set VMID to 2x50k */ - snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80); -+#endif - break; - - case SND_SOC_BIAS_STANDBY: -+#if 1 -+ wm8960_preinit(codec); -+#else - if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { - regcache_sync(wm8960->regmap); - -@@ -650,9 +728,13 @@ static int wm8960_set_bias_level_out3(st - - /* Set VMID to 2x250k */ - snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100); -+#endif - break; - - case SND_SOC_BIAS_OFF: -+#if 1 -+ wm8960_close(codec); -+#else - /* Enable anti-pop features */ - snd_soc_write(codec, WM8960_APOP1, - WM8960_POBCTRL | WM8960_SOFT_ST | -@@ -661,6 +743,7 @@ static int wm8960_set_bias_level_out3(st - /* Disable VMID and VREF, let them discharge */ - snd_soc_write(codec, WM8960_POWER1, 0); - msleep(600); -+#endif - break; - } - -@@ -853,10 +936,15 @@ static int wm8960_set_dai_pll(struct snd - - if (pll_div.k) { - reg |= 0x20; -- -+#if 1 - snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); - snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); - snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); -+#else -+ snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); -+ snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); -+ snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); -+#endif - } - snd_soc_write(codec, WM8960_PLL1, reg); - -@@ -888,7 +976,11 @@ static int wm8960_set_dai_clkdiv(struct - snd_soc_write(codec, WM8960_PLL1, reg | div); - break; - case WM8960_DCLKDIV: -+#if 1 - reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; -+#else -+ reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; -+#endif - snd_soc_write(codec, WM8960_CLOCK2, reg | div); - break; - case WM8960_TOCLKSEL: -@@ -962,7 +1054,7 @@ static int wm8960_probe(struct snd_soc_c - { - struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); - struct wm8960_data *pdata = dev_get_platdata(codec->dev); -- int ret; -+ int ret = 0; - - wm8960->set_bias_level = wm8960_set_bias_level_out3; - -@@ -973,11 +1065,7 @@ static int wm8960_probe(struct snd_soc_c - wm8960->set_bias_level = wm8960_set_bias_level_capless; - } - -- ret = wm8960_reset(codec); -- if (ret < 0) { -- dev_err(codec->dev, "Failed to issue reset\n"); -- return ret; -- } -+ wm8960_reset(codec); - - wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY); - ---- a/sound/soc/codecs/wm8960.h -+++ b/sound/soc/codecs/wm8960.h -@@ -110,4 +110,68 @@ - #define WM8960_OPCLK_DIV_5_5 (4 << 0) - #define WM8960_OPCLK_DIV_6 (5 << 0) - -+/* -+ * WM8960 Power management -+ */ -+#define WM8960_PWR1_VMIDSEL_DISABLED (0 << 7) -+#define WM8960_PWR1_VMIDSEL_50K (1 << 7) -+#define WM8960_PWR1_VMIDSEL_250K (2 << 7) -+#define WM8960_PWR1_VMIDSEL_5K (3 << 7) -+#define WM8960_PWR1_VREF (1 << 6) -+#define WM8960_PWR1_AINL (1 << 5) -+#define WM8960_PWR1_AINR (1 << 4) -+#define WM8960_PWR1_ADCL (1 << 3) -+#define WM8960_PWR1_ADCR (1 << 2) -+#define WM8960_PWR1_MICB (1 << 1) -+#define WM8960_PWR1_DIGENB (1 << 0) -+ -+#define WM8960_PWR2_DACL (1 << 8) -+#define WM8960_PWR2_DACR (1 << 7) -+//#define WM8960_PWR2_LOUT1 (1 << 6) -+//#define WM8960_PWR2_ROUT1 (1 << 5) -+#define WM8960_PWR2_SPKL (1 << 4) -+#define WM8960_PWR2_SPKR (1 << 3) -+//#define WM8960_PWR2_OUT3 (1 << 1) -+#define WM8960_PWR2_PLL_EN (1 << 0) -+ -+#define WM8960_PWR3_LMIC (1 << 5) -+#define WM8960_PWR3_RMIC (1 << 4) -+#define WM8960_PWR3_LOMIX (1 << 3) -+#define WM8960_PWR3_ROMIX (1 << 2) -+ -+#define LEFTGAIN 0x0a -+#define LEFTGAIN_LDVU (1 << 8) -+#define LEFTGAIN_LDACVOL(x) ((x) & 0xff) -+ -+#define RIGHTGAIN 0x0b -+#define RIGHTGAIN_RDVU (1 << 8) -+#define RIGHTGAIN_RDACVOL(x) ((x) & 0xff) -+ -+#define ADDITIONAL1_DATSEL(x) (((x) & 0x3) << 2) -+ -+#define AINTFCE1_WL_32 (3 << 2) -+#define AINTFCE1_WL_24 (2 << 2) -+#define AINTFCE1_WL_20 (1 << 2) -+#define AINTFCE1_WL_16 (0 << 2) -+#define AINTFCE1_FORMAT_I2S (2 << 0) -+ -+#define LOUT1_LO1VU (1 << 8) -+#define LOUT1_LO1ZC (1 << 7) -+#define LOUT1_LOUT1VOL(x) ((x) & 0x7f) -+ -+#define ROUT1_RO1VU (1 << 8) -+#define ROUT1_RO1ZC (1 << 7) -+#define ROUT1_ROUT1VOL(x) ((x) & 0x7f) -+ -+#define LINV_IPVU (1 << 8) /* FIXME */ -+ -+#define LINV_LINMUTE (1 << 7) -+#define LINV_LIZC (1 << 6) -+#define LINV_LINVOL(x) ((x) & 0x3f) -+ -+#define RINV_IPVU (1 << 8) /* FIXME */ -+#define RINV_RINMUTE (1 << 7) -+#define RINV_RIZC (1 << 6) -+#define RINV_RINVOL(x) ((x) & 0x3f) -+ - #endif +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0051-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-4.3/0051-serial-add-ugly-custom-baud-rate-hack.patch new file mode 100644 index 0000000000..361b8d718a --- /dev/null +++ b/target/linux/ramips/patches-4.3/0051-serial-add-ugly-custom-baud-rate-hack.patch @@ -0,0 +1,27 @@ +From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:31:08 +0100 +Subject: [PATCH 51/53] serial: add ugly custom baud rate hack + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/tty/serial/serial_core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c +index 603d2cc..4020e07 100644 +--- a/drivers/tty/serial/serial_core.c ++++ b/drivers/tty/serial/serial_core.c +@@ -359,6 +359,9 @@ uart_get_baud_rate(struct uart_port *port, struct ktermios *termios, + break; + } + ++ if (tty_termios_baud_rate(termios) == 2500000) ++ return 250000; ++ + for (try = 0; try < 2; try++) { + baud = tty_termios_baud_rate(termios); + +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-3.18/0065-mt7628-pww.patch b/target/linux/ramips/patches-4.3/0052-pwm-add-mediatek-support.patch index dc2ca95e4d..caaf84aab3 100644 --- a/target/linux/ramips/patches-3.18/0065-mt7628-pww.patch +++ b/target/linux/ramips/patches-4.3/0052-pwm-add-mediatek-support.patch @@ -1,6 +1,21 @@ +From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 17:16:50 +0100 +Subject: [PATCH 52/53] pwm: add mediatek support + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/pwm/Kconfig | 9 +++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 183 insertions(+) + create mode 100644 drivers/pwm/pwm-mediatek.c + +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 062630a..76974ea 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig -@@ -177,6 +177,15 @@ config PWM_LPSS_PLATFORM +@@ -230,6 +230,15 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. @@ -16,9 +31,11 @@ config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS && OF +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index a0e00c0..aa0bd2e 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile -@@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx +@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o @@ -26,6 +43,9 @@ obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o +diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c +new file mode 100644 +index 0000000..f9d8ed4 --- /dev/null +++ b/drivers/pwm/pwm-mediatek.c @@ -0,0 +1,173 @@ @@ -202,3 +222,6 @@ +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); +MODULE_ALIAS("platform:mtk-pwm"); +-- +1.7.10.4 + diff --git a/target/linux/ramips/patches-4.3/0053-gic.patch b/target/linux/ramips/patches-4.3/0053-gic.patch new file mode 100644 index 0000000000..c20cedf48e --- /dev/null +++ b/target/linux/ramips/patches-4.3/0053-gic.patch @@ -0,0 +1,305 @@ +From 7b042645c1bd6407b1f7d9aa5785868e7e14b860 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 7 Dec 2015 18:40:16 +0100 +Subject: [PATCH 53/53] gic + +--- + arch/mips/ralink/Kconfig | 1 + + arch/mips/ralink/Makefile | 2 +- + arch/mips/ralink/irq-gic.c | 212 ++------------------------------------------ + 3 files changed, 11 insertions(+), 204 deletions(-) + +--- a/arch/mips/ralink/Kconfig ++++ b/arch/mips/ralink/Kconfig +@@ -51,9 +51,9 @@ + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_MIPS_CMP ++ select MIPS_GIC + select IRQ_GIC + select HW_HAS_PCI +- + endchoice + + choice +--- a/arch/mips/ralink/Makefile ++++ b/arch/mips/ralink/Makefile +@@ -13,7 +13,7 @@ + obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o + + obj-$(CONFIG_IRQ_INTC) += irq.o +-obj-$(CONFIG_IRQ_GIC) += irq-gic.o ++obj-$(CONFIG_MIPS_GIC_IPI) += irq-gic.o + obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o + + obj-$(CONFIG_SOC_RT288X) += rt288x.o +--- a/arch/mips/ralink/irq-gic.c ++++ b/arch/mips/ralink/irq-gic.c +@@ -16,248 +16,22 @@ + #include <asm/irq.h> + #include <asm/setup.h> + +-#include <asm/gic.h> ++#include <asm/mips-cm.h> ++#include <linux/irqchip/mips-gic.h> + + #include <asm/mach-ralink/mt7621.h> +-#define GIC_BASE_ADDR 0x1fbc0000 + +-unsigned long _gcmp_base; +-static int gic_resched_int_base = 56; +-static int gic_call_int_base = 60; +-static struct irq_chip *irq_gic; +-static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS]; +- +-#if defined(CONFIG_MIPS_MT_SMP) +-static int gic_resched_int_base; +-static int gic_call_int_base; ++extern int __init gic_of_init(struct device_node *node, ++ struct device_node *parent); + +-#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu)) +-#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu)) +- +-static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +-{ +- scheduler_ipi(); +- +- return IRQ_HANDLED; +-} +- +-static irqreturn_t +-ipi_call_interrupt(int irq, void *dev_id) +-{ +- smp_call_function_interrupt(); +- +- return IRQ_HANDLED; +-} +- +-static struct irqaction irq_resched = { +- .handler = ipi_resched_interrupt, +- .flags = IRQF_DISABLED|IRQF_PERCPU, +- .name = "ipi resched" +-}; +- +-static struct irqaction irq_call = { +- .handler = ipi_call_interrupt, +- .flags = IRQF_DISABLED|IRQF_PERCPU, +- .name = "ipi call" +-}; +- +-#endif +- +-static void __init +-gic_fill_map(void) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) { +- gic_intr_map[i].cpunum = 0; +- gic_intr_map[i].pin = GIC_CPU_INT0; +- gic_intr_map[i].polarity = GIC_POL_POS; +- gic_intr_map[i].trigtype = GIC_TRIG_LEVEL; +- gic_intr_map[i].flags = 0; +- } +- +-#if defined(CONFIG_MIPS_MT_SMP) +- { +- int cpu; +- +- gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids; +- gic_resched_int_base = gic_call_int_base - nr_cpu_ids; +- +- i = gic_resched_int_base; +- +- for (cpu = 0; cpu < nr_cpu_ids; cpu++) { +- gic_intr_map[i + cpu].cpunum = cpu; +- gic_intr_map[i + cpu].pin = GIC_CPU_INT1; +- gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE; +- +- gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu; +- gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2; +- gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE; +- } +- } +-#endif +-} +- +-void +-gic_irq_ack(struct irq_data *d) +-{ +- int irq = (d->irq - gic_irq_base); +- +- GIC_CLR_INTR_MASK(irq); +- +- if (gic_irq_flags[irq] & GIC_TRIG_EDGE) +- GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); +-} +- +-void +-gic_finish_irq(struct irq_data *d) +-{ +- GIC_SET_INTR_MASK(d->irq - gic_irq_base); +-} +- +-void __init +-gic_platform_init(int irqs, struct irq_chip *irq_controller) +-{ +- irq_gic = irq_controller; +-} +- +-static void +-gic_irqdispatch(void) +-{ +- unsigned int irq = gic_get_int(); +- +- if (likely(irq < GIC_NUM_INTRS)) +- do_IRQ(MIPS_GIC_IRQ_BASE + irq); +- else { +- pr_debug("Spurious GIC Interrupt!\n"); +- spurious_interrupt(); +- } +- +-} +- +-static void +-vi_timer_irqdispatch(void) +-{ +- do_IRQ(cp0_compare_irq); +-} +- +-#if defined(CONFIG_MIPS_MT_SMP) +-unsigned int +-plat_ipi_call_int_xlate(unsigned int cpu) +-{ +- return GIC_CALL_INT(cpu); +-} +- +-unsigned int +-plat_ipi_resched_int_xlate(unsigned int cpu) +-{ +- return GIC_RESCHED_INT(cpu); +-} +-#endif +- +-asmlinkage void +-plat_irq_dispatch(void) +-{ +- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; +- +- if (unlikely(!pending)) { +- pr_err("Spurious CP0 Interrupt!\n"); +- spurious_interrupt(); +- } else { +- if (pending & CAUSEF_IP7) +- do_IRQ(cp0_compare_irq); +- +- if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2)) +- gic_irqdispatch(); +- } +-} +- +-unsigned int __cpuinit +-get_c0_compare_int(void) +-{ +- return CP0_LEGACY_COMPARE_IRQ; +-} +- +-static int +-gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +-{ +- irq_set_chip_and_handler(irq, irq_gic, +-#if defined(CONFIG_MIPS_MT_SMP) +- (hw >= gic_resched_int_base) ? +- handle_percpu_irq : +-#endif +- handle_level_irq); +- +- return 0; +-} +- +-static const struct irq_domain_ops irq_domain_ops = { +- .xlate = irq_domain_xlate_onecell, +- .map = gic_map, +-}; +- +-static int __init +-of_gic_init(struct device_node *node, +- struct device_node *parent) ++unsigned int get_c0_compare_int(void) + { +- struct irq_domain *domain; +- struct resource gcmp = { 0 }, gic = { 0 }; +- unsigned int gic_rev; +- int i; +- +- if (of_address_to_resource(node, 0, &gic)) +- panic("Failed to get gic memory range"); +- if (request_mem_region(gic.start, resource_size(&gic), +- gic.name) < 0) +- panic("Failed to request gic memory"); +- if (of_address_to_resource(node, 2, &gcmp)) +- panic("Failed to get gic memory range"); +- if (request_mem_region(gcmp.start, resource_size(&gcmp), +- gcmp.name) < 0) +- panic("Failed to request gcmp memory"); +- +- _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp)); +- if (!_gcmp_base) +- panic("Failed to remap gcmp memory\n"); +- +- /* tell the gcmp where to find the gic */ +- write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); +- gic_present = 1; +- if (cpu_has_vint) { +- set_vi_handler(2, gic_irqdispatch); +- set_vi_handler(3, gic_irqdispatch); +- set_vi_handler(4, gic_irqdispatch); +- set_vi_handler(7, vi_timer_irqdispatch); +- } +- +- gic_fill_map(); +- +- gic_init(gic.start, resource_size(&gic), gic_intr_map, +- ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +- +- GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev); +- pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff); +- +- domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE, +- 0, &irq_domain_ops, NULL); +- if (!domain) +- panic("Failed to add irqdomain"); +- +-#if defined(CONFIG_MIPS_MT_SMP) +- for (i = 0; i < nr_cpu_ids; i++) { +- setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched); +- setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call); +- } +-#endif +- +- change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 | +- STATUSF_IP2); +- return 0; ++ return gic_get_c0_compare_int(); + } + + static struct of_device_id __initdata of_irq_ids[] = { +- { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, +- { .compatible = "ralink,mt7621-gic", .data = of_gic_init }, ++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, ++ { .compatible = "mti,gic", .data = gic_of_init }, + {}, + }; + +--- a/drivers/irqchip/irq-mips-gic.c ++++ b/drivers/irqchip/irq-mips-gic.c +@@ -864,7 +864,7 @@ + __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); + } + +-static int __init gic_of_init(struct device_node *node, ++int __init gic_of_init(struct device_node *node, + struct device_node *parent) + { + struct resource res; diff --git a/target/linux/ramips/patches-4.3/0054-mtd-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-4.3/0054-mtd-add-chunked-read-io-to-m25p80.patch new file mode 100644 index 0000000000..c7a33d2c38 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0054-mtd-add-chunked-read-io-to-m25p80.patch @@ -0,0 +1,123 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -1008,6 +1008,66 @@ write_err: + return ret; + } + ++static int spi_nor_chunked_write(struct mtd_info *mtd, loff_t _to, size_t _len, ++ size_t *_retlen, const u_char *_buf) ++{ ++ struct spi_nor *nor = mtd_to_spi_nor(mtd); ++ int chunk_size; ++ int retlen = 0; ++ int ret; ++ ++ chunk_size = nor->chunk_size; ++ if (!chunk_size) ++ chunk_size = _len; ++ ++ if (nor->addr_width > 3) ++ chunk_size -= nor->addr_width - 3; ++ ++ while (retlen < _len) { ++ size_t len = min_t(int, chunk_size, _len - retlen); ++ const u_char *buf = _buf + retlen; ++ loff_t to = _to + retlen; ++ ++ if (nor->flags & SNOR_F_SST) ++ ret = sst_write(mtd, to, len, &retlen, buf); ++ else ++ ret = spi_nor_write(mtd, to, len, &retlen, buf); ++ if (ret) ++ return ret; ++ } ++ ++ *_retlen += retlen; ++ return 0; ++} ++ ++static int spi_nor_chunked_read(struct mtd_info *mtd, loff_t _from, size_t _len, ++ size_t *_retlen, u_char *_buf) ++{ ++ struct spi_nor *nor = mtd_to_spi_nor(mtd); ++ int chunk_size; ++ int ret; ++ ++ chunk_size = nor->chunk_size; ++ if (!chunk_size) ++ chunk_size = _len; ++ ++ *_retlen = 0; ++ while (*_retlen < _len) { ++ size_t len = min_t(int, chunk_size, _len - *_retlen); ++ u_char *buf = _buf + *_retlen; ++ loff_t from = _from + *_retlen; ++ int retlen = 0; ++ ++ ret = spi_nor_read(mtd, from, len, &retlen, buf); ++ if (ret) ++ return ret; ++ ++ *_retlen += retlen; ++ } ++ ++ return 0; ++} ++ + static int macronix_quad_enable(struct spi_nor *nor) + { + int ret, val; +@@ -1231,10 +1291,12 @@ int spi_nor_scan(struct spi_nor *nor, co + } + + /* sst nor chips use AAI word program */ +- if (info->flags & SST_WRITE) ++ if (info->flags & SST_WRITE) { + mtd->_write = sst_write; +- else ++ nor->flags |= SNOR_F_SST; ++ } else { + mtd->_write = spi_nor_write; ++ } + + if (info->flags & USE_FSR) + nor->flags |= SNOR_F_USE_FSR; +@@ -1262,11 +1324,20 @@ int spi_nor_scan(struct spi_nor *nor, co + mtd->writebufsize = nor->page_size; + + if (np) { ++ u32 val; ++ + /* If we were instantiated by DT, use it */ + if (of_property_read_bool(np, "m25p,fast-read")) + nor->flash_read = SPI_NOR_FAST; + else + nor->flash_read = SPI_NOR_NORMAL; ++ ++ if (!of_property_read_u32(np, "m25p,chunked-io", &val)) { ++ dev_info(dev, "using chunked io (size=%d)\n", val); ++ mtd->_read = spi_nor_chunked_read; ++ mtd->_write = spi_nor_chunked_write; ++ nor->chunk_size = val; ++ } + } else { + /* If we weren't instantiated by DT, default to fast-read */ + nor->flash_read = SPI_NOR_FAST; +--- a/include/linux/mtd/spi-nor.h ++++ b/include/linux/mtd/spi-nor.h +@@ -116,6 +116,7 @@ enum spi_nor_ops { + + enum spi_nor_option_flags { + SNOR_F_USE_FSR = BIT(0), ++ SNOR_F_SST = BIT(1), + }; + + /** +@@ -156,6 +157,7 @@ struct spi_nor { + struct device *dev; + struct device_node *flash_node; + u32 page_size; ++ u16 chunk_size; + u8 addr_width; + u8 erase_opcode; + u8 read_opcode; diff --git a/target/linux/ramips/patches-3.18/0100-mtd-split-remove-padding.patch b/target/linux/ramips/patches-4.3/0100-mtd-split-remove-padding.patch index 81702c28e8..81702c28e8 100644 --- a/target/linux/ramips/patches-3.18/0100-mtd-split-remove-padding.patch +++ b/target/linux/ramips/patches-4.3/0100-mtd-split-remove-padding.patch diff --git a/target/linux/ramips/patches-3.18/0101-mtd-add-rtn56u-support.patch b/target/linux/ramips/patches-4.3/0101-mtd-add-rtn56u-support.patch index 50b88dbcd3..50b88dbcd3 100644 --- a/target/linux/ramips/patches-3.18/0101-mtd-add-rtn56u-support.patch +++ b/target/linux/ramips/patches-4.3/0101-mtd-add-rtn56u-support.patch diff --git a/target/linux/ramips/patches-3.18/0103-MIPS-OWRTDTB.patch b/target/linux/ramips/patches-4.3/0103-MIPS-OWRTDTB.patch index b90138317b..b90138317b 100644 --- a/target/linux/ramips/patches-3.18/0103-MIPS-OWRTDTB.patch +++ b/target/linux/ramips/patches-4.3/0103-MIPS-OWRTDTB.patch diff --git a/target/linux/ramips/patches-3.18/0104-fix_bootargs_handling.patch b/target/linux/ramips/patches-4.3/0104-fix_bootargs_handling.patch index 9f76aa1f5b..9f76aa1f5b 100644 --- a/target/linux/ramips/patches-3.18/0104-fix_bootargs_handling.patch +++ b/target/linux/ramips/patches-4.3/0104-fix_bootargs_handling.patch diff --git a/target/linux/ramips/patches-3.18/0200-linkit_bootstrap.patch b/target/linux/ramips/patches-4.3/0200-linkit_bootstrap.patch index 70e8170c44..70e8170c44 100644 --- a/target/linux/ramips/patches-3.18/0200-linkit_bootstrap.patch +++ b/target/linux/ramips/patches-4.3/0200-linkit_bootstrap.patch diff --git a/target/linux/ramips/rt288x/config-3.18 b/target/linux/ramips/rt288x/config-4.3 index f9eacfb964..658e235770 100644 --- a/target/linux/ramips/rt288x/config-3.18 +++ b/target/linux/ramips/rt288x/config-4.3 @@ -1,16 +1,20 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CEVT_R4K=y +# CONFIG_CEVT_SYSTICK_QUIRK is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" @@ -24,24 +28,28 @@ CONFIG_CPU_MIPS32=y # CONFIG_CPU_MIPS32_R1 is not set CONFIG_CPU_MIPS32_R2=y CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y # CONFIG_DTB_RT2880_EVAL is not set CONFIG_DTB_RT_NONE=y CONFIG_DTC=y CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_8250 is not set CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -50,12 +58,15 @@ CONFIG_GPIO_SYSFS=y CONFIG_HARDWARE_WATCHPOINTS=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_TRACEHOOK=y # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y CONFIG_HAVE_CC_STACKPROTECTOR=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CONTEXT_TRACKING=y @@ -64,13 +75,14 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_HAVE_DEBUG_STACKOVERFLOW=y CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -80,23 +92,29 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IP17XX_PHY=y CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y +CONFIG_LIBFDT=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=4 CONFIG_MIPS_L1_CACHE_SHIFT_4=y # CONFIG_MIPS_MACHINE is not set -CONFIG_MIPS_MT_DISABLED=y +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CMDLINE_PARTS=y @@ -111,7 +129,8 @@ CONFIG_NEED_PER_CPU_KM=y CONFIG_NET_RALINK=y CONFIG_NET_RALINK_MDIO=y CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RX_BUSY_POLL=y +CONFIG_NET_RALINK_RT288X=y +# CONFIG_NO_IOPORT_MAP is not set CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_EARLY_FLATTREE=y @@ -124,28 +143,26 @@ CONFIG_OF_NET=y CONFIG_PAGEFLAGS_EXTENDED=y # CONFIG_PCI is not set CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y # CONFIG_PHY_RALINK_USB is not set -# CONFIG_PINCONF is not set CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -# CONFIG_RALINK_USBPHY is not set CONFIG_RALINK_WDT=y -CONFIG_RA_NAT_NONE=y # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set CONFIG_SOC_RT288X=y # CONFIG_SOC_RT305X is not set # CONFIG_SOC_RT3883 is not set @@ -153,16 +170,19 @@ CONFIG_SPI=y CONFIG_SPI_MASTER=y # CONFIG_SPI_MT7621 is not set CONFIG_SPI_RT2880=y +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_USB_SUPPORT=y CONFIG_USE_OF=y CONFIG_WATCHDOG_CORE=y -# CONFIG_ZBUD is not set CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ramips/rt305x/config-3.18 b/target/linux/ramips/rt305x/config-4.3 index 9fb846f90e..4b81771192 100644 --- a/target/linux/ramips/rt305x/config-3.18 +++ b/target/linux/ramips/rt305x/config-4.3 @@ -1,13 +1,15 @@ -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -46,12 +48,13 @@ CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -62,6 +65,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -83,6 +87,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -92,20 +97,26 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CMDLINE_PARTS=y @@ -132,25 +143,27 @@ CONFIG_OF_MTD=y CONFIG_OF_NET=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHY_RALINK_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y # CONFIG_RALINK_ILL_ACC is not set CONFIG_RALINK_WDT=y # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set # CONFIG_SOC_RT288X is not set CONFIG_SOC_RT305X=y # CONFIG_SOC_RT3883 is not set @@ -158,7 +171,10 @@ CONFIG_SPI=y CONFIG_SPI_MASTER=y # CONFIG_SPI_MT7621 is not set CONFIG_SPI_RT2880=y +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y diff --git a/target/linux/ramips/rt3883/config-3.18 b/target/linux/ramips/rt3883/config-4.3 index 6dccb464dc..1e8bddde2b 100644 --- a/target/linux/ramips/rt3883/config-3.18 +++ b/target/linux/ramips/rt3883/config-4.3 @@ -1,18 +1,21 @@ CONFIG_AR8216_PHY=y -CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y # CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CEVT_R4K=y +# CONFIG_CEVT_SYSTICK_QUIRK is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" @@ -32,6 +35,8 @@ CONFIG_CPU_R4K_FPU=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DEBUG_PINCTRL=y CONFIG_DMA_NONCOHERENT=y @@ -42,12 +47,13 @@ CONFIG_EARLY_PRINTK=y CONFIG_ETHERNET_PACKET_MANGLE=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GPIOLIB=y CONFIG_GPIO_DEVRES=y @@ -58,6 +64,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -79,6 +86,7 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_KVM=y CONFIG_HAVE_MACH_CLKDEV=y CONFIG_HAVE_MEMBLOCK=y @@ -88,28 +96,34 @@ CONFIG_HAVE_NET_DSA=y CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HW_HAS_PCI=y CONFIG_HZ_PERIODIC=y CONFIG_INITRAMFS_SOURCE="" CONFIG_IRQCHIP=y -CONFIG_IRQ_CPU=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y +CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y +# CONFIG_MACH_INGENIC is not set +# CONFIG_MACH_LOONGSON32 is not set +# CONFIG_MACH_LOONGSON64 is not set CONFIG_MDIO_BOARDINFO=y CONFIG_MIPS=y # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set CONFIG_MIPS_L1_CACHE_SHIFT=5 # CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_NO_APPENDED_DTB=y +# CONFIG_MIPS_RAW_APPENDED_DTB is not set +CONFIG_MIPS_SPRAM=y CONFIG_MODULES_USE_ELF_REL=y # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_M25P80=y CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_SEAMA_FW=y CONFIG_MTD_SPLIT_UIMAGE_FW=y CONFIG_NEED_DMA_MAP_STATE=y @@ -136,29 +150,29 @@ CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PHY_RALINK_USB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RT2880=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PREEMPT_RCU is not set CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_USBPHY=y CONFIG_RALINK_WDT=y # CONFIG_RCU_STALL_COMMON is not set CONFIG_RESET_CONTROLLER=y CONFIG_RTL8366_SMI=y CONFIG_RTL8367B_PHY=y CONFIG_RTL8367_PHY=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set # CONFIG_SCSI_DMA is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set # CONFIG_SOC_RT288X is not set # CONFIG_SOC_RT305X is not set CONFIG_SOC_RT3883=y @@ -166,7 +180,10 @@ CONFIG_SPI=y CONFIG_SPI_MASTER=y # CONFIG_SPI_MT7621 is not set CONFIG_SPI_RT2880=y +CONFIG_SRCU=y +# CONFIG_SUNXI_SRAM is not set CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_EARLY_PRINTK=y @@ -175,7 +192,6 @@ CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_USB_PHY=y CONFIG_USB_SUPPORT=y CONFIG_USE_OF=y CONFIG_WATCHDOG_CORE=y |