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-rw-r--r--target/linux/sunxi/patches-4.4/103-clk-sunxi-add-h3-clksupport.patch180
1 files changed, 0 insertions, 180 deletions
diff --git a/target/linux/sunxi/patches-4.4/103-clk-sunxi-add-h3-clksupport.patch b/target/linux/sunxi/patches-4.4/103-clk-sunxi-add-h3-clksupport.patch
deleted file mode 100644
index 8bc66274c3..0000000000
--- a/target/linux/sunxi/patches-4.4/103-clk-sunxi-add-h3-clksupport.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From ab6e23a4e388f5f2696b8e92c350f845142da118 Mon Sep 17 00:00:00 2001
-From: Jens Kuske <jenskuske@gmail.com>
-Date: Fri, 4 Dec 2015 22:24:40 +0100
-Subject: [PATCH] clk: sunxi: Add H3 clocks support
-
-The H3 clock control unit is similar to the those of other sun8i family
-members like the A23.
-
-It adds a new bus gates clock similar to the simple gates, but with a
-different parent clock for each single gate.
-Some of the gates use the new AHB2 clock as parent, whose clock source
-is muxable between AHB1 and PLL6/2. The documentation isn't totally clear
-about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it
-is mostly based on Allwinner kernel source code.
-
-Signed-off-by: Jens Kuske <jenskuske@gmail.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
- drivers/clk/sunxi/Makefile | 1 +
- drivers/clk/sunxi/clk-sun8i-bus-gates.c | 112 ++++++++++++++++++++++
- drivers/clk/sunxi/clk-sunxi.c | 6 ++
- 4 files changed, 121 insertions(+)
- create mode 100644 drivers/clk/sunxi/clk-sun8i-bus-gates.c
-
---- a/drivers/clk/sunxi/Makefile
-+++ b/drivers/clk/sunxi/Makefile
-@@ -10,6 +10,7 @@ obj-y += clk-a10-pll2.o
- obj-y += clk-a20-gmac.o
- obj-y += clk-mod0.o
- obj-y += clk-simple-gates.o
-+obj-y += clk-sun8i-bus-gates.o
- obj-y += clk-sun8i-mbus.o
- obj-y += clk-sun9i-core.o
- obj-y += clk-sun9i-mmc.o
---- /dev/null
-+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
-@@ -0,0 +1,112 @@
-+/*
-+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
-+ *
-+ * Based on clk-simple-gates.c, which is:
-+ * Copyright 2015 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+
-+static DEFINE_SPINLOCK(gates_lock);
-+
-+static void __init sun8i_h3_bus_gates_init(struct device_node *node)
-+{
-+ static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
-+ enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
-+ const char *parents[PARENT_MAX];
-+ struct clk_onecell_data *clk_data;
-+ const char *clk_name;
-+ struct property *prop;
-+ struct resource res;
-+ void __iomem *clk_reg;
-+ void __iomem *reg;
-+ const __be32 *p;
-+ int number, i;
-+ u8 clk_bit;
-+ u32 index;
-+
-+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
-+ if (IS_ERR(reg))
-+ return;
-+
-+ for (i = 0; i < ARRAY_SIZE(names); i++) {
-+ index = of_property_match_string(node, "clock-names",
-+ names[i]);
-+ if (index < 0)
-+ return;
-+
-+ parents[i] = of_clk_get_parent_name(node, index);
-+ }
-+
-+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
-+ if (!clk_data)
-+ goto err_unmap;
-+
-+ number = of_property_count_u32_elems(node, "clock-indices");
-+ of_property_read_u32_index(node, "clock-indices", number - 1, &number);
-+
-+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
-+ if (!clk_data->clks)
-+ goto err_free_data;
-+
-+ i = 0;
-+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
-+ of_property_read_string_index(node, "clock-output-names",
-+ i, &clk_name);
-+
-+ if (index == 17 || (index >= 29 && index <= 31))
-+ clk_parent = AHB2;
-+ else if (index <= 63 || index >= 128)
-+ clk_parent = AHB1;
-+ else if (index >= 64 && index <= 95)
-+ clk_parent = APB1;
-+ else if (index >= 96 && index <= 127)
-+ clk_parent = APB2;
-+
-+ clk_reg = reg + 4 * (index / 32);
-+ clk_bit = index % 32;
-+
-+ clk_data->clks[index] = clk_register_gate(NULL, clk_name,
-+ parents[clk_parent],
-+ 0, clk_reg, clk_bit,
-+ 0, &gates_lock);
-+ i++;
-+
-+ if (IS_ERR(clk_data->clks[index])) {
-+ WARN_ON(true);
-+ continue;
-+ }
-+ }
-+
-+ clk_data->clk_num = number + 1;
-+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+ return;
-+
-+err_free_data:
-+ kfree(clk_data);
-+err_unmap:
-+ iounmap(reg);
-+ of_address_to_resource(node, 0, &res);
-+ release_mem_region(res.start, resource_size(&res));
-+}
-+
-+CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
-+ sun8i_h3_bus_gates_init);
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -778,6 +778,10 @@ static const struct mux_data sun6i_a31_a
- .shift = 12,
- };
-
-+static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
-+ .shift = 0,
-+};
-+
- static void __init sunxi_mux_clk_setup(struct device_node *node,
- struct mux_data *data)
- {
-@@ -1130,6 +1134,7 @@ static const struct of_device_id clk_div
- static const struct of_device_id clk_mux_match[] __initconst = {
- {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
- {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
-+ {.compatible = "allwinner,sun8i-h3-ahb2-clk", .data = &sun8i_h3_ahb2_mux_data,},
- {}
- };
-
-@@ -1212,6 +1217,7 @@ CLK_OF_DECLARE(sun6i_a31_clk_init, "allw
- CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
- CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
- CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
-+CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
-
- static void __init sun9i_init_clocks(struct device_node *node)
- {
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-14 04:40:10 +0000