diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.18')
19 files changed, 0 insertions, 4211 deletions
diff --git a/target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch b/target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch deleted file mode 100644 index b81ed449fb..0000000000 --- a/target/linux/sunxi/patches-3.18/100-dt-sun7i-add_spi0_pins_a.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0253d14782f80cfd1741d4ddd82b83dd7d44a91e Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 28 Jul 2014 22:44:59 +0200 -Subject: [PATCH] ARM: dts: sun7i: Add spi0_pins_a pinctrl setting - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -784,6 +784,13 @@ - allwinner,pull = <0>; - }; - -+ spi0_pins_a: spi0@0 { -+ allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; -+ allwinner,function = "spi0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ - spi1_pins_a: spi1@0 { - allwinner,pins = "PI16", "PI17", "PI18", "PI19"; - allwinner,function = "spi1"; diff --git a/target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch b/target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch deleted file mode 100644 index 284537af92..0000000000 --- a/target/linux/sunxi/patches-3.18/101-dt-sun7i-add-uart3_pins.patch +++ /dev/null @@ -1,29 +0,0 @@ -From e37ccbcd4587b7a2b943e23a9943b8917010b336 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Oct 2014 08:39:58 +0200 -Subject: [PATCH] ARM: dts: sun7i: Add uart3_pins_b pinctrl setting - -The uart3_pins_a multiplexes the uart3 pins to port G, add a pinctrl entry -for mapping them to port H (as used on the Bananapi). - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -677,6 +677,13 @@ - allwinner,pull = <0>; - }; - -+ uart3_pins_b: uart3@1 { -+ allwinner,pins = "PH0", "PH1"; -+ allwinner,function = "uart3"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ - uart4_pins_a: uart4@0 { - allwinner,pins = "PG10", "PG11"; - allwinner,function = "uart4"; diff --git a/target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch b/target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch deleted file mode 100644 index 28128db5e1..0000000000 --- a/target/linux/sunxi/patches-3.18/102-dt-sun7i-add_mmc2_pins.patch +++ /dev/null @@ -1,26 +0,0 @@ -From f65624ca1b67c5683317b75da2c09ffadc22fa2e Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Oct 2014 00:40:57 +0200 -Subject: [PATCH] ARM: dts: sun7i: Add mmc2_pins_a pinctrl definition - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -833,6 +833,13 @@ - allwinner,pull = <1>; - }; - -+ mmc2_pins_a: mmc2@0 { -+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; -+ allwinner,function = "mmc2"; -+ allwinner,drive = <2>; -+ allwinner,pull = <1>; -+ }; -+ - mmc3_pins_a: mmc3@0 { - allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; - allwinner,function = "mmc3"; diff --git a/target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch b/target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch deleted file mode 100644 index 12b4628f04..0000000000 --- a/target/linux/sunxi/patches-3.18/110-input-add-sun4i-lradc.patch +++ /dev/null @@ -1,400 +0,0 @@ -From 2c1fab89e83245a520871e807e233e66cbdb7c57 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Jan 2014 19:44:49 +0100 -Subject: [PATCH] input: Add new sun4i-lradc-keys driver - -Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is -specifically designed to have various (tablet) keys (ie home, back, search, -etc). attached to it using a resistor network. This adds a driver for this. - -There are 2 channels, currently this driver only supports chan0 since there -are no boards known to use chan1. - -This has been tested on an olimex a10s-olinuxino-micro, a13-olinuxino, and -a20-olinuxino-micro. - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- -Changes in v2: --Change devicetree bindings to use a per key subnode, like gpio-keys does ---- - .../devicetree/bindings/input/sun4i-lradc-keys.txt | 62 +++++ - MAINTAINERS | 7 + - drivers/input/keyboard/Kconfig | 10 + - drivers/input/keyboard/Makefile | 1 + - drivers/input/keyboard/sun4i-lradc-keys.c | 258 +++++++++++++++++++++ - 5 files changed, 338 insertions(+) - create mode 100644 Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt - create mode 100644 drivers/input/keyboard/sun4i-lradc-keys.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt -@@ -0,0 +1,62 @@ -+Allwinner sun4i low res adc attached tablet keys -+------------------------------------------------ -+ -+Required properties: -+ - compatible: "allwinner,sun4i-a10-lradc-keys" -+ - reg: mmio address range of the chip -+ - interrupts: interrupt to which the chip is connected -+ - vref-supply: powersupply for the lradc reference voltage -+ -+Each key is represented as a sub-node of "allwinner,sun4i-a10-lradc-keys": -+ -+Required subnode-properties: -+ - label: Descriptive name of the key. -+ - linux,code: Keycode to emit. -+ - channel: Channel this key is attached to, mut be 0 or 1. -+ - voltage: Voltage in µV at lradc input when this key is pressed. -+ -+Example: -+ -+#include <dt-bindings/input/input.h> -+ -+ lradc: lradc@01c22800 { -+ compatible = "allwinner,sun4i-a10-lradc-keys"; -+ reg = <0x01c22800 0x100>; -+ interrupts = <31>; -+ vref-supply = <®_vcc3v0>; -+ -+ button@191 { -+ label = "Volume Up"; -+ linux,code = <KEY_VOLUMEUP>; -+ channel = <0>; -+ voltage = <191274>; -+ }; -+ -+ button@392 { -+ label = "Volume Down"; -+ linux,code = <KEY_VOLUMEDOWN>; -+ channel = <0>; -+ voltage = <392644>; -+ }; -+ -+ button@601 { -+ label = "Menu"; -+ linux,code = <KEY_MENU>; -+ channel = <0>; -+ voltage = <601151>; -+ }; -+ -+ button@795 { -+ label = "Enter"; -+ linux,code = <KEY_ENTER>; -+ channel = <0>; -+ voltage = <795090>; -+ }; -+ -+ button@987 { -+ label = "Home"; -+ linux,code = <KEY_HOMEPAGE>; -+ channel = <0>; -+ voltage = <987387>; -+ }; -+ }; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -9002,6 +9002,13 @@ F: arch/m68k/sun3*/ - F: arch/m68k/include/asm/sun3* - F: drivers/net/ethernet/i825xx/sun3* - -+SUN4I LOW RES ADC ATTACHED TABLET KEYS DRIVER -+M: Hans de Goede <hdegoede@redhat.com> -+L: linux-input@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt -+F: drivers/input/keyboard/sun4i-lradc-keys.c -+ - SUNDANCE NETWORK DRIVER - M: Denis Kirjanov <kda@linux-powerpc.org> - L: netdev@vger.kernel.org ---- a/drivers/input/keyboard/Kconfig -+++ b/drivers/input/keyboard/Kconfig -@@ -567,6 +567,16 @@ config KEYBOARD_STMPE - To compile this driver as a module, choose M here: the module will be - called stmpe-keypad. - -+config KEYBOARD_SUN4I_LRADC -+ tristate "Allwinner sun4i low res adc attached tablet keys support" -+ depends on ARCH_SUNXI -+ help -+ This selects support for the Allwinner low res adc attached tablet -+ keys found on Allwinner sunxi SoCs. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called sun4i-lradc-keys. -+ - config KEYBOARD_DAVINCI - tristate "TI DaVinci Key Scan" - depends on ARCH_DAVINCI_DM365 ---- a/drivers/input/keyboard/Makefile -+++ b/drivers/input/keyboard/Makefile -@@ -53,6 +53,7 @@ obj-$(CONFIG_KEYBOARD_SPEAR) += spear-k - obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o - obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o - obj-$(CONFIG_KEYBOARD_ST_KEYSCAN) += st-keyscan.o -+obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o - obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o - obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o - obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o ---- /dev/null -+++ b/drivers/input/keyboard/sun4i-lradc-keys.c -@@ -0,0 +1,258 @@ -+/* -+ * Allwinner sun4i low res adc attached tablet keys driver -+ * -+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+/* -+ * Allwinnner sunxi SoCs have a lradc which is specifically designed to have -+ * various (tablet) keys (ie home, back, search, etc). attached to it using -+ * a resistor network. This driver is for the keys on such boards. -+ * -+ * There are 2 channels, currently this driver only supports channel 0 since -+ * there are no boards known to use channel 1. -+ */ -+ -+#include <linux/err.h> -+#include <linux/init.h> -+#include <linux/input.h> -+#include <linux/interrupt.h> -+#include <linux/io.h> -+#include <linux/module.h> -+#include <linux/of_platform.h> -+#include <linux/platform_device.h> -+#include <linux/regulator/consumer.h> -+#include <linux/slab.h> -+ -+#define LRADC_CTRL 0x00 -+#define LRADC_INTC 0x04 -+#define LRADC_INTS 0x08 -+#define LRADC_DATA0 0x0c -+#define LRADC_DATA1 0x10 -+ -+/* LRADC_CTRL bits */ -+#define FIRST_CONVERT_DLY(x) ((x) << 24) /* 8 bits */ -+#define CHAN_SELECT(x) ((x) << 22) /* 2 bits */ -+#define CONTINUE_TIME_SEL(x) ((x) << 16) /* 4 bits */ -+#define KEY_MODE_SEL(x) ((x) << 12) /* 2 bits */ -+#define LEVELA_B_CNT(x) ((x) << 8) /* 4 bits */ -+#define HOLD_EN(x) ((x) << 6) -+#define LEVELB_VOL(x) ((x) << 4) /* 2 bits */ -+#define SAMPLE_RATE(x) ((x) << 2) /* 2 bits */ -+#define ENABLE(x) ((x) << 0) -+ -+/* LRADC_INTC and LRADC_INTS bits */ -+#define CHAN1_KEYUP_IRQ BIT(12) -+#define CHAN1_ALRDY_HOLD_IRQ BIT(11) -+#define CHAN1_HOLD_IRQ BIT(10) -+#define CHAN1_KEYDOWN_IRQ BIT(9) -+#define CHAN1_DATA_IRQ BIT(8) -+#define CHAN0_KEYUP_IRQ BIT(4) -+#define CHAN0_ALRDY_HOLD_IRQ BIT(3) -+#define CHAN0_HOLD_IRQ BIT(2) -+#define CHAN0_KEYDOWN_IRQ BIT(1) -+#define CHAN0_DATA_IRQ BIT(0) -+ -+struct sun4i_lradc_keymap { -+ u32 voltage; -+ u32 keycode; -+}; -+ -+struct sun4i_lradc_data { -+ struct device *dev; -+ struct input_dev *input; -+ void __iomem *base; -+ struct regulator *vref_supply; -+ struct sun4i_lradc_keymap *chan0_map; -+ u32 chan0_map_count; -+ u32 chan0_keycode; -+ u32 vref; -+}; -+ -+static irqreturn_t sun4i_lradc_irq(int irq, void *dev_id) -+{ -+ struct sun4i_lradc_data *lradc = dev_id; -+ u32 i, ints, val, voltage, diff, keycode = 0, closest = 0xffffffff; -+ -+ ints = readl(lradc->base + LRADC_INTS); -+ -+ /* -+ * lradc supports only one keypress at a time, release does not give -+ * any info as to which key was released, so we cache the keycode. -+ */ -+ if ((ints & CHAN0_KEYDOWN_IRQ) && lradc->chan0_keycode == 0) { -+ val = readl(lradc->base + LRADC_DATA0) & 0x3f; -+ voltage = val * lradc->vref / 63; -+ -+ for (i = 0; i < lradc->chan0_map_count; i++) { -+ diff = abs(lradc->chan0_map[i].voltage - voltage); -+ if (diff < closest) { -+ closest = diff; -+ keycode = lradc->chan0_map[i].keycode; -+ } -+ } -+ -+ lradc->chan0_keycode = keycode; -+ input_report_key(lradc->input, lradc->chan0_keycode, 1); -+ } -+ -+ if (ints & CHAN0_KEYUP_IRQ) { -+ input_report_key(lradc->input, lradc->chan0_keycode, 0); -+ lradc->chan0_keycode = 0; -+ } -+ -+ input_sync(lradc->input); -+ -+ writel(ints, lradc->base + LRADC_INTS); -+ -+ return IRQ_HANDLED; -+} -+ -+static int sun4i_lradc_open(struct input_dev *dev) -+{ -+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev); -+ int ret; -+ -+ ret = regulator_enable(lradc->vref_supply); -+ if (ret) -+ return ret; -+ -+ /* lradc Vref internally is divided by 2/3 */ -+ lradc->vref = regulator_get_voltage(lradc->vref_supply) * 2 / 3; -+ -+ /* -+ * Set sample time to 4 ms / 250 Hz. Wait 2 * 4 ms for key to -+ * stabilize on press, wait (1 + 1) * 4 ms for key release -+ */ -+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) | -+ SAMPLE_RATE(0) | ENABLE(1), lradc->base + LRADC_CTRL); -+ -+ writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC); -+ -+ return 0; -+} -+ -+static void sun4i_lradc_close(struct input_dev *dev) -+{ -+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev); -+ -+ /* Disable lradc, leave other settings unchanged */ -+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) | -+ SAMPLE_RATE(2), lradc->base + LRADC_CTRL); -+ writel(0, lradc->base + LRADC_INTC); -+ -+ regulator_disable(lradc->vref_supply); -+} -+ -+static int sun4i_lradc_probe(struct platform_device *pdev) -+{ -+ struct sun4i_lradc_data *lradc; -+ struct device *dev = &pdev->dev; -+ struct device_node *pp, *np = dev->of_node; -+ u32 channel; -+ int i, ret; -+ -+ lradc = devm_kzalloc(dev, sizeof(struct sun4i_lradc_data), GFP_KERNEL); -+ if (!lradc) -+ return -ENOMEM; -+ -+ lradc->chan0_map_count = of_get_child_count(np); -+ lradc->chan0_map = devm_kmalloc(dev, lradc->chan0_map_count * -+ sizeof(struct sun4i_lradc_keymap), GFP_KERNEL); -+ if (!lradc->chan0_map) -+ return -ENOMEM; -+ -+ i = 0; -+ for_each_child_of_node(np, pp) { -+ struct sun4i_lradc_keymap *map = &lradc->chan0_map[i]; -+ -+ ret = of_property_read_u32(pp, "channel", &channel); -+ if (ret || channel != 0) { -+ dev_err(dev, "%s: Inval channel prop\n", pp->name); -+ return -EINVAL; -+ } -+ -+ ret = of_property_read_u32(pp, "voltage", &map->voltage); -+ if (ret) { -+ dev_err(dev, "%s: Inval voltage prop\n", pp->name); -+ return -EINVAL; -+ } -+ -+ ret = of_property_read_u32(pp, "linux,code", &map->keycode); -+ if (ret) { -+ dev_err(dev, "%s: Inval linux,code prop\n", pp->name); -+ return -EINVAL; -+ } -+ -+ i++; -+ } -+ -+ lradc->vref_supply = devm_regulator_get(dev, "vref"); -+ if (IS_ERR(lradc->vref_supply)) -+ return PTR_ERR(lradc->vref_supply); -+ -+ lradc->dev = dev; -+ lradc->input = devm_input_allocate_device(dev); -+ if (!lradc->input) -+ return -ENOMEM; -+ -+ lradc->input->name = pdev->name; -+ lradc->input->phys = "sun4i_lradc/input0"; -+ lradc->input->open = sun4i_lradc_open; -+ lradc->input->close = sun4i_lradc_close; -+ lradc->input->id.bustype = BUS_HOST; -+ lradc->input->id.vendor = 0x0001; -+ lradc->input->id.product = 0x0001; -+ lradc->input->id.version = 0x0100; -+ lradc->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY); -+ for (i = 0; i < lradc->chan0_map_count; i++) -+ set_bit(lradc->chan0_map[i].keycode, lradc->input->keybit); -+ input_set_drvdata(lradc->input, lradc); -+ -+ lradc->base = devm_ioremap_resource(dev, -+ platform_get_resource(pdev, IORESOURCE_MEM, 0)); -+ if (IS_ERR(lradc->base)) -+ return PTR_ERR(lradc->base); -+ -+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), sun4i_lradc_irq, -+ 0, "sun4i-a10-lradc-keys", lradc); -+ if (ret) -+ return ret; -+ -+ ret = input_register_device(lradc->input); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, lradc); -+ return 0; -+} -+ -+static const struct of_device_id sun4i_lradc_of_match[] = { -+ { .compatible = "allwinner,sun4i-a10-lradc-keys", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match); -+ -+static struct platform_driver sun4i_lradc_driver = { -+ .driver = { -+ .name = "sun4i-a10-lradc-keys", -+ .of_match_table = of_match_ptr(sun4i_lradc_of_match), -+ }, -+ .probe = sun4i_lradc_probe, -+}; -+ -+module_platform_driver(sun4i_lradc_driver); -+ -+MODULE_DESCRIPTION("Allwinner sun4i low res adc attached tablet keys driver"); -+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch b/target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch deleted file mode 100644 index d2298a4826..0000000000 --- a/target/linux/sunxi/patches-3.18/111-dt-sun4i-add-lradc.patch +++ /dev/null @@ -1,26 +0,0 @@ -From f39ea4358d2e4b939b8ca55ee344d3c8fdfc0a6a Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Jan 2014 19:51:36 +0100 -Subject: [PATCH] ARM: dts: sun4i: Add lradc node - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/sun4i-a10.dtsi -+++ b/arch/arm/boot/dts/sun4i-a10.dtsi -@@ -669,6 +669,13 @@ - status = "disabled"; - }; - -+ lradc: lradc@01c22800 { -+ compatible = "allwinner,sun4i-a10-lradc-keys"; -+ reg = <0x01c22800 0x100>; -+ interrupts = <31>; -+ status = "disabled"; -+ }; -+ - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; diff --git a/target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch b/target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch deleted file mode 100644 index edc9016aa9..0000000000 --- a/target/linux/sunxi/patches-3.18/112-dt-sun5i-add-lradc.patch +++ /dev/null @@ -1,167 +0,0 @@ -From 3bf1194692f3a275e0776d3c0b6f17826cc01baa Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Jan 2014 19:50:33 +0100 -Subject: [PATCH] ARM: dts: sun5i: Add lradc node - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 45 ++++++++++++++++++++++-- - arch/arm/boot/dts/sun5i-a10s.dtsi | 7 ++++ - arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 45 ++++++++++++++++++++++-- - arch/arm/boot/dts/sun5i-a13.dtsi | 7 ++++ - 4 files changed, 100 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts -+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts -@@ -12,8 +12,9 @@ - */ - - /dts-v1/; --/include/ "sun5i-a10s.dtsi" --/include/ "sunxi-common-regulators.dtsi" -+#include "sun5i-a10s.dtsi" -+#include "sunxi-common-regulators.dtsi" -+#include <dt-bindings/input/input.h> - - / { - model = "Olimex A10s-Olinuxino Micro"; -@@ -98,6 +99,46 @@ - }; - }; - -+ lradc: lradc@01c22800 { -+ vref-supply = <®_vcc3v0>; -+ status = "okay"; -+ -+ button@191 { -+ label = "Volume Up"; -+ linux,code = <KEY_VOLUMEUP>; -+ channel = <0>; -+ voltage = <191274>; -+ }; -+ -+ button@392 { -+ label = "Volume Down"; -+ linux,code = <KEY_VOLUMEDOWN>; -+ channel = <0>; -+ voltage = <392644>; -+ }; -+ -+ button@601 { -+ label = "Menu"; -+ linux,code = <KEY_MENU>; -+ channel = <0>; -+ voltage = <601151>; -+ }; -+ -+ button@795 { -+ label = "Enter"; -+ linux,code = <KEY_ENTER>; -+ channel = <0>; -+ voltage = <795090>; -+ }; -+ -+ button@987 { -+ label = "Home"; -+ linux,code = <KEY_HOMEPAGE>; -+ channel = <0>; -+ voltage = <987387>; -+ }; -+ }; -+ - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; ---- a/arch/arm/boot/dts/sun5i-a10s.dtsi -+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi -@@ -520,6 +520,13 @@ - reg = <0x01c20c90 0x10>; - }; - -+ lradc: lradc@01c22800 { -+ compatible = "allwinner,sun4i-a10-lradc-keys"; -+ reg = <0x01c22800 0x100>; -+ interrupts = <31>; -+ status = "disabled"; -+ }; -+ - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; ---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts -+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts -@@ -12,8 +12,9 @@ - */ - - /dts-v1/; --/include/ "sun5i-a13.dtsi" --/include/ "sunxi-common-regulators.dtsi" -+#include "sun5i-a13.dtsi" -+#include "sunxi-common-regulators.dtsi" -+#include <dt-bindings/input/input.h> - - / { - model = "Olimex A13-Olinuxino"; -@@ -66,6 +67,46 @@ - }; - }; - -+ lradc: lradc@01c22800 { -+ vref-supply = <®_vcc3v0>; -+ status = "okay"; -+ -+ button@191 { -+ label = "Volume Up"; -+ linux,code = <KEY_VOLUMEUP>; -+ channel = <0>; -+ voltage = <191274>; -+ }; -+ -+ button@392 { -+ label = "Volume Down"; -+ linux,code = <KEY_VOLUMEDOWN>; -+ channel = <0>; -+ voltage = <392644>; -+ }; -+ -+ button@601 { -+ label = "Menu"; -+ linux,code = <KEY_MENU>; -+ channel = <0>; -+ voltage = <601151>; -+ }; -+ -+ button@795 { -+ label = "Enter"; -+ linux,code = <KEY_ENTER>; -+ channel = <0>; -+ voltage = <795090>; -+ }; -+ -+ button@987 { -+ label = "Home"; -+ linux,code = <KEY_HOMEPAGE>; -+ channel = <0>; -+ voltage = <987387>; -+ }; -+ }; -+ - uart1: serial@01c28400 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; ---- a/arch/arm/boot/dts/sun5i-a13.dtsi -+++ b/arch/arm/boot/dts/sun5i-a13.dtsi -@@ -468,6 +468,13 @@ - reg = <0x01c20c90 0x10>; - }; - -+ lradc: lradc@01c22800 { -+ compatible = "allwinner,sun4i-a10-lradc-keys"; -+ reg = <0x01c22800 0x100>; -+ interrupts = <31>; -+ status = "disabled"; -+ }; -+ - sid: eeprom@01c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; diff --git a/target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch b/target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch deleted file mode 100644 index ae2c383069..0000000000 --- a/target/linux/sunxi/patches-3.18/113-dt-sun7i-add-lradc.patch +++ /dev/null @@ -1,102 +0,0 @@ -From a735a9b354ebc1a17b648ef8c3482c71fdbf40da Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 1 Jan 2014 20:26:21 +0100 -Subject: [PATCH] ARM: dts: sun7i: Add lradc node - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 59 ++++++++++++++++++++++++- - arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++ - 2 files changed, 64 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts -+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts -@@ -12,8 +12,9 @@ - */ - - /dts-v1/; --/include/ "sun7i-a20.dtsi" --/include/ "sunxi-common-regulators.dtsi" -+#include "sun7i-a20.dtsi" -+#include "sunxi-common-regulators.dtsi" -+#include <dt-bindings/input/input.h> - - / { - model = "Olimex A20-Olinuxino Micro"; -@@ -100,6 +101,60 @@ - }; - }; - -+ lradc: lradc@01c22800 { -+ vref-supply = <®_vcc3v0>; -+ status = "okay"; -+ -+ button@191 { -+ label = "Volume Up"; -+ linux,code = <KEY_VOLUMEUP>; -+ channel = <0>; -+ voltage = <191274>; -+ }; -+ -+ button@392 { -+ label = "Volume Down"; -+ linux,code = <KEY_VOLUMEDOWN>; -+ channel = <0>; -+ voltage = <392644>; -+ }; -+ -+ button@601 { -+ label = "Menu"; -+ linux,code = <KEY_MENU>; -+ channel = <0>; -+ voltage = <601151>; -+ }; -+ -+ button@795 { -+ label = "Search"; -+ linux,code = <KEY_SEARCH>; -+ channel = <0>; -+ voltage = <795090>; -+ }; -+ -+ button@987 { -+ label = "Home"; -+ linux,code = <KEY_HOMEPAGE>; -+ channel = <0>; -+ voltage = <987387>; -+ }; -+ -+ button@1184 { -+ label = "Esc"; -+ linux,code = <KEY_ESC>; -+ channel = <0>; -+ voltage = <1184678>; -+ }; -+ -+ button@1398 { -+ label = "Enter"; -+ linux,code = <KEY_ENTER>; -+ channel = <0>; -+ voltage = <1398804>; -+ }; -+ }; -+ - uart0: serial@01c28000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -911,6 +911,13 @@ - status = "disabled"; - }; - -+ lradc: lradc@01c22800 { -+ compatible = "allwinner,sun4i-a10-lradc-keys"; -+ reg = <0x01c22800 0x100>; -+ interrupts = <0 31 4>; -+ status = "disabled"; -+ }; -+ - sid: eeprom@01c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200>; diff --git a/target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch b/target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch deleted file mode 100644 index 331c93b5a8..0000000000 --- a/target/linux/sunxi/patches-3.18/115-input-sun4i-ts-update-temp-curve.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 2e2493cd07405dfa88e53199b47bdbbb5336fdce Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 16 Jun 2014 20:01:12 +0200 -Subject: [PATCH] touchscreen: sun4i-ts: A10 (sun4i) has a different - temperature curve - -Testing has revealed that the temperature in the rtp controller of the A10 -(sun4i) SoC has a different curve then on the A13 (sun5i) and later models. - -Add a new sun5i-a13-ts compatible to differentiate the newer models and -set the curve based on the compatible string. - -This fixes the temperature reported on the A10 being much higher then -expected. - -Note the new curve is still not ideal on all A10-s, that seems to have to -do with there being a large spread between different A10-s out there. - -Reported-by: Tong Zhang <lovewilliam@gmail.com> -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - .../devicetree/bindings/input/touchscreen/sun4i.txt | 2 +- - drivers/input/touchscreen/sun4i-ts.c | 13 ++++++++++++- - 2 files changed, 13 insertions(+), 2 deletions(-) - ---- a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt -+++ b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt -@@ -2,7 +2,7 @@ sun4i resistive touchscreen controller - -------------------------------------- - - Required properties: -- - compatible: "allwinner,sun4i-a10-ts" -+ - compatible: "allwinner,sun4i-a10-ts" or "allwinner,sun5i-a13-ts" - - reg: mmio address range of the chip - - interrupts: interrupt to which the chip is connected - ---- a/drivers/input/touchscreen/sun4i-ts.c -+++ b/drivers/input/touchscreen/sun4i-ts.c -@@ -111,6 +111,8 @@ struct sun4i_ts_data { - unsigned int irq; - bool ignore_fifo_data; - int temp_data; -+ int temp_offset; -+ int temp_step; - }; - - static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val) -@@ -189,7 +191,8 @@ static ssize_t show_temp(struct device * - if (ts->temp_data == -1) - return -EAGAIN; - -- return sprintf(buf, "%d\n", (ts->temp_data - 1447) * 100); -+ return sprintf(buf, "%d\n", -+ (ts->temp_data - ts->temp_offset) * ts->temp_step); - } - - static ssize_t show_temp_label(struct device *dev, -@@ -224,6 +227,13 @@ static int sun4i_ts_probe(struct platfor - ts->dev = dev; - ts->ignore_fifo_data = true; - ts->temp_data = -1; -+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-ts")) { -+ ts->temp_offset = 1900; -+ ts->temp_step = 100; -+ } else { -+ ts->temp_offset = 1447; -+ ts->temp_step = 100; -+ } - - ts_attached = of_property_read_bool(np, "allwinner,ts-attached"); - if (ts_attached) { -@@ -318,6 +328,7 @@ static int sun4i_ts_remove(struct platfo - - static const struct of_device_id sun4i_ts_of_match[] = { - { .compatible = "allwinner,sun4i-a10-ts", }, -+ { .compatible = "allwinner,sun5i-a13-ts", }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, sun4i_ts_of_match); diff --git a/target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch b/target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch deleted file mode 100644 index fe8dcdbc0a..0000000000 --- a/target/linux/sunxi/patches-3.18/116-dt-sunxi-update-compats-for-tempcurves.patch +++ /dev/null @@ -1,51 +0,0 @@ -From ff774d842a2bf9136b9c7ddd7f5085a9062705ac Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 16 Jun 2014 20:06:43 +0200 -Subject: [PATCH] ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and - later - -The touchscreen controller in the A13 and later has a different temperature -curve than the one in the original A10, change the compatible for the A13 and -later so that the kernel will use the correct curve. - -Reported-by: Tong Zhang <lovewilliam@gmail.com> -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- - arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- - arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/sun5i-a10s.dtsi -+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi -@@ -533,7 +533,7 @@ - }; - - rtp: rtp@01c25000 { -- compatible = "allwinner,sun4i-a10-ts"; -+ compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - }; ---- a/arch/arm/boot/dts/sun5i-a13.dtsi -+++ b/arch/arm/boot/dts/sun5i-a13.dtsi -@@ -481,7 +481,7 @@ - }; - - rtp: rtp@01c25000 { -- compatible = "allwinner,sun4i-a10-ts"; -+ compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - }; ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -924,7 +924,7 @@ - }; - - rtp: rtp@01c25000 { -- compatible = "allwinner,sun4i-a10-ts"; -+ compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <0 29 4>; - }; diff --git a/target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch b/target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch deleted file mode 100644 index 28ed6a3b2d..0000000000 --- a/target/linux/sunxi/patches-3.18/130-input-add-axp20x-pek.patch +++ /dev/null @@ -1,332 +0,0 @@ -From 63d559304a15ffead2fa1014b93dbcabf516c257 Mon Sep 17 00:00:00 2001 -From: Carlo Caione <carlo@caione.org> -Date: Mon, 19 May 2014 21:47:45 +0200 -Subject: [PATCH] input: misc: Add driver for AXP20x Power Enable Key - -This patch add support for the Power Enable Key found on MFD AXP202 and -AXP209. Besides the basic support for the button, the driver adds two -entries in sysfs to configure the time delay for power on/off. - -Signed-off-by: Carlo Caione <carlo@caione.org> -Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> ---- - drivers/input/misc/Kconfig | 11 ++ - drivers/input/misc/Makefile | 1 + - drivers/input/misc/axp20x-pek.c | 281 ++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 293 insertions(+) - create mode 100644 drivers/input/misc/axp20x-pek.c - ---- a/drivers/input/misc/Kconfig -+++ b/drivers/input/misc/Kconfig -@@ -404,6 +404,17 @@ config INPUT_RETU_PWRBUTTON - To compile this driver as a module, choose M here. The module will - be called retu-pwrbutton. - -+config INPUT_AXP20X_PEK -+ tristate "X-Powers AXP20X power button driver" -+ depends on MFD_AXP20X -+ help -+ Say Y here if you want to enable power key reporting via the -+ AXP20X PMIC. -+ -+ To compile this driver as a module, choose M here. The module will -+ be called axp20x-pek. -+ -+ - config INPUT_TWL4030_PWRBUTTON - tristate "TWL4030 Power button Driver" - depends on TWL4030_CORE ---- a/drivers/input/misc/Makefile -+++ b/drivers/input/misc/Makefile -@@ -54,6 +54,7 @@ obj-$(CONFIG_INPUT_POWERMATE) += powerm - obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o - obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o - obj-$(CONFIG_INPUT_RETU_PWRBUTTON) += retu-pwrbutton.o -+obj-$(CONFIG_INPUT_AXP20X_PEK) += axp20x-pek.o - obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER) += rotary_encoder.o - obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o - obj-$(CONFIG_INPUT_SIRFSOC_ONKEY) += sirfsoc-onkey.o ---- /dev/null -+++ b/drivers/input/misc/axp20x-pek.c -@@ -0,0 +1,281 @@ -+/* -+ * axp20x power button driver. -+ * -+ * Copyright (C) 2013 Carlo Caione <carlo@caione.org> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/errno.h> -+#include <linux/irq.h> -+#include <linux/init.h> -+#include <linux/input.h> -+#include <linux/interrupt.h> -+#include <linux/kernel.h> -+#include <linux/mfd/axp20x.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+#include <linux/slab.h> -+ -+#define AXP20X_PEK_STARTUP_MASK (0xc0) -+#define AXP20X_PEK_SHUTDOWN_MASK (0x03) -+ -+struct axp20x_pek { -+ struct axp20x_dev *axp20x; -+ struct input_dev *input; -+ int irq_dbr; -+ int irq_dbf; -+}; -+ -+struct axp20x_time { -+ unsigned int time; -+ unsigned int idx; -+}; -+ -+static const struct axp20x_time startup_time[] = { -+ { .time = 128, .idx = 0 }, -+ { .time = 1000, .idx = 2 }, -+ { .time = 3000, .idx = 1 }, -+ { .time = 2000, .idx = 3 }, -+}; -+ -+static const struct axp20x_time shutdown_time[] = { -+ { .time = 4000, .idx = 0 }, -+ { .time = 6000, .idx = 1 }, -+ { .time = 8000, .idx = 2 }, -+ { .time = 10000, .idx = 3 }, -+}; -+ -+struct axp20x_pek_ext_attr { -+ const struct axp20x_time *p_time; -+ unsigned int mask; -+}; -+ -+static struct axp20x_pek_ext_attr axp20x_pek_startup_ext_attr = { -+ .p_time = startup_time, -+ .mask = AXP20X_PEK_STARTUP_MASK, -+}; -+ -+static struct axp20x_pek_ext_attr axp20x_pek_shutdown_ext_attr = { -+ .p_time = shutdown_time, -+ .mask = AXP20X_PEK_SHUTDOWN_MASK, -+}; -+ -+static struct axp20x_pek_ext_attr *get_axp_ext_attr(struct device_attribute *attr) -+{ -+ return container_of(attr, struct dev_ext_attribute, attr)->var; -+} -+ -+static ssize_t axp20x_show_ext_attr(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev); -+ struct axp20x_pek_ext_attr *axp20x_ea = get_axp_ext_attr(attr); -+ unsigned int val; -+ int ret, i; -+ -+ ret = regmap_read(axp20x_pek->axp20x->regmap, AXP20X_PEK_KEY, &val); -+ if (ret != 0) -+ return ret; -+ -+ val &= axp20x_ea->mask; -+ val >>= ffs(axp20x_ea->mask) - 1; -+ -+ for (i = 0; i < 4; i++) -+ if (val == axp20x_ea->p_time[i].idx) -+ val = axp20x_ea->p_time[i].time; -+ -+ return sprintf(buf, "%u\n", val); -+} -+ -+static ssize_t axp20x_store_ext_attr(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct axp20x_pek *axp20x_pek = dev_get_drvdata(dev); -+ struct axp20x_pek_ext_attr *axp20x_ea = get_axp_ext_attr(attr); -+ char val_str[20]; -+ size_t len; -+ int ret, i; -+ unsigned int val, idx = 0; -+ unsigned int best_err = UINT_MAX; -+ -+ val_str[sizeof(val_str) - 1] = '\0'; -+ strncpy(val_str, buf, sizeof(val_str) - 1); -+ len = strlen(val_str); -+ -+ if (len && val_str[len - 1] == '\n') -+ val_str[len - 1] = '\0'; -+ -+ ret = kstrtouint(val_str, 10, &val); -+ if (ret) -+ return ret; -+ -+ for (i = 3; i >= 0; i--) { -+ unsigned int err; -+ -+ err = abs(axp20x_ea->p_time[i].time - val); -+ if (err < best_err) { -+ best_err = err; -+ idx = axp20x_ea->p_time[i].idx; -+ } -+ -+ if (!err) -+ break; -+ } -+ -+ idx <<= ffs(axp20x_ea->mask) - 1; -+ ret = regmap_update_bits(axp20x_pek->axp20x->regmap, -+ AXP20X_PEK_KEY, -+ axp20x_ea->mask, idx); -+ if (ret != 0) -+ return -EINVAL; -+ return count; -+} -+ -+static struct dev_ext_attribute axp20x_dev_attr_startup = { -+ .attr = __ATTR(startup, 0644, axp20x_show_ext_attr, axp20x_store_ext_attr), -+ .var = &axp20x_pek_startup_ext_attr -+}; -+ -+static struct dev_ext_attribute axp20x_dev_attr_shutdown = { -+ .attr = __ATTR(shutdown, 0644, axp20x_show_ext_attr, axp20x_store_ext_attr), -+ .var = &axp20x_pek_shutdown_ext_attr -+}; -+ -+static irqreturn_t axp20x_pek_irq(int irq, void *pwr) -+{ -+ struct input_dev *idev = pwr; -+ struct axp20x_pek *axp20x_pek = input_get_drvdata(idev); -+ -+ if (irq == axp20x_pek->irq_dbr) -+ input_report_key(idev, KEY_POWER, true); -+ else if (irq == axp20x_pek->irq_dbf) -+ input_report_key(idev, KEY_POWER, false); -+ -+ input_sync(idev); -+ -+ return IRQ_HANDLED; -+} -+ -+static int axp20x_pek_probe(struct platform_device *pdev) -+{ -+ struct axp20x_pek *axp20x_pek; -+ struct axp20x_dev *axp20x; -+ struct input_dev *idev; -+ int error; -+ -+ axp20x_pek = devm_kzalloc(&pdev->dev, sizeof(struct axp20x_pek), -+ GFP_KERNEL); -+ if (!axp20x_pek) -+ return -ENOMEM; -+ -+ axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent); -+ axp20x = axp20x_pek->axp20x; -+ -+ axp20x_pek->irq_dbr = platform_get_irq_byname(pdev, "PEK_DBR"); -+ if (axp20x_pek->irq_dbr < 0) { -+ dev_err(&pdev->dev, "No IRQ for PEK_DBR, error=%d\n", -+ axp20x_pek->irq_dbr); -+ return axp20x_pek->irq_dbr; -+ } -+ axp20x_pek->irq_dbr = regmap_irq_get_virq(axp20x->regmap_irqc, -+ axp20x_pek->irq_dbr); -+ -+ axp20x_pek->irq_dbf = platform_get_irq_byname(pdev, "PEK_DBF"); -+ if (axp20x_pek->irq_dbf < 0) { -+ dev_err(&pdev->dev, "No IRQ for PEK_DBF, error=%d\n", -+ axp20x_pek->irq_dbf); -+ return axp20x_pek->irq_dbf; -+ } -+ axp20x_pek->irq_dbf = regmap_irq_get_virq(axp20x->regmap_irqc, -+ axp20x_pek->irq_dbf); -+ -+ axp20x_pek->input = devm_input_allocate_device(&pdev->dev); -+ if (!axp20x_pek->input) -+ return -ENOMEM; -+ -+ idev = axp20x_pek->input; -+ -+ idev->name = "axp20x-pek"; -+ idev->phys = "m1kbd/input2"; -+ idev->dev.parent = &pdev->dev; -+ -+ input_set_capability(idev, EV_KEY, KEY_POWER); -+ -+ input_set_drvdata(idev, axp20x_pek); -+ -+ error = devm_request_any_context_irq(&pdev->dev, axp20x_pek->irq_dbr, -+ axp20x_pek_irq, 0, -+ "axp20x-pek-dbr", idev); -+ if (error < 0) { -+ dev_err(axp20x->dev, "Failed to request dbr IRQ#%d: %d\n", -+ axp20x_pek->irq_dbr, error); -+ -+ return error; -+ } -+ -+ error = devm_request_any_context_irq(&pdev->dev, axp20x_pek->irq_dbf, -+ axp20x_pek_irq, 0, -+ "axp20x-pek-dbf", idev); -+ if (error < 0) { -+ dev_err(axp20x->dev, "Failed to request dbf IRQ#%d: %d\n", -+ axp20x_pek->irq_dbf, error); -+ return error; -+ } -+ -+ error = device_create_file(&pdev->dev, &axp20x_dev_attr_startup.attr); -+ if (error) -+ return error; -+ -+ error = device_create_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr); -+ if (error) -+ goto clear_startup_attr; -+ -+ error = input_register_device(idev); -+ if (error) { -+ dev_err(axp20x->dev, "Can't register input device: %d\n", error); -+ goto clear_attr; -+ } -+ -+ platform_set_drvdata(pdev, axp20x_pek); -+ -+ return 0; -+ -+clear_attr: -+ device_remove_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr); -+ -+clear_startup_attr: -+ device_remove_file(&pdev->dev, &axp20x_dev_attr_startup.attr); -+ -+ return error; -+} -+ -+int axp20x_pek_remove(struct platform_device *pdev) -+{ -+ device_remove_file(&pdev->dev, &axp20x_dev_attr_shutdown.attr); -+ device_remove_file(&pdev->dev, &axp20x_dev_attr_startup.attr); -+ -+ return 0; -+} -+ -+static struct platform_driver axp20x_pek_driver = { -+ .probe = axp20x_pek_probe, -+ .remove = axp20x_pek_remove, -+ .driver = { -+ .name = "axp20x-pek", -+ .owner = THIS_MODULE, -+ }, -+}; -+module_platform_driver(axp20x_pek_driver); -+ -+MODULE_DESCRIPTION("axp20x Power Button"); -+MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch b/target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch deleted file mode 100644 index 49560c39a4..0000000000 --- a/target/linux/sunxi/patches-3.18/150-pwm-add-sunxi-driver.patch +++ /dev/null @@ -1,402 +0,0 @@ ---- a/drivers/pwm/Kconfig -+++ b/drivers/pwm/Kconfig -@@ -263,6 +263,15 @@ config PWM_STI - To compile this driver as a module, choose M here: the module - will be called pwm-sti. - -+config PWM_SUN4I -+ tristate "Allwinner sun4i PWM support" -+ depends on ARCH_SUNXI || COMPILE_TEST -+ help -+ Generic PWM framework driver for Allwinner sun4i and sun7i SoCs. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called pwm-sun4i. -+ - config PWM_TEGRA - tristate "NVIDIA Tegra PWM support" - depends on ARCH_TEGRA ---- a/drivers/pwm/Makefile -+++ b/drivers/pwm/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockch - obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o - obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o - obj-$(CONFIG_PWM_STI) += pwm-sti.o -+obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o - obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o - obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o - obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o ---- /dev/null -+++ b/drivers/pwm/pwm-sun4i.c -@@ -0,0 +1,371 @@ -+/* -+ * Driver for Allwinner sun4i Pulse Width Modulation Controller -+ * -+ * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> -+ * -+ * Licensed under GPLv2. -+ */ -+ -+#include <linux/bitops.h> -+#include <linux/clk.h> -+#include <linux/err.h> -+#include <linux/io.h> -+#include <linux/module.h> -+#include <linux/mutex.h> -+#include <linux/of.h> -+#include <linux/of_device.h> -+#include <linux/platform_device.h> -+#include <linux/pwm.h> -+#include <linux/slab.h> -+#include <linux/time.h> -+ -+#define PWM_CTRL_REG 0x0 -+ -+#define PWM_CH_PRD_BASE 0x4 -+#define PWM_CH_PRD_OFFSET 0x4 -+#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch)) -+ -+#define PWMCH_OFFSET 15 -+#define PWM_PRESCAL_MASK GENMASK(3, 0) -+#define PWM_PRESCAL_OFF 0 -+#define PWM_EN BIT(4) -+#define PWM_ACT_STATE BIT(5) -+#define PWM_CLK_GATING BIT(6) -+#define PWM_MODE BIT(7) -+#define PWM_PULSE BIT(8) -+#define PWM_BYPASS BIT(9) -+ -+#define PWM_RDY_BASE 28 -+#define PWM_RDY_OFFSET 1 -+#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) -+ -+#define PWM_PRD(prd) (((prd) - 1) << 16) -+#define PWM_PRD_MASK GENMASK(15, 0) -+ -+#define PWM_DTY_MASK GENMASK(15, 0) -+ -+#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) -+ -+static const u32 prescaler_table[] = { -+ 120, -+ 180, -+ 240, -+ 360, -+ 480, -+ 0, -+ 0, -+ 0, -+ 12000, -+ 24000, -+ 36000, -+ 48000, -+ 72000, -+ 0, -+ 0, -+ 0, /* Actually 1 but tested separately */ -+}; -+ -+struct sun4i_pwm_data { -+ bool has_prescaler_bypass; -+ bool has_rdy; -+}; -+ -+struct sun4i_pwm_chip { -+ struct pwm_chip chip; -+ struct clk *clk; -+ void __iomem *base; -+ struct mutex ctrl_lock; -+ const struct sun4i_pwm_data *data; -+}; -+ -+static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip) -+{ -+ return container_of(chip, struct sun4i_pwm_chip, chip); -+} -+ -+static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip, -+ unsigned long offset) -+{ -+ return readl(chip->base + offset); -+} -+ -+static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip, -+ u32 val, unsigned long offset) -+{ -+ writel(val, chip->base + offset); -+} -+ -+static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, -+ int duty_ns, int period_ns) -+{ -+ struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); -+ u32 clk_rate, prd, dty, val, clk_gate; -+ u64 div = 0; -+ unsigned int prescaler = 0; -+ int err; -+ -+ clk_rate = clk_get_rate(sun4i_pwm->clk); -+ -+ if (sun4i_pwm->data->has_prescaler_bypass) { -+ /* First, test without any prescaler when available */ -+ prescaler = PWM_PRESCAL_MASK; -+ /* -+ * When not using any prescaler, the clock period in nanoseconds -+ * is not an integer so round it half up instead of -+ * truncating to get less surprising values. -+ */ -+ div = clk_rate * (u64)period_ns + NSEC_PER_SEC/2; -+ do_div(div, NSEC_PER_SEC); -+ if (div - 1 > PWM_PRD_MASK) -+ prescaler = 0; -+ } -+ -+ if (prescaler == 0) { -+ /* Go up from the first divider */ -+ for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) { -+ if (!prescaler_table[prescaler]) -+ continue; -+ div = clk_rate / prescaler_table[prescaler]; -+ div = div * (u64)period_ns; -+ do_div(div, NSEC_PER_SEC); -+ if (div - 1 <= PWM_PRD_MASK) -+ break; -+ } -+ -+ if (div - 1 > PWM_PRD_MASK) { -+ dev_err(chip->dev, "period exceeds the maximum value\n"); -+ return -EINVAL; -+ } -+ } -+ -+ prd = div; -+ div *= duty_ns; -+ do_div(div, period_ns); -+ dty = div; -+ -+ err = clk_prepare_enable(sun4i_pwm->clk); -+ if (err) { -+ dev_err(chip->dev, "failed to enable PWM clock\n"); -+ return err; -+ } -+ -+ mutex_lock(&sun4i_pwm->ctrl_lock); -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ -+ if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) { -+ mutex_unlock(&sun4i_pwm->ctrl_lock); -+ clk_disable_unprepare(sun4i_pwm->clk); -+ return -EBUSY; -+ } -+ -+ clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ if (clk_gate) { -+ val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ } -+ -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); -+ val |= BIT_CH(prescaler, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ -+ val = (dty & PWM_DTY_MASK) | PWM_PRD(prd); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); -+ -+ if (clk_gate) { -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ val |= clk_gate; -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ } -+ -+ mutex_unlock(&sun4i_pwm->ctrl_lock); -+ clk_disable_unprepare(sun4i_pwm->clk); -+ -+ return 0; -+} -+ -+static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, -+ enum pwm_polarity polarity) -+{ -+ struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); -+ u32 val; -+ int ret; -+ -+ ret = clk_prepare_enable(sun4i_pwm->clk); -+ if (ret) { -+ dev_err(chip->dev, "failed to enable PWM clock\n"); -+ return ret; -+ } -+ -+ mutex_lock(&sun4i_pwm->ctrl_lock); -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ -+ if (polarity != PWM_POLARITY_NORMAL) -+ val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); -+ else -+ val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); -+ -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ -+ mutex_unlock(&sun4i_pwm->ctrl_lock); -+ clk_disable_unprepare(sun4i_pwm->clk); -+ -+ return 0; -+} -+ -+static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); -+ u32 val; -+ int ret; -+ -+ ret = clk_prepare_enable(sun4i_pwm->clk); -+ if (ret) { -+ dev_err(chip->dev, "failed to enable PWM clock\n"); -+ return ret; -+ } -+ -+ mutex_lock(&sun4i_pwm->ctrl_lock); -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ val |= BIT_CH(PWM_EN, pwm->hwpwm); -+ val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ mutex_unlock(&sun4i_pwm->ctrl_lock); -+ -+ return 0; -+} -+ -+static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); -+ u32 val; -+ -+ mutex_lock(&sun4i_pwm->ctrl_lock); -+ val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); -+ val &= ~BIT_CH(PWM_EN, pwm->hwpwm); -+ val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG); -+ mutex_unlock(&sun4i_pwm->ctrl_lock); -+ -+ clk_disable_unprepare(sun4i_pwm->clk); -+} -+ -+static const struct pwm_ops sun4i_pwm_ops = { -+ .config = sun4i_pwm_config, -+ .set_polarity = sun4i_pwm_set_polarity, -+ .enable = sun4i_pwm_enable, -+ .disable = sun4i_pwm_disable, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct sun4i_pwm_data sun4i_pwm_data_a10 = { -+ .has_prescaler_bypass = false, -+ .has_rdy = false, -+}; -+ -+static const struct sun4i_pwm_data sun4i_pwm_data_a20 = { -+ .has_prescaler_bypass = true, -+ .has_rdy = true, -+}; -+ -+static const struct of_device_id sun4i_pwm_dt_ids[] = { -+ { -+ .compatible = "allwinner,sun4i-a10-pwm", -+ .data = &sun4i_pwm_data_a10, -+ }, { -+ .compatible = "allwinner,sun7i-a20-pwm", -+ .data = &sun4i_pwm_data_a20, -+ }, { -+ /* sentinel */ -+ }, -+}; -+MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); -+ -+static int sun4i_pwm_probe(struct platform_device *pdev) -+{ -+ struct sun4i_pwm_chip *pwm; -+ struct resource *res; -+ u32 val; -+ int i, ret; -+ const struct of_device_id *match; -+ -+ match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev); -+ -+ pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); -+ if (!pwm) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ pwm->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(pwm->base)) -+ return PTR_ERR(pwm->base); -+ -+ pwm->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(pwm->clk)) -+ return PTR_ERR(pwm->clk); -+ -+ pwm->chip.dev = &pdev->dev; -+ pwm->chip.ops = &sun4i_pwm_ops; -+ pwm->chip.base = -1; -+ pwm->chip.npwm = 2; -+ pwm->chip.can_sleep = true; -+ pwm->chip.of_xlate = of_pwm_xlate_with_flags; -+ pwm->chip.of_pwm_n_cells = 3; -+ pwm->data = match->data; -+ -+ mutex_init(&pwm->ctrl_lock); -+ -+ ret = pwmchip_add(&pwm->chip); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); -+ goto error; -+ } -+ -+ platform_set_drvdata(pdev, pwm); -+ -+ ret = clk_prepare_enable(pwm->clk); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to enable PWM clock\n"); -+ goto clk_error; -+ } -+ -+ val = sun4i_pwm_readl(pwm, PWM_CTRL_REG); -+ for (i = 0; i < pwm->chip.npwm; i++) { -+ if (!(val & BIT_CH(PWM_ACT_STATE, i))) -+ pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED; -+ } -+ clk_disable_unprepare(pwm->clk); -+ -+ return 0; -+ -+clk_error: -+ pwmchip_remove(&pwm->chip); -+ -+error: -+ mutex_destroy(&pwm->ctrl_lock); -+ return ret; -+} -+ -+static int sun4i_pwm_remove(struct platform_device *pdev) -+{ -+ struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); -+ -+ mutex_destroy(&pwm->ctrl_lock); -+ -+ return pwmchip_remove(&pwm->chip); -+} -+ -+static struct platform_driver sun4i_pwm_driver = { -+ .driver = { -+ .name = "sun4i-pwm", -+ .of_match_table = sun4i_pwm_dt_ids, -+ }, -+ .probe = sun4i_pwm_probe, -+ .remove = sun4i_pwm_remove, -+}; -+module_platform_driver(sun4i_pwm_driver); -+ -+MODULE_ALIAS("platform:sun4i-pwm"); -+MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); -+MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch b/target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch deleted file mode 100644 index dcbb3a4767..0000000000 --- a/target/linux/sunxi/patches-3.18/200-mmc-add-sdio-function-subnode.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 8c2057afe84c074ef7cd3ee2ec8e9bed835b9e93 Mon Sep 17 00:00:00 2001 -From: Sascha Hauer <s.hauer@pengutronix.de> -Date: Wed, 21 May 2014 19:50:04 +0200 -Subject: [PATCH] mmc: Add SDIO function devicetree subnode parsing - -This adds SDIO devicetree subnode parsing to the mmc core. While -SDIO devices are runtime probable they sometimes need nonprobable -additional information on embedded systems, like an additional gpio -interrupt or a clock. This patch makes it possible to supply this -information from the devicetree. SDIO drivers will find a pointer -to the devicenode in their devices of_node pointer. - -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> -[hdegoede@redhat.com: Misc. cleanups] -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/mmc/core/bus.c | 4 ++++ - drivers/mmc/core/core.c | 28 ++++++++++++++++++++++++++++ - drivers/mmc/core/core.h | 3 +++ - drivers/mmc/core/sdio_bus.c | 11 +++++++++++ - 4 files changed, 46 insertions(+) - ---- a/drivers/mmc/core/bus.c -+++ b/drivers/mmc/core/bus.c -@@ -16,6 +16,7 @@ - #include <linux/err.h> - #include <linux/slab.h> - #include <linux/stat.h> -+#include <linux/of.h> - #include <linux/pm_runtime.h> - - #include <linux/mmc/card.h> -@@ -352,6 +353,8 @@ int mmc_add_card(struct mmc_card *card) - #endif - mmc_init_context_info(card->host); - -+ card->dev.of_node = mmc_of_find_child_device(card->host, 0); -+ - ret = device_add(&card->dev); - if (ret) - return ret; -@@ -380,6 +383,7 @@ void mmc_remove_card(struct mmc_card *ca - mmc_hostname(card->host), card->rca); - } - device_del(&card->dev); -+ of_node_put(card->dev.of_node); - } - - put_device(&card->dev); ---- a/drivers/mmc/core/core.c -+++ b/drivers/mmc/core/core.c -@@ -1231,6 +1231,34 @@ EXPORT_SYMBOL(mmc_of_parse_voltage); - - #endif /* CONFIG_OF */ - -+static int mmc_of_get_func_num(struct device_node *node) -+{ -+ u32 reg; -+ int ret; -+ -+ ret = of_property_read_u32(node, "reg", ®); -+ if (ret < 0) -+ return ret; -+ -+ return reg; -+} -+ -+struct device_node *mmc_of_find_child_device(struct mmc_host *host, -+ unsigned func_num) -+{ -+ struct device_node *node; -+ -+ if (!host->parent || !host->parent->of_node) -+ return NULL; -+ -+ for_each_child_of_node(host->parent->of_node, node) { -+ if (mmc_of_get_func_num(node) == func_num) -+ return node; -+ } -+ -+ return NULL; -+} -+ - #ifdef CONFIG_REGULATOR - - /** ---- a/drivers/mmc/core/core.h -+++ b/drivers/mmc/core/core.h -@@ -32,6 +32,9 @@ struct mmc_bus_ops { - void mmc_attach_bus(struct mmc_host *host, const struct mmc_bus_ops *ops); - void mmc_detach_bus(struct mmc_host *host); - -+struct device_node *mmc_of_find_child_device(struct mmc_host *host, -+ unsigned func_num); -+ - void mmc_init_erase(struct mmc_card *card); - - void mmc_set_chip_select(struct mmc_host *host, int mode); ---- a/drivers/mmc/core/sdio_bus.c -+++ b/drivers/mmc/core/sdio_bus.c -@@ -22,7 +22,9 @@ - #include <linux/mmc/card.h> - #include <linux/mmc/host.h> - #include <linux/mmc/sdio_func.h> -+#include <linux/of.h> - -+#include "core.h" - #include "sdio_cis.h" - #include "sdio_bus.h" - -@@ -303,6 +305,13 @@ static void sdio_acpi_set_handle(struct - static inline void sdio_acpi_set_handle(struct sdio_func *func) {} - #endif - -+static void sdio_set_of_node(struct sdio_func *func) -+{ -+ struct mmc_host *host = func->card->host; -+ -+ func->dev.of_node = mmc_of_find_child_device(host, func->num); -+} -+ - /* - * Register a new SDIO function with the driver model. - */ -@@ -312,6 +321,7 @@ int sdio_add_func(struct sdio_func *func - - dev_set_name(&func->dev, "%s:%d", mmc_card_id(func->card), func->num); - -+ sdio_set_of_node(func); - sdio_acpi_set_handle(func); - ret = device_add(&func->dev); - if (ret == 0) { -@@ -335,6 +345,7 @@ void sdio_remove_func(struct sdio_func * - - dev_pm_domain_detach(&func->dev, false); - device_del(&func->dev); -+ of_node_put(func->dev.of_node); - put_device(&func->dev); - } - diff --git a/target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch b/target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch deleted file mode 100644 index e2cfeb711c..0000000000 --- a/target/linux/sunxi/patches-3.18/201-dt-sun7i-add-oob-irq-to-bcm-sdio-wifi.patch +++ /dev/null @@ -1,64 +0,0 @@ -From e4127db9b980a5684c537d9010ed2aaa05a1e79a Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Sat, 24 May 2014 20:53:49 +0200 -Subject: [PATCH] ARM: dts: sun7i: Add OOB irq support to boards with broadcom - sdio wifi - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 11 +++++++++++ - arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 11 +++++++++++ - 2 files changed, 22 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts -+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts -@@ -31,12 +31,23 @@ - }; - - mmc3: mmc@01c12000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <10 8>; /* PH10 / EINT10 */ -+ interrupt-names = "host-wake"; -+ }; - }; - - usbphy: phy@01c13400 { ---- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts -+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts -@@ -29,12 +29,23 @@ - }; - - mmc3: mmc@01c12000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; - vmmc-supply = <®_vmmc3>; - bus-width = <4>; - non-removable; - status = "okay"; -+ -+ brcmf: bcrmf@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <10 8>; /* PH10 / EINT10 */ -+ interrupt-names = "host-wake"; -+ }; - }; - - usbphy: phy@01c13400 { diff --git a/target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch b/target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch deleted file mode 100644 index 9c0d969232..0000000000 --- a/target/linux/sunxi/patches-3.18/202-dt-sun7i-add-bluetooth-to-cubietruck.patch +++ /dev/null @@ -1,73 +0,0 @@ -From c6e2b7dad39a7887f935458d1c8de84db06243e1 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai <wens@csie.org> -Date: Thu, 26 Dec 2013 17:15:47 +0800 -Subject: [PATCH] ARM: dts: sun7i: add bluetooth module to CubieTruck DTS - -The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The -Bluetooth part is a BCM20710 IC connected to UART2 in the A20 -SoC. The IC also takes a 32.768 KHz low power clock input, a power -enable signal and a wake signal via GPIO. - -The Bluetooth module supports out-of-band interrupt signaling via -GPIO, but this is not supported in this patch. ---- - arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 36 ++++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts -+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts -@@ -103,6 +103,20 @@ - allwinner,drive = <0>; - allwinner,pull = <0>; - }; -+ -+ bt_pwr_pin: bt_pwr_pin@0 { -+ allwinner,pins = "PH18"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ bt_wake_pin: bt_wake_pin@0 { -+ allwinner,pins = "PH24"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; - }; - - pwm: pwm@01c20e00 { -@@ -123,6 +137,12 @@ - status = "okay"; - }; - -+ uart2: serial@01c28800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins_a>; -+ status = "okay"; -+ }; -+ - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; -@@ -214,4 +234,20 @@ - enable-active-high; - gpio = <&pio 7 9 0>; - }; -+ -+ rfkill-switches { -+ compatible = "simple-bus"; -+ pinctrl-names = "default"; -+ -+ rfkill_bt { -+ compatible = "rfkill-gpio"; -+ pinctrl-0 = <&bt_pwr_pin>, <&clk_out_a_pins_a>; -+ rfkill-name = "bt"; -+ rfkill-type = <2>; -+ bt_shutdown-gpios = <0>, <&pio 7 18 0>; /* PH18 */ -+ bt_reset-gpios = <&pio 7 24 0>; /* PH24 */ -+ clocks = <&clk_out_a>; -+ clock-frequency = <32768>; -+ }; -+ }; - }; diff --git a/target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch b/target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch deleted file mode 100644 index f03e2d9df3..0000000000 --- a/target/linux/sunxi/patches-3.18/270-dt-sun7i-add-ss-to-a20.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -577,6 +577,14 @@ - status = "disabled"; - }; - -+ crypto: crypto-engine@01c15000 { -+ compatible = "allwinner,sun7i-a20-crypto"; -+ reg = <0x01c15000 0x1000>; -+ interrupts = <0 86 4>; -+ clocks = <&ahb_gates 5>, <&ss_clk>; -+ clock-names = "ahb", "mod"; -+ }; -+ - spi2: spi@01c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; diff --git a/target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch b/target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch deleted file mode 100644 index 0788c6f84c..0000000000 --- a/target/linux/sunxi/patches-3.18/271-crypto-add-ss.patch +++ /dev/null @@ -1,1493 +0,0 @@ ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -437,4 +437,21 @@ config CRYPTO_DEV_QCE - hardware. To compile this driver as a module, choose M here. The - module will be called qcrypto. - -+config CRYPTO_DEV_SUNXI_SS -+ tristate "Support for Allwinner Security System cryptographic accelerator" -+ depends on ARCH_SUNXI -+ select CRYPTO_MD5 -+ select CRYPTO_SHA1 -+ select CRYPTO_AES -+ select CRYPTO_DES -+ select CRYPTO_BLKCIPHER -+ help -+ Some Allwinner SoC have a crypto accelerator named -+ Security System. Select this if you want to use it. -+ The Security System handle AES/DES/3DES ciphers in CBC mode -+ and SHA1 and MD5 hash algorithms. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sunxi-ss. -+ - endif # CRYPTO_HW ---- a/drivers/crypto/Makefile -+++ b/drivers/crypto/Makefile -@@ -25,3 +25,4 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += tali - obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ - obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/ - obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ -+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss/ ---- /dev/null -+++ b/drivers/crypto/sunxi-ss/Makefile -@@ -0,0 +1,2 @@ -+obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o -+sunxi-ss-y += sunxi-ss-core.o sunxi-ss-hash.o sunxi-ss-cipher.o ---- /dev/null -+++ b/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c -@@ -0,0 +1,489 @@ -+/* -+ * sunxi-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC -+ * -+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com> -+ * -+ * This file add support for AES cipher with 128,192,256 bits -+ * keysize in CBC mode. -+ * Add support also for DES and 3DES in CBC mode. -+ * -+ * You could find the datasheet in Documentation/arm/sunxi/README -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+#include "sunxi-ss.h" -+ -+extern struct sunxi_ss_ctx *ss; -+ -+static int sunxi_ss_cipher(struct ablkcipher_request *areq, u32 mode) -+{ -+ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq); -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ const char *cipher_type; -+ -+ if (areq->nbytes == 0) -+ return 0; -+ -+ if (areq->info == NULL) { -+ dev_err(ss->dev, "ERROR: Empty IV\n"); -+ return -EINVAL; -+ } -+ -+ if (areq->src == NULL || areq->dst == NULL) { -+ dev_err(ss->dev, "ERROR: Some SGs are NULL\n"); -+ return -EINVAL; -+ } -+ -+ cipher_type = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm)); -+ -+ if (strcmp("cbc(aes)", cipher_type) == 0) { -+ mode |= SS_OP_AES | SS_CBC | SS_ENABLED | op->keymode; -+ return sunxi_ss_aes_poll(areq, mode); -+ } -+ -+ if (strcmp("cbc(des)", cipher_type) == 0) { -+ mode |= SS_OP_DES | SS_CBC | SS_ENABLED | op->keymode; -+ return sunxi_ss_des_poll(areq, mode); -+ } -+ -+ if (strcmp("cbc(des3_ede)", cipher_type) == 0) { -+ mode |= SS_OP_3DES | SS_CBC | SS_ENABLED | op->keymode; -+ return sunxi_ss_des_poll(areq, mode); -+ } -+ -+ dev_err(ss->dev, "ERROR: Cipher %s not handled\n", cipher_type); -+ return -EINVAL; -+} -+ -+int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq) -+{ -+ return sunxi_ss_cipher(areq, SS_ENCRYPTION); -+} -+ -+int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq) -+{ -+ return sunxi_ss_cipher(areq, SS_DECRYPTION); -+} -+ -+int sunxi_ss_cipher_init(struct crypto_tfm *tfm) -+{ -+ struct sunxi_tfm_ctx *op = crypto_tfm_ctx(tfm); -+ -+ memset(op, 0, sizeof(struct sunxi_tfm_ctx)); -+ return 0; -+} -+ -+/* -+ * Optimized function for the case where we have only one SG, -+ * so we can use kmap_atomic -+ */ -+static int sunxi_ss_aes_poll_atomic(struct ablkcipher_request *areq) -+{ -+ u32 spaces; -+ struct scatterlist *in_sg = areq->src; -+ struct scatterlist *out_sg = areq->dst; -+ void *src_addr; -+ void *dst_addr; -+ unsigned int ileft = areq->nbytes; -+ unsigned int oleft = areq->nbytes; -+ unsigned int todo; -+ u32 *src32; -+ u32 *dst32; -+ u32 rx_cnt = 32; -+ u32 tx_cnt = 0; -+ int i; -+ -+ src_addr = kmap_atomic(sg_page(in_sg)) + in_sg->offset; -+ if (src_addr == NULL) { -+ dev_err(ss->dev, "kmap_atomic error for src SG\n"); -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ -+ dst_addr = kmap_atomic(sg_page(out_sg)) + out_sg->offset; -+ if (dst_addr == NULL) { -+ dev_err(ss->dev, "kmap_atomic error for dst SG\n"); -+ writel(0, ss->base + SS_CTL); -+ kunmap_atomic(src_addr); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ -+ src32 = (u32 *)src_addr; -+ dst32 = (u32 *)dst_addr; -+ ileft = areq->nbytes / 4; -+ oleft = areq->nbytes / 4; -+ i = 0; -+ do { -+ if (ileft > 0 && rx_cnt > 0) { -+ todo = min(rx_cnt, ileft); -+ ileft -= todo; -+ do { -+ writel_relaxed(*src32++, -+ ss->base + -+ SS_RXFIFO); -+ todo--; -+ } while (todo > 0); -+ } -+ if (tx_cnt > 0) { -+ todo = min(tx_cnt, oleft); -+ oleft -= todo; -+ do { -+ *dst32++ = readl_relaxed(ss->base + -+ SS_TXFIFO); -+ todo--; -+ } while (todo > 0); -+ } -+ spaces = readl_relaxed(ss->base + SS_FCSR); -+ rx_cnt = SS_RXFIFO_SPACES(spaces); -+ tx_cnt = SS_TXFIFO_SPACES(spaces); -+ } while (oleft > 0); -+ writel(0, ss->base + SS_CTL); -+ kunmap_atomic(src_addr); -+ kunmap_atomic(dst_addr); -+ mutex_unlock(&ss->lock); -+ return 0; -+} -+ -+int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode) -+{ -+ u32 spaces; -+ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq); -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ unsigned int ivsize = crypto_ablkcipher_ivsize(tfm); -+ /* when activating SS, the default FIFO space is 32 */ -+ u32 rx_cnt = 32; -+ u32 tx_cnt = 0; -+ u32 v; -+ int i; -+ struct scatterlist *in_sg = areq->src; -+ struct scatterlist *out_sg = areq->dst; -+ void *src_addr; -+ void *dst_addr; -+ unsigned int ileft = areq->nbytes; -+ unsigned int oleft = areq->nbytes; -+ unsigned int sgileft = areq->src->length; -+ unsigned int sgoleft = areq->dst->length; -+ unsigned int todo; -+ u32 *src32; -+ u32 *dst32; -+ -+ mutex_lock(&ss->lock); -+ -+ for (i = 0; i < op->keylen; i += 4) -+ writel(*(op->key + i/4), ss->base + SS_KEY0 + i); -+ -+ if (areq->info != NULL) { -+ for (i = 0; i < 4 && i < ivsize / 4; i++) { -+ v = *(u32 *)(areq->info + i * 4); -+ writel(v, ss->base + SS_IV0 + i * 4); -+ } -+ } -+ writel(mode, ss->base + SS_CTL); -+ -+ /* If we have only one SG, we can use kmap_atomic */ -+ if (sg_next(in_sg) == NULL && sg_next(out_sg) == NULL) -+ return sunxi_ss_aes_poll_atomic(areq); -+ -+ /* -+ * If we have more than one SG, we cannot use kmap_atomic since -+ * we hold the mapping too long -+ */ -+ src_addr = kmap(sg_page(in_sg)) + in_sg->offset; -+ if (src_addr == NULL) { -+ dev_err(ss->dev, "KMAP error for src SG\n"); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ dst_addr = kmap(sg_page(out_sg)) + out_sg->offset; -+ if (dst_addr == NULL) { -+ kunmap(sg_page(in_sg)); -+ dev_err(ss->dev, "KMAP error for dst SG\n"); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ src32 = (u32 *)src_addr; -+ dst32 = (u32 *)dst_addr; -+ ileft = areq->nbytes / 4; -+ oleft = areq->nbytes / 4; -+ sgileft = in_sg->length / 4; -+ sgoleft = out_sg->length / 4; -+ do { -+ spaces = readl_relaxed(ss->base + SS_FCSR); -+ rx_cnt = SS_RXFIFO_SPACES(spaces); -+ tx_cnt = SS_TXFIFO_SPACES(spaces); -+ todo = min3(rx_cnt, ileft, sgileft); -+ if (todo > 0) { -+ ileft -= todo; -+ sgileft -= todo; -+ } -+ while (todo > 0) { -+ writel_relaxed(*src32++, ss->base + SS_RXFIFO); -+ todo--; -+ } -+ if (in_sg != NULL && sgileft == 0 && ileft > 0) { -+ kunmap(sg_page(in_sg)); -+ in_sg = sg_next(in_sg); -+ while (in_sg != NULL && in_sg->length == 0) -+ in_sg = sg_next(in_sg); -+ if (in_sg != NULL && ileft > 0) { -+ src_addr = kmap(sg_page(in_sg)) + in_sg->offset; -+ if (src_addr == NULL) { -+ dev_err(ss->dev, "ERROR: KMAP for src SG\n"); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ src32 = src_addr; -+ sgileft = in_sg->length / 4; -+ } -+ } -+ /* do not test oleft since when oleft == 0 we have finished */ -+ todo = min3(tx_cnt, oleft, sgoleft); -+ if (todo > 0) { -+ oleft -= todo; -+ sgoleft -= todo; -+ } -+ while (todo > 0) { -+ *dst32++ = readl_relaxed(ss->base + SS_TXFIFO); -+ todo--; -+ } -+ if (out_sg != NULL && sgoleft == 0 && oleft >= 0) { -+ kunmap(sg_page(out_sg)); -+ out_sg = sg_next(out_sg); -+ while (out_sg != NULL && out_sg->length == 0) -+ out_sg = sg_next(out_sg); -+ if (out_sg != NULL && oleft > 0) { -+ dst_addr = kmap(sg_page(out_sg)) + -+ out_sg->offset; -+ if (dst_addr == NULL) { -+ dev_err(ss->dev, "KMAP error\n"); -+ mutex_unlock(&ss->lock); -+ return -EINVAL; -+ } -+ dst32 = dst_addr; -+ sgoleft = out_sg->length / 4; -+ } -+ } -+ } while (oleft > 0); -+ -+ writel_relaxed(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return 0; -+} -+ -+/* -+ * Pure CPU way of doing DES/3DES with SS -+ * Since DES and 3DES SGs could be smaller than 4 bytes, I use sg_copy_to_buffer -+ * for "linearize" them. -+ * The problem with that is that I alloc (2 x areq->nbytes) for buf_in/buf_out -+ * TODO: change this system, I need to support other mode than CBC where len -+ * is not a multiple of 4 and the hack of linearize use too much memory -+ * SGsrc -> buf_in -> SS -> buf_out -> SGdst -+ */ -+int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode) -+{ -+ u32 value, spaces; -+ size_t nb_in_sg_tx, nb_in_sg_rx; -+ size_t ir, it; -+ struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq); -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ unsigned int ivsize = crypto_ablkcipher_ivsize(tfm); -+ u32 tx_cnt = 0; -+ u32 rx_cnt = 0; -+ u32 v; -+ int i; -+ int no_chunk = 1; -+ struct scatterlist *in_sg = areq->src; -+ struct scatterlist *out_sg = areq->dst; -+ -+ /* -+ * if we have only SGs with size multiple of 4, -+ * we can use the SS AES function -+ */ -+ while (in_sg != NULL && no_chunk == 1) { -+ if ((in_sg->length % 4) != 0) -+ no_chunk = 0; -+ in_sg = sg_next(in_sg); -+ } -+ while (out_sg != NULL && no_chunk == 1) { -+ if ((out_sg->length % 4) != 0) -+ no_chunk = 0; -+ out_sg = sg_next(out_sg); -+ } -+ -+ if (no_chunk == 1) -+ return sunxi_ss_aes_poll(areq, mode); -+ -+ in_sg = areq->src; -+ out_sg = areq->dst; -+ -+ nb_in_sg_rx = sg_nents(in_sg); -+ nb_in_sg_tx = sg_nents(out_sg); -+ -+ /* -+ * buf_in and buf_out are allocated only one time -+ * then we keep the buffer until driver end -+ * the allocation can only grow more -+ * we do not reduce it for simplification -+ */ -+ mutex_lock(&ss->bufin_lock); -+ if (ss->buf_in == NULL) { -+ ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL); -+ ss->buf_in_size = areq->nbytes; -+ } else { -+ if (areq->nbytes > ss->buf_in_size) { -+ kfree(ss->buf_in); -+ ss->buf_in = kmalloc(areq->nbytes, GFP_KERNEL); -+ ss->buf_in_size = areq->nbytes; -+ } -+ } -+ if (ss->buf_in == NULL) { -+ ss->buf_in_size = 0; -+ mutex_unlock(&ss->bufin_lock); -+ dev_err(ss->dev, "Unable to allocate pages.\n"); -+ return -ENOMEM; -+ } -+ mutex_lock(&ss->bufout_lock); -+ if (ss->buf_out == NULL) { -+ ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL); -+ if (ss->buf_out == NULL) { -+ ss->buf_out_size = 0; -+ mutex_unlock(&ss->bufin_lock); -+ mutex_unlock(&ss->bufout_lock); -+ dev_err(ss->dev, "Unable to allocate pages.\n"); -+ return -ENOMEM; -+ } -+ ss->buf_out_size = areq->nbytes; -+ } else { -+ if (areq->nbytes > ss->buf_out_size) { -+ kfree(ss->buf_out); -+ ss->buf_out = kmalloc(areq->nbytes, GFP_KERNEL); -+ if (ss->buf_out == NULL) { -+ ss->buf_out_size = 0; -+ mutex_unlock(&ss->bufin_lock); -+ mutex_unlock(&ss->bufout_lock); -+ dev_err(ss->dev, "Unable to allocate pages.\n"); -+ return -ENOMEM; -+ } -+ ss->buf_out_size = areq->nbytes; -+ } -+ } -+ -+ sg_copy_to_buffer(areq->src, nb_in_sg_rx, ss->buf_in, areq->nbytes); -+ -+ ir = 0; -+ it = 0; -+ mutex_lock(&ss->lock); -+ -+ for (i = 0; i < op->keylen; i += 4) -+ writel(*(op->key + i/4), ss->base + SS_KEY0 + i); -+ if (areq->info != NULL) { -+ for (i = 0; i < 4 && i < ivsize / 4; i++) { -+ v = *(u32 *)(areq->info + i * 4); -+ writel(v, ss->base + SS_IV0 + i * 4); -+ } -+ } -+ writel(mode, ss->base + SS_CTL); -+ -+ do { -+ if (rx_cnt == 0 || tx_cnt == 0) { -+ spaces = readl(ss->base + SS_FCSR); -+ rx_cnt = SS_RXFIFO_SPACES(spaces); -+ tx_cnt = SS_TXFIFO_SPACES(spaces); -+ } -+ if (rx_cnt > 0 && ir < areq->nbytes) { -+ do { -+ value = *(u32 *)(ss->buf_in + ir); -+ writel(value, ss->base + SS_RXFIFO); -+ ir += 4; -+ rx_cnt--; -+ } while (rx_cnt > 0 && ir < areq->nbytes); -+ } -+ if (tx_cnt > 0 && it < areq->nbytes) { -+ do { -+ value = readl(ss->base + SS_TXFIFO); -+ *(u32 *)(ss->buf_out + it) = value; -+ it += 4; -+ tx_cnt--; -+ } while (tx_cnt > 0 && it < areq->nbytes); -+ } -+ if (ir == areq->nbytes) { -+ mutex_unlock(&ss->bufin_lock); -+ ir++; -+ } -+ } while (it < areq->nbytes); -+ -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ -+ /* -+ * a simple optimization, since we dont need the hardware for this copy -+ * we release the lock and do the copy. With that we gain 5/10% perf -+ */ -+ sg_copy_from_buffer(areq->dst, nb_in_sg_tx, ss->buf_out, areq->nbytes); -+ -+ mutex_unlock(&ss->bufout_lock); -+ return 0; -+} -+ -+/* check and set the AES key, prepare the mode to be used */ -+int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen) -+{ -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ -+ switch (keylen) { -+ case 128 / 8: -+ op->keymode = SS_AES_128BITS; -+ break; -+ case 192 / 8: -+ op->keymode = SS_AES_192BITS; -+ break; -+ case 256 / 8: -+ op->keymode = SS_AES_256BITS; -+ break; -+ default: -+ dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen); -+ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); -+ return -EINVAL; -+ } -+ op->keylen = keylen; -+ memcpy(op->key, key, keylen); -+ return 0; -+} -+ -+/* check and set the DES key, prepare the mode to be used */ -+int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen) -+{ -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ -+ if (keylen != DES_KEY_SIZE) { -+ dev_err(ss->dev, "Invalid keylen %u\n", keylen); -+ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); -+ return -EINVAL; -+ } -+ op->keylen = keylen; -+ memcpy(op->key, key, keylen); -+ return 0; -+} -+ -+/* check and set the 3DES key, prepare the mode to be used */ -+int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen) -+{ -+ struct sunxi_tfm_ctx *op = crypto_ablkcipher_ctx(tfm); -+ -+ if (keylen != 3 * DES_KEY_SIZE) { -+ dev_err(ss->dev, "Invalid keylen %u\n", keylen); -+ crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); -+ return -EINVAL; -+ } -+ op->keylen = keylen; -+ memcpy(op->key, key, keylen); -+ return 0; -+} ---- /dev/null -+++ b/drivers/crypto/sunxi-ss/sunxi-ss-core.c -@@ -0,0 +1,318 @@ -+/* -+ * sunxi-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC -+ * -+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com> -+ * -+ * Core file which registers crypto algorithms supported by the SS. -+ * -+ * You could find a link for the datasheet in Documentation/arm/sunxi/README -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+#include <linux/clk.h> -+#include <linux/crypto.h> -+#include <linux/io.h> -+#include <linux/module.h> -+#include <linux/of.h> -+#include <linux/platform_device.h> -+#include <crypto/scatterwalk.h> -+#include <linux/scatterlist.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+ -+#include "sunxi-ss.h" -+ -+struct sunxi_ss_ctx *ss; -+ -+/* -+ * General notes for whole driver: -+ * -+ * After each request the device must be disabled with a write of 0 in SS_CTL -+ * -+ * For performance reason, we use writel_relaxed/read_relaxed for all -+ * operations on RX and TX FIFO and also SS_FCSR. -+ * Excepts for the last write on TX FIFO. -+ * For all other registers, we use writel/readl. -+ * See http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117644 -+ * and http://permalink.gmane.org/gmane.linux.ports.arm.kernel/117640 -+ */ -+ -+static struct ahash_alg sunxi_md5_alg = { -+ .init = sunxi_hash_init, -+ .update = sunxi_hash_update, -+ .final = sunxi_hash_final, -+ .finup = sunxi_hash_finup, -+ .digest = sunxi_hash_digest, -+ .halg = { -+ .digestsize = MD5_DIGEST_SIZE, -+ .base = { -+ .cra_name = "md5", -+ .cra_driver_name = "md5-sunxi-ss", -+ .cra_priority = 300, -+ .cra_alignmask = 3, -+ .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC, -+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct sunxi_req_ctx), -+ .cra_module = THIS_MODULE, -+ .cra_type = &crypto_ahash_type, -+ .cra_init = sunxi_hash_crainit -+ } -+ } -+}; -+ -+static struct ahash_alg sunxi_sha1_alg = { -+ .init = sunxi_hash_init, -+ .update = sunxi_hash_update, -+ .final = sunxi_hash_final, -+ .finup = sunxi_hash_finup, -+ .digest = sunxi_hash_digest, -+ .halg = { -+ .digestsize = SHA1_DIGEST_SIZE, -+ .base = { -+ .cra_name = "sha1", -+ .cra_driver_name = "sha1-sunxi-ss", -+ .cra_priority = 300, -+ .cra_alignmask = 3, -+ .cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC, -+ .cra_blocksize = SHA1_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct sunxi_req_ctx), -+ .cra_module = THIS_MODULE, -+ .cra_type = &crypto_ahash_type, -+ .cra_init = sunxi_hash_crainit -+ } -+ } -+}; -+ -+static struct crypto_alg sunxi_cipher_algs[] = { -+{ -+ .cra_name = "cbc(aes)", -+ .cra_driver_name = "cbc-aes-sunxi-ss", -+ .cra_priority = 300, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .cra_ctxsize = sizeof(struct sunxi_tfm_ctx), -+ .cra_module = THIS_MODULE, -+ .cra_alignmask = 3, -+ .cra_type = &crypto_ablkcipher_type, -+ .cra_init = sunxi_ss_cipher_init, -+ .cra_u = { -+ .ablkcipher = { -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .setkey = sunxi_ss_aes_setkey, -+ .encrypt = sunxi_ss_cipher_encrypt, -+ .decrypt = sunxi_ss_cipher_decrypt, -+ } -+ } -+}, { -+ .cra_name = "cbc(des)", -+ .cra_driver_name = "cbc-des-sunxi-ss", -+ .cra_priority = 300, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .cra_ctxsize = sizeof(struct sunxi_req_ctx), -+ .cra_module = THIS_MODULE, -+ .cra_alignmask = 3, -+ .cra_type = &crypto_ablkcipher_type, -+ .cra_init = sunxi_ss_cipher_init, -+ .cra_u.ablkcipher = { -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ .ivsize = DES_BLOCK_SIZE, -+ .setkey = sunxi_ss_des_setkey, -+ .encrypt = sunxi_ss_cipher_encrypt, -+ .decrypt = sunxi_ss_cipher_decrypt, -+ } -+}, { -+ .cra_name = "cbc(des3_ede)", -+ .cra_driver_name = "cbc-des3-sunxi-ss", -+ .cra_priority = 300, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .cra_ctxsize = sizeof(struct sunxi_req_ctx), -+ .cra_module = THIS_MODULE, -+ .cra_alignmask = 3, -+ .cra_type = &crypto_ablkcipher_type, -+ .cra_init = sunxi_ss_cipher_init, -+ .cra_u.ablkcipher = { -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .setkey = sunxi_ss_des3_setkey, -+ .encrypt = sunxi_ss_cipher_encrypt, -+ .decrypt = sunxi_ss_cipher_decrypt, -+ } -+} -+}; -+ -+static int sunxi_ss_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ u32 v; -+ int err; -+ unsigned long cr; -+ const unsigned long cr_ahb = 24 * 1000 * 1000; -+ const unsigned long cr_mod = 150 * 1000 * 1000; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL); -+ if (ss == NULL) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ss->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(ss->base)) { -+ dev_err(&pdev->dev, "Cannot request MMIO\n"); -+ return PTR_ERR(ss->base); -+ } -+ -+ ss->ssclk = devm_clk_get(&pdev->dev, "mod"); -+ if (IS_ERR(ss->ssclk)) { -+ err = PTR_ERR(ss->ssclk); -+ dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err); -+ return err; -+ } -+ dev_dbg(&pdev->dev, "clock ss acquired\n"); -+ -+ ss->busclk = devm_clk_get(&pdev->dev, "ahb"); -+ if (IS_ERR(ss->busclk)) { -+ err = PTR_ERR(ss->busclk); -+ dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err); -+ return err; -+ } -+ dev_dbg(&pdev->dev, "clock ahb_ss acquired\n"); -+ -+ /* Enable both clocks */ -+ err = clk_prepare_enable(ss->busclk); -+ if (err != 0) { -+ dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); -+ return err; -+ } -+ err = clk_prepare_enable(ss->ssclk); -+ if (err != 0) { -+ dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n"); -+ clk_disable_unprepare(ss->busclk); -+ return err; -+ } -+ -+ /* -+ * Check that clock have the correct rates gived in the datasheet -+ * Try to set the clock to the maximum allowed -+ */ -+ err = clk_set_rate(ss->ssclk, cr_mod); -+ if (err != 0) { -+ dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n"); -+ clk_disable_unprepare(ss->ssclk); -+ clk_disable_unprepare(ss->busclk); -+ return err; -+ } -+ -+ cr = clk_get_rate(ss->busclk); -+ if (cr >= cr_ahb) -+ dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n", -+ cr, cr / 1000000, cr_ahb); -+ else -+ dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n", -+ cr, cr / 1000000, cr_ahb); -+ -+ cr = clk_get_rate(ss->ssclk); -+ if (cr <= cr_mod) -+ if (cr < cr_mod) -+ dev_info(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n", -+ cr, cr / 1000000, cr_mod); -+ else -+ dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n", -+ cr, cr / 1000000, cr_mod); -+ else -+ dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n", -+ cr, cr / 1000000, cr_mod); -+ -+ /* -+ * Datasheet named it "Die Bonding ID" -+ * I expect to be a sort of Security System Revision number. -+ * Since the A80 seems to have an other version of SS -+ * this info could be useful -+ */ -+ writel(SS_ENABLED, ss->base + SS_CTL); -+ v = readl(ss->base + SS_CTL); -+ v >>= 16; -+ v &= 0x07; -+ dev_info(&pdev->dev, "Die ID %d\n", v); -+ writel(0, ss->base + SS_CTL); -+ -+ ss->dev = &pdev->dev; -+ -+ mutex_init(&ss->lock); -+ mutex_init(&ss->bufin_lock); -+ mutex_init(&ss->bufout_lock); -+ -+ err = crypto_register_ahash(&sunxi_md5_alg); -+ if (err) -+ goto error_md5; -+ err = crypto_register_ahash(&sunxi_sha1_alg); -+ if (err) -+ goto error_sha1; -+ err = crypto_register_algs(sunxi_cipher_algs, -+ ARRAY_SIZE(sunxi_cipher_algs)); -+ if (err) -+ goto error_ciphers; -+ -+ return 0; -+error_ciphers: -+ crypto_unregister_ahash(&sunxi_sha1_alg); -+error_sha1: -+ crypto_unregister_ahash(&sunxi_md5_alg); -+error_md5: -+ clk_disable_unprepare(ss->ssclk); -+ clk_disable_unprepare(ss->busclk); -+ return err; -+} -+ -+static int __exit sunxi_ss_remove(struct platform_device *pdev) -+{ -+ if (!pdev->dev.of_node) -+ return 0; -+ -+ crypto_unregister_ahash(&sunxi_md5_alg); -+ crypto_unregister_ahash(&sunxi_sha1_alg); -+ crypto_unregister_algs(sunxi_cipher_algs, -+ ARRAY_SIZE(sunxi_cipher_algs)); -+ -+ if (ss->buf_in != NULL) -+ kfree(ss->buf_in); -+ if (ss->buf_out != NULL) -+ kfree(ss->buf_out); -+ -+ writel(0, ss->base + SS_CTL); -+ clk_disable_unprepare(ss->busclk); -+ clk_disable_unprepare(ss->ssclk); -+ return 0; -+} -+ -+static const struct of_device_id a20ss_crypto_of_match_table[] = { -+ { .compatible = "allwinner,sun7i-a20-crypto" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table); -+ -+static struct platform_driver sunxi_ss_driver = { -+ .probe = sunxi_ss_probe, -+ .remove = __exit_p(sunxi_ss_remove), -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "sunxi-ss", -+ .of_match_table = a20ss_crypto_of_match_table, -+ }, -+}; -+ -+module_platform_driver(sunxi_ss_driver); -+ -+MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>"); ---- /dev/null -+++ b/drivers/crypto/sunxi-ss/sunxi-ss-hash.c -@@ -0,0 +1,445 @@ -+/* -+ * sunxi-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC -+ * -+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com> -+ * -+ * This file add support for MD5 and SHA1. -+ * -+ * You could find the datasheet in Documentation/arm/sunxi/README -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+#include "sunxi-ss.h" -+ -+/* This is a totaly arbitrary value */ -+#define SS_TIMEOUT 100 -+ -+extern struct sunxi_ss_ctx *ss; -+ -+int sunxi_hash_crainit(struct crypto_tfm *tfm) -+{ -+ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), -+ sizeof(struct sunxi_req_ctx)); -+ return 0; -+} -+ -+/* sunxi_hash_init: initialize request context */ -+int sunxi_hash_init(struct ahash_request *areq) -+{ -+ const char *hash_type; -+ struct sunxi_req_ctx *op = ahash_request_ctx(areq); -+ -+ memset(op, 0, sizeof(struct sunxi_req_ctx)); -+ -+ hash_type = crypto_tfm_alg_name(areq->base.tfm); -+ -+ if (strcmp(hash_type, "sha1") == 0) -+ op->mode = SS_OP_SHA1; -+ if (strcmp(hash_type, "md5") == 0) -+ op->mode = SS_OP_MD5; -+ if (op->mode == 0) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rx_cnt; -+ -+inline void ss_writer(const u32 v) -+{ -+ u32 spaces; -+ -+ writel(v, ss->base + SS_RXFIFO); -+ rx_cnt--; -+ while (rx_cnt == 0) { -+ spaces = readl_relaxed(ss->base + SS_FCSR); -+ rx_cnt = SS_RXFIFO_SPACES(spaces); -+ } -+} -+ -+inline void ss_writer_relaxed(const u32 v) -+{ -+ u32 spaces; -+ -+ writel_relaxed(v, ss->base + SS_RXFIFO); -+ rx_cnt--; -+ while (rx_cnt == 0) { -+ spaces = readl_relaxed(ss->base + SS_FCSR); -+ rx_cnt = SS_RXFIFO_SPACES(spaces); -+ } -+} -+ -+/* -+ * sunxi_hash_update: update hash engine -+ * -+ * Could be used for both SHA1 and MD5 -+ * Write data by step of 32bits and put then in the SS. -+ * -+ * Since we cannot leave partial data and hash state in the engine, -+ * we need to get the hash state at the end of this function. -+ * After some work, I have found that we can get the hash state every 64o -+ * -+ * So the first work is to get the number of bytes to write to SS modulo 64 -+ * The extra bytes will go to two different destination: -+ * op->wait for full 32bits word -+ * op->wb (waiting bytes) for partial 32 bits word -+ * So we can have up to (64/4)-1 op->wait words and 0/1/2/3 bytes in wb -+ * -+ * So at the begin of update() -+ * if op->nwait * 4 + areq->nbytes < 64 -+ * => all data writed to wait buffers and end=0 -+ * if not write all nwait to the device and position end to complete to 64o -+ * -+ * example 1: -+ * update1 60o => nwait=15 -+ * update2 60o => need one more word to have 64o -+ * end=4 -+ * so write all data in op->wait and one word of SGs -+ * write remaining data in op->wait -+ * final state op->nwait=14 -+ */ -+int sunxi_hash_update(struct ahash_request *areq) -+{ -+ u32 v, ivmode = 0; -+ unsigned int i = 0; -+ /* -+ * i is the total bytes read from SGs, to be compared to areq->nbytes -+ * i is important because we cannot rely on SG length since the sum of -+ * SG->length could be greater than areq->nbytes -+ */ -+ -+ struct sunxi_req_ctx *op = ahash_request_ctx(areq); -+ struct scatterlist *in_sg; -+ unsigned int in_i = 0; /* advancement in the current SG */ -+ u64 end; -+ /* -+ * end is the position when we need to stop writing to the device, -+ * to be compared to i -+ */ -+ int in_r; -+ void *src_addr; -+ -+ dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x bw=%u ww=%u", -+ __func__, crypto_tfm_alg_name(areq->base.tfm), -+ op->byte_count, areq->nbytes, op->mode, -+ op->nbw, op->nwait); -+ -+ if (areq->nbytes == 0) -+ return 0; -+ -+ end = ((areq->nbytes + op->nwait * 4 + op->nbw) / 64) * 64 -+ - op->nbw - op->nwait * 4; -+ -+ if (end > areq->nbytes || areq->nbytes - end > 63) { -+ dev_err(ss->dev, "ERROR: Bound error %llu %u\n", -+ end, areq->nbytes); -+ return -EINVAL; -+ } -+ -+ if (op->nwait > 0 && end > 0) { -+ /* a precedent update was done */ -+ for (i = 0; i < op->nwait; i++) { -+ ss_writer(op->wait[i]); -+ op->byte_count += 4; -+ } -+ op->nwait = 0; -+ } -+ -+ mutex_lock(&ss->lock); -+ /* -+ * if some data have been processed before, -+ * we need to restore the partial hash state -+ */ -+ if (op->byte_count > 0) { -+ ivmode = SS_IV_ARBITRARY; -+ for (i = 0; i < 5; i++) -+ writel(op->hash[i], ss->base + SS_IV0 + i * 4); -+ } -+ /* Enable the device */ -+ writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL); -+ -+ rx_cnt = 0; -+ i = 0; -+ -+ in_sg = areq->src; -+ src_addr = kmap(sg_page(in_sg)) + in_sg->offset; -+ if (src_addr == NULL) { -+ mutex_unlock(&ss->lock); -+ dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n"); -+ return -EFAULT; -+ } -+ do { -+ /* -+ * step 1, if some bytes remains from last SG, -+ * try to complete them to 4 and send that word -+ */ -+ if (op->nbw > 0) { -+ while (op->nbw < 4 && i < areq->nbytes && -+ in_i < in_sg->length) { -+ op->wb |= (*(u8 *)(src_addr + in_i)) -+ << (8 * op->nbw); -+ dev_dbg(ss->dev, "%s Complete w=%d wb=%x\n", -+ __func__, op->nbw, op->wb); -+ i++; -+ in_i++; -+ op->nbw++; -+ } -+ if (op->nbw == 4) { -+ if (i <= end) { -+ ss_writer(op->wb); -+ op->byte_count += 4; -+ } else { -+ op->wait[op->nwait] = op->wb; -+ op->nwait++; -+ dev_dbg(ss->dev, "%s Keep %u bytes after %llu\n", -+ __func__, op->nwait, end); -+ } -+ op->nbw = 0; -+ op->wb = 0; -+ } -+ } -+ /* step 2, main loop, read data 4bytes at a time */ -+ while (i < areq->nbytes && in_i < in_sg->length) { -+ /* how many bytes we can read, (we need 4) */ -+ in_r = min(in_sg->length - in_i, areq->nbytes - i); -+ if (in_r < 4) { -+ /* Not enough data to write to the device */ -+ op->wb = 0; -+ while (in_r > 0) { -+ op->wb |= (*(u8 *)(src_addr + in_i)) -+ << (8 * op->nbw); -+ dev_dbg(ss->dev, "%s ending bw=%d wb=%x\n", -+ __func__, op->nbw, op->wb); -+ in_r--; -+ i++; -+ in_i++; -+ op->nbw++; -+ } -+ goto nextsg; -+ } -+ v = *(u32 *)(src_addr + in_i); -+ if (i < end) { -+ /* last write must be done without relaxed */ -+ if (i + 4 >= end) -+ ss_writer(v); -+ else -+ ss_writer_relaxed(v); -+ i += 4; -+ op->byte_count += 4; -+ in_i += 4; -+ } else { -+ op->wait[op->nwait] = v; -+ i += 4; -+ in_i += 4; -+ op->nwait++; -+ dev_dbg(ss->dev, "%s Keep word ww=%u after %llu\n", -+ __func__, op->nwait, end); -+ if (op->nwait > 15) { -+ dev_err(ss->dev, "FATAL: Cannot enqueue more, bug?\n"); -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return -EIO; -+ } -+ } -+ } -+nextsg: -+ /* Nothing more to read in this SG */ -+ if (in_i == in_sg->length) { -+ kunmap(sg_page(in_sg)); -+ do { -+ in_sg = sg_next(in_sg); -+ } while (in_sg != NULL && in_sg->length == 0); -+ in_i = 0; -+ if (in_sg != NULL) { -+ src_addr = kmap(sg_page(in_sg)) + in_sg->offset; -+ if (src_addr == NULL) { -+ mutex_unlock(&ss->lock); -+ dev_err(ss->dev, "ERROR: Cannot kmap source buffer\n"); -+ return -EFAULT; -+ } -+ } -+ } -+ } while (in_sg != NULL && i < areq->nbytes); -+ -+ /* ask the device to finish the hashing */ -+ writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); -+ i = 0; -+ do { -+ v = readl(ss->base + SS_CTL); -+ i++; -+ } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0); -+ if (i >= SS_TIMEOUT) { -+ dev_err(ss->dev, "ERROR: %s hash end timeout after %d loop, CTL=%x\n", -+ __func__, i, v); -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return -EIO; -+ } -+ -+ /* get the partial hash */ -+ if (op->mode == SS_OP_SHA1) { -+ for (i = 0; i < 5; i++) -+ op->hash[i] = readl(ss->base + SS_MD0 + i * 4); -+ } else { -+ for (i = 0; i < 4; i++) -+ op->hash[i] = readl(ss->base + SS_MD0 + i * 4); -+ } -+ -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return 0; -+} -+ -+/* -+ * sunxi_hash_final: finalize hashing operation -+ * -+ * If we have some remaining bytes, we write them. -+ * Then ask the SS for finalizing the hashing operation -+ */ -+int sunxi_hash_final(struct ahash_request *areq) -+{ -+ u32 v, ivmode = 0; -+ unsigned int i; -+ int zeros; -+ unsigned int index, padlen; -+ __be64 bits; -+ struct sunxi_req_ctx *op = ahash_request_ctx(areq); -+ -+ dev_dbg(ss->dev, "%s byte=%llu len=%u mode=%x bw=%u %x h=%x ww=%u", -+ __func__, op->byte_count, areq->nbytes, op->mode, -+ op->nbw, op->wb, op->hash[0], op->nwait); -+ -+ mutex_lock(&ss->lock); -+ rx_cnt = 0; -+ -+ /* -+ * if we have already writed something, -+ * restore the partial hash state -+ */ -+ if (op->byte_count > 0) { -+ ivmode = SS_IV_ARBITRARY; -+ for (i = 0; i < 5; i++) -+ writel(op->hash[i], ss->base + SS_IV0 + i * 4); -+ } -+ writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL); -+ -+ /* write the remaining words of the wait buffer */ -+ if (op->nwait > 0) { -+ for (i = 0; i < op->nwait; i++) { -+ v = op->wait[i]; -+ ss_writer(v); -+ op->byte_count += 4; -+ dev_dbg(ss->dev, "%s write %llu i=%u %x\n", -+ __func__, op->byte_count, i, v); -+ } -+ op->nwait = 0; -+ } -+ -+ /* write the remaining bytes of the nbw buffer */ -+ if (op->nbw > 0) { -+ op->wb |= ((1 << 7) << (op->nbw * 8)); -+ ss_writer(op->wb); -+ } else { -+ ss_writer((1 << 7)); -+ } -+ -+ /* -+ * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1) -+ * I take the operations from other md5/sha1 implementations -+ */ -+ -+ /* we have already send 4 more byte of which nbw data */ -+ if (op->mode == SS_OP_MD5) { -+ index = (op->byte_count + 4) & 0x3f; -+ op->byte_count += op->nbw; -+ if (index > 56) -+ zeros = (120 - index) / 4; -+ else -+ zeros = (56 - index) / 4; -+ } else { -+ op->byte_count += op->nbw; -+ index = op->byte_count & 0x3f; -+ padlen = (index < 56) ? (56 - index) : ((64+56) - index); -+ zeros = (padlen - 1) / 4; -+ } -+ for (i = 0; i < zeros; i++) -+ ss_writer(0); -+ -+ /* write the length of data */ -+ if (op->mode == SS_OP_SHA1) { -+ bits = cpu_to_be64(op->byte_count << 3); -+ ss_writer(bits & 0xffffffff); -+ ss_writer((bits >> 32) & 0xffffffff); -+ } else { -+ ss_writer((op->byte_count << 3) & 0xffffffff); -+ ss_writer((op->byte_count >> 29) & 0xffffffff); -+ } -+ -+ /* Tell the SS to stop the hashing */ -+ writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); -+ -+ /* -+ * Wait for SS to finish the hash. -+ * The timeout could happend only in case of bad overcloking -+ * or driver bug. -+ */ -+ i = 0; -+ do { -+ v = readl(ss->base + SS_CTL); -+ i++; -+ } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0); -+ if (i >= SS_TIMEOUT) { -+ dev_err(ss->dev, "ERROR: hash end timeout %d>%d ctl=%x len=%u\n", -+ i, SS_TIMEOUT, v, areq->nbytes); -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return -EIO; -+ } -+ -+ /* Get the hash from the device */ -+ if (op->mode == SS_OP_SHA1) { -+ for (i = 0; i < 5; i++) { -+ v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4)); -+ memcpy(areq->result + i * 4, &v, 4); -+ } -+ } else { -+ for (i = 0; i < 4; i++) { -+ v = readl(ss->base + SS_MD0 + i * 4); -+ memcpy(areq->result + i * 4, &v, 4); -+ } -+ } -+ writel(0, ss->base + SS_CTL); -+ mutex_unlock(&ss->lock); -+ return 0; -+} -+ -+/* sunxi_hash_finup: finalize hashing operation after an update */ -+int sunxi_hash_finup(struct ahash_request *areq) -+{ -+ int err; -+ -+ err = sunxi_hash_update(areq); -+ if (err != 0) -+ return err; -+ -+ return sunxi_hash_final(areq); -+} -+ -+/* combo of init/update/final functions */ -+int sunxi_hash_digest(struct ahash_request *areq) -+{ -+ int err; -+ -+ err = sunxi_hash_init(areq); -+ if (err != 0) -+ return err; -+ -+ err = sunxi_hash_update(areq); -+ if (err != 0) -+ return err; -+ -+ return sunxi_hash_final(areq); -+} ---- /dev/null -+++ b/drivers/crypto/sunxi-ss/sunxi-ss.h -@@ -0,0 +1,193 @@ -+/* -+ * sunxi-ss.c - hardware cryptographic accelerator for Allwinner A20 SoC -+ * -+ * Copyright (C) 2013-2014 Corentin LABBE <clabbe.montjoie@gmail.com> -+ * -+ * Support AES cipher with 128,192,256 bits keysize. -+ * Support MD5 and SHA1 hash algorithms. -+ * Support DES and 3DES -+ * -+ * You could find the datasheet in Documentation/arm/sunxi/README -+ * -+ * Licensed under the GPL-2. -+ */ -+ -+#include <linux/clk.h> -+#include <linux/crypto.h> -+#include <linux/io.h> -+#include <linux/module.h> -+#include <linux/of.h> -+#include <linux/platform_device.h> -+#include <crypto/scatterwalk.h> -+#include <linux/scatterlist.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+#include <crypto/md5.h> -+#include <crypto/sha.h> -+#include <crypto/hash.h> -+#include <crypto/internal/hash.h> -+#include <crypto/aes.h> -+#include <crypto/des.h> -+#include <crypto/internal/rng.h> -+ -+#define SS_CTL 0x00 -+#define SS_KEY0 0x04 -+#define SS_KEY1 0x08 -+#define SS_KEY2 0x0C -+#define SS_KEY3 0x10 -+#define SS_KEY4 0x14 -+#define SS_KEY5 0x18 -+#define SS_KEY6 0x1C -+#define SS_KEY7 0x20 -+ -+#define SS_IV0 0x24 -+#define SS_IV1 0x28 -+#define SS_IV2 0x2C -+#define SS_IV3 0x30 -+ -+#define SS_CNT0 0x34 -+#define SS_CNT1 0x38 -+#define SS_CNT2 0x3C -+#define SS_CNT3 0x40 -+ -+#define SS_FCSR 0x44 -+#define SS_ICSR 0x48 -+ -+#define SS_MD0 0x4C -+#define SS_MD1 0x50 -+#define SS_MD2 0x54 -+#define SS_MD3 0x58 -+#define SS_MD4 0x5C -+ -+#define SS_RXFIFO 0x200 -+#define SS_TXFIFO 0x204 -+ -+/* SS_CTL configuration values */ -+ -+/* PRNG generator mode - bit 15 */ -+#define SS_PRNG_ONESHOT (0 << 15) -+#define SS_PRNG_CONTINUE (1 << 15) -+ -+/* IV mode for hash */ -+#define SS_IV_ARBITRARY (1 << 14) -+ -+/* SS operation mode - bits 12-13 */ -+#define SS_ECB (0 << 12) -+#define SS_CBC (1 << 12) -+#define SS_CNT (2 << 12) -+ -+/* Counter width for CNT mode - bits 10-11 */ -+#define SS_CNT_16BITS (0 << 10) -+#define SS_CNT_32BITS (1 << 10) -+#define SS_CNT_64BITS (2 << 10) -+ -+/* Key size for AES - bits 8-9 */ -+#define SS_AES_128BITS (0 << 8) -+#define SS_AES_192BITS (1 << 8) -+#define SS_AES_256BITS (2 << 8) -+ -+/* Operation direction - bit 7 */ -+#define SS_ENCRYPTION (0 << 7) -+#define SS_DECRYPTION (1 << 7) -+ -+/* SS Method - bits 4-6 */ -+#define SS_OP_AES (0 << 4) -+#define SS_OP_DES (1 << 4) -+#define SS_OP_3DES (2 << 4) -+#define SS_OP_SHA1 (3 << 4) -+#define SS_OP_MD5 (4 << 4) -+#define SS_OP_PRNG (5 << 4) -+ -+/* Data end bit - bit 2 */ -+#define SS_DATA_END (1 << 2) -+ -+/* PRNG start bit - bit 1 */ -+#define SS_PRNG_START (1 << 1) -+ -+/* SS Enable bit - bit 0 */ -+#define SS_DISABLED (0 << 0) -+#define SS_ENABLED (1 << 0) -+ -+/* SS_FCSR configuration values */ -+/* RX FIFO status - bit 30 */ -+#define SS_RXFIFO_FREE (1 << 30) -+ -+/* RX FIFO empty spaces - bits 24-29 */ -+#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f) -+ -+/* TX FIFO status - bit 22 */ -+#define SS_TXFIFO_AVAILABLE (1 << 22) -+ -+/* TX FIFO available spaces - bits 16-21 */ -+#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f) -+ -+#define SS_RXFIFO_EMP_INT_PENDING (1 << 10) -+#define SS_TXFIFO_AVA_INT_PENDING (1 << 8) -+#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2) -+#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0) -+ -+/* SS_ICSR configuration values */ -+#define SS_ICS_DRQ_ENABLE (1 << 4) -+ -+struct sunxi_ss_ctx { -+ void __iomem *base; -+ int irq; -+ struct clk *busclk; -+ struct clk *ssclk; -+ struct device *dev; -+ struct resource *res; -+ void *buf_in; /* pointer to data to be uploaded to the device */ -+ size_t buf_in_size; /* size of buf_in */ -+ void *buf_out; -+ size_t buf_out_size; -+ struct mutex lock; /* control the use of the device */ -+ struct mutex bufout_lock; /* control the use of buf_out*/ -+ struct mutex bufin_lock; /* control the sue of buf_in*/ -+}; -+ -+struct sunxi_tfm_ctx { -+ u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */ -+ u32 keylen; -+ u32 keymode; -+}; -+ -+struct sunxi_req_ctx { -+ u32 mode; -+ u64 byte_count; /* number of bytes "uploaded" to the device */ -+ u32 wb; /* a partial word waiting to be completed and -+ uploaded to the device */ -+ /* number of bytes to be uploaded in the wb word */ -+ unsigned int nbw; -+ u32 hash[5]; -+ u32 wait[64]; -+ unsigned int nwait; -+}; -+ -+#define SS_SEED_LEN (192/8) -+#define SS_DATA_LEN (160/8) -+ -+struct prng_context { -+ u32 seed[SS_SEED_LEN/4]; -+ unsigned int slen; -+}; -+ -+int sunxi_hash_crainit(struct crypto_tfm *tfm); -+int sunxi_hash_init(struct ahash_request *areq); -+int sunxi_hash_update(struct ahash_request *areq); -+int sunxi_hash_final(struct ahash_request *areq); -+int sunxi_hash_finup(struct ahash_request *areq); -+int sunxi_hash_digest(struct ahash_request *areq); -+int sunxi_hash_export(struct ahash_request *areq, void *out); -+int sunxi_hash_import(struct ahash_request *areq, const void *in); -+ -+int sunxi_ss_aes_poll(struct ablkcipher_request *areq, u32 mode); -+int sunxi_ss_des_poll(struct ablkcipher_request *areq, u32 mode); -+int sunxi_ss_cipher_init(struct crypto_tfm *tfm); -+int sunxi_ss_cipher_encrypt(struct ablkcipher_request *areq); -+int sunxi_ss_cipher_decrypt(struct ablkcipher_request *areq); -+int sunxi_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen); -+int sunxi_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen); -+int sunxi_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key, -+ unsigned int keylen); diff --git a/target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch b/target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch deleted file mode 100644 index c60b1fe013..0000000000 --- a/target/linux/sunxi/patches-3.18/300-dt-sun7i-add-bananapi.patch +++ /dev/null @@ -1,245 +0,0 @@ -From 29b4146ec174f0f598d6b454caa335e8f57e392b Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 28 Jul 2014 23:05:14 +0200 -Subject: [PATCH] ARM: dts: sun7i: Add Banana Pi board - -The Banana Pi is an A20 based development board using Raspberry Pi compatible -IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi -and stereo audio out + various expenansion headers: - -http://www.lemaker.org/ - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun7i-a20-bananapi.dts | 214 +++++++++++++++++++++++++++++++ - 2 files changed, 215 insertions(+) - create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapi.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -435,6 +435,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-hummingbird.dtb \ - sun6i-a31-m9.dtb - dtb-$(CONFIG_MACH_SUN7I) += \ -+ sun7i-a20-bananapi.dtb \ - sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-hummingbird.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts -@@ -0,0 +1,214 @@ -+/* -+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com> -+ * -+ * Hans de Goede <hdegoede@redhat.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this library; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+/include/ "sun7i-a20.dtsi" -+/include/ "sunxi-common-regulators.dtsi" -+ -+/ { -+ model = "LeMaker Banana Pi"; -+ compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; -+ -+ soc@01c00000 { -+ spi0: spi@01c05000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins_a>; -+ status = "okay"; -+ }; -+ -+ mmc0: mmc@01c0f000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 7 10 0>; /* PH10 */ -+ cd-inverted; -+ status = "okay"; -+ }; -+ -+ usbphy: phy@01c13400 { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ usb2_vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+ }; -+ -+ ehci0: usb@01c14000 { -+ status = "okay"; -+ }; -+ -+ ohci0: usb@01c14400 { -+ status = "okay"; -+ }; -+ -+ ahci: sata@01c18000 { -+ status = "okay"; -+ }; -+ -+ ehci1: usb@01c1c000 { -+ status = "okay"; -+ }; -+ -+ ohci1: usb@01c1c400 { -+ status = "okay"; -+ }; -+ -+ pinctrl@01c20800 { -+ mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { -+ allwinner,pins = "PH10"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = <0>; -+ allwinner,pull = <1>; -+ }; -+ -+ gmac_power_pin_bananapi: gmac_power_pin@0 { -+ allwinner,pins = "PH23"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ led_pins_bananapi: led_pins@0 { -+ allwinner,pins = "PH24"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ }; -+ -+ ir0: ir@01c21800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart0: serial@01c28000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart3: serial@01c28c00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins_b>; -+ status = "okay"; -+ }; -+ -+ uart7: serial@01c29c00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart7_pins_a>; -+ status = "okay"; -+ }; -+ -+ i2c0: i2c@01c2ac00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins_a>; -+ status = "okay"; -+ -+ axp209: pmic@34 { -+ compatible = "x-powers,axp209"; -+ reg = <0x34>; -+ interrupt-parent = <&nmi_intc>; -+ interrupts = <0 8>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ i2c2: i2c@01c2b400 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ status = "okay"; -+ }; -+ -+ gmac: ethernet@01c50000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_pins_rgmii_a>; -+ phy = <&phy1>; -+ phy-mode = "rgmii"; -+ phy-supply = <®_gmac_3v3>; -+ status = "okay"; -+ -+ phy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins_bananapi>; -+ -+ green { -+ label = "bananapi:green:usr"; -+ gpios = <&pio 7 24 0>; -+ }; -+ }; -+ -+ reg_usb1_vbus: usb1-vbus { -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: usb2-vbus { -+ status = "okay"; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_power_pin_bananapi>; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <50000>; -+ enable-active-high; -+ gpio = <&pio 7 23 0>; -+ }; -+}; diff --git a/target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch b/target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch deleted file mode 100644 index c8cdb1d191..0000000000 --- a/target/linux/sunxi/patches-3.18/301-dt-sun7i-add-bananapro.patch +++ /dev/null @@ -1,291 +0,0 @@ -From 3613d535a77270eaf15a5f988a48434c7d1530f2 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 7 Jan 2015 20:44:52 +0100 -Subject: [PATCH] ARM: dts: sun7i: Add dts file for Bananapro board - -Add support for the new Bananapro A20 development board from lemaker.org. -This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for -OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver, -3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi. - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun7i-a20-bananapro.dts | 261 ++++++++++++++++++++++++++++++ - 2 files changed, 262 insertions(+) - create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapro.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -436,6 +436,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-m9.dtb - dtb-$(CONFIG_MACH_SUN7I) += \ - sun7i-a20-bananapi.dtb \ -+ sun7i-a20-bananapro.dtb \ - sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-hummingbird.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts -@@ -0,0 +1,261 @@ -+/* -+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this file; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+/include/ "sun7i-a20.dtsi" -+/include/ "sunxi-common-regulators.dtsi" -+ -+/ { -+ model = "LeMaker Banana Pro"; -+ compatible = "lemaker,bananapro", "allwinner,sun7i-a20"; -+ -+ soc@01c00000 { -+ spi0: spi@01c05000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins_a>; -+ status = "okay"; -+ }; -+ -+ mmc0: mmc@01c0f000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 7 10 0>; /* PH10 */ -+ cd-inverted; -+ status = "okay"; -+ }; -+ -+ mmc3: mmc@01c12000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc3_pins_a>; -+ vmmc-supply = <®_vmmc3>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ }; -+ -+ usbphy: phy@01c13400 { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ usb2_vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+ }; -+ -+ ehci0: usb@01c14000 { -+ status = "okay"; -+ }; -+ -+ ohci0: usb@01c14400 { -+ status = "okay"; -+ }; -+ -+ ahci: sata@01c18000 { -+ status = "okay"; -+ }; -+ -+ ehci1: usb@01c1c000 { -+ status = "okay"; -+ }; -+ -+ ohci1: usb@01c1c400 { -+ status = "okay"; -+ }; -+ -+ pinctrl@01c20800 { -+ usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { -+ allwinner,pins = "PH0"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { -+ allwinner,pins = "PH1"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { -+ allwinner,pins = "PH10"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = <0>; -+ allwinner,pull = <1>; -+ }; -+ -+ vmmc3_pin_bananapro: vmmc3_pin@0 { -+ allwinner,pins = "PH22"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ gmac_power_pin_bananapi: gmac_power_pin@0 { -+ allwinner,pins = "PH23"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ led_pins_bananapi: led_pins@0 { -+ allwinner,pins = "PH24", "PG2"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ }; -+ -+ ir0: ir@01c21800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart0: serial@01c28000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart2: serial@01c28800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart7: serial@01c29c00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart7_pins_a>; -+ status = "okay"; -+ }; -+ -+ i2c0: i2c@01c2ac00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins_a>; -+ status = "okay"; -+ -+ axp209: pmic@34 { -+ compatible = "x-powers,axp209"; -+ reg = <0x34>; -+ interrupt-parent = <&nmi_intc>; -+ interrupts = <0 8>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ i2c2: i2c@01c2b400 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ status = "okay"; -+ }; -+ -+ gmac: ethernet@01c50000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_pins_rgmii_a>; -+ phy = <&phy1>; -+ phy-mode = "rgmii"; -+ phy-supply = <®_gmac_3v3>; -+ status = "okay"; -+ -+ phy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins_bananapi>; -+ -+ green { -+ label = "bananapi:green:usr"; -+ gpios = <&pio 7 24 0>; -+ }; -+ blue { -+ label = "bananapi:blue:usr"; -+ gpios = <&pio 6 2 0>; -+ }; -+ }; -+ -+ reg_usb1_vbus: usb1-vbus { -+ pinctrl-0 = <&usb1_vbus_pin_bananapro>; -+ gpio = <&pio 7 0 0>; /* PH0 */ -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: usb2-vbus { -+ pinctrl-0 = <&usb2_vbus_pin_bananapro>; -+ gpio = <&pio 7 1 0>; /* PH1 */ -+ status = "okay"; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_power_pin_bananapi>; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 7 23 0>; -+ }; -+ -+ reg_vmmc3: vmmc3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vmmc3_pin_bananapro>; -+ regulator-name = "vmmc3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&pio 7 22 0>; -+ }; -+}; diff --git a/target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch b/target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch deleted file mode 100644 index 5d5ba11e63..0000000000 --- a/target/linux/sunxi/patches-3.18/302-dt-sun7i-add-lamobo-r1.patch +++ /dev/null @@ -1,248 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -441,6 +441,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-hummingbird.dtb \ - sun7i-a20-i12-tvbox.dtb \ -+ sun7i-a20-lamobo-r1.dtb \ - sun7i-a20-olinuxino-lime.dtb \ - sun7i-a20-olinuxino-micro.dtb \ - sun7i-a20-pcduino3.dtb ---- /dev/null -+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts -@@ -0,0 +1,235 @@ -+/* -+ * Copyright 2015 Daniel Golle <daniel@makrotopia.org> -+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this library; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+/include/ "sun7i-a20.dtsi" -+/include/ "sunxi-common-regulators.dtsi" -+#include <dt-bindings/input/input.h> -+ -+/ { -+ model = "Lamobo R1"; -+ compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; -+ -+ soc@01c00000 { -+ spi0: spi@01c05000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins_a>; -+ status = "okay"; -+ }; -+ -+ mmc0: mmc@01c0f000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo>; -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 7 10 0>; /* PH10 */ -+ cd-inverted; -+ status = "okay"; -+ }; -+ -+ usbphy: phy@01c13400 { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ usb2_vbus-supply = <®_usb2_vbus>; -+ status = "okay"; -+ }; -+ -+ ehci0: usb@01c14000 { -+ status = "okay"; -+ }; -+ -+ ohci0: usb@01c14400 { -+ status = "okay"; -+ }; -+ -+ ahci: sata@01c18000 { -+ target-supply = <®_ahci_5v>; -+ status = "okay"; -+ }; -+ -+ ehci1: usb@01c1c000 { -+ status = "okay"; -+ }; -+ -+ ohci1: usb@01c1c400 { -+ status = "okay"; -+ }; -+ -+ pinctrl@01c20800 { -+ mmc0_cd_pin_lamobo: mmc0_cd_pin@0 { -+ allwinner,pins = "PH10"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = <0>; -+ allwinner,pull = <1>; -+ }; -+ -+ gmac_power_pin_lamobo: gmac_power_pin@0 { -+ allwinner,pins = "PH23"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; -+ }; -+ -+ led_pins_lamobo: led_pins@0 { -+ allwinner,pins = "PH2"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <1>; -+ allwinner,pull = <0>; -+ }; -+ }; -+ -+ lradc: lradc@01c22800 { -+ allwinner,chan0-step = <200>; -+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN -+ KEY_MENU KEY_SEARCH KEY_HOME -+ KEY_ESC KEY_ENTER>; -+ status = "okay"; -+ }; -+ -+ ir0: ir@01c21800 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart0: serial@01c28000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins_a>; -+ status = "okay"; -+ }; -+ -+ uart3: serial@01c28c00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins_b>; -+ status = "okay"; -+ }; -+ -+ uart7: serial@01c29c00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart7_pins_a>; -+ status = "okay"; -+ }; -+ -+ i2c0: i2c@01c2ac00 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins_a>; -+ status = "okay"; -+ -+ axp209: pmic@34 { -+ compatible = "x-powers,axp209"; -+ reg = <0x34>; -+ interrupt-parent = <&nmi_intc>; -+ interrupts = <0 8>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ i2c1: i2c@01c2b000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins_a>; -+ status = "okay"; -+ }; -+ -+ i2c2: i2c@01c2b400 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins_a>; -+ status = "okay"; -+ }; -+ -+ gmac: ethernet@01c50000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_pins_rgmii_a>; -+ phy = <&phy1>; -+ phy-mode = "rgmii"; -+ phy-supply = <®_gmac_3v3>; -+ status = "okay"; -+ -+ phy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_pins_lamobo>; -+ -+ green { -+ label = "lamobo:green:usr"; -+ gpios = <&pio 7 24 0>; -+ default-state = "on"; -+ }; -+ }; -+ -+ reg_ahci_5v: ahci-5v { -+ status = "okay"; -+ }; -+ -+ reg_usb1_vbus: usb1-vbus { -+ status = "okay"; -+ }; -+ -+ reg_usb2_vbus: usb2-vbus { -+ status = "okay"; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_power_pin_lamobo>; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 7 23 0>; -+ status = "okay"; -+ }; -+}; |