diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch b/target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch new file mode 100644 index 0000000000..83b69b5b9a --- /dev/null +++ b/target/linux/sunxi/patches-3.13/124-clk-sunxi-muxable-ahb-clock.patch @@ -0,0 +1,102 @@ +From 9490107c16c8eaa35b07794e19d5d2eddea8e44b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar> +Date: Sat, 14 Sep 2013 20:48:40 -0300 +Subject: [PATCH] clk: sunxi: Implement muxable AHB clock +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +sun5i and sun7i have a mux to change the AHB clock parent, this commit +adds support for it on the driver. + +Signed-off-by: Emilio López <emilio@elopez.com.ar> +--- + Documentation/devicetree/bindings/clock/sunxi.txt | 1 + + drivers/clk/sunxi/clk-sunxi.c | 37 +++++++++++++++++++++++ + 2 files changed, 38 insertions(+) + +diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt +index e840cb2..941bd93 100644 +--- a/Documentation/devicetree/bindings/clock/sunxi.txt ++++ b/Documentation/devicetree/bindings/clock/sunxi.txt +@@ -15,6 +15,7 @@ Required properties: + "allwinner,sun4i-axi-clk" - for the AXI clock + "allwinner,sun4i-axi-gates-clk" - for the AXI gates + "allwinner,sun4i-ahb-clk" - for the AHB clock ++ "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 + "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 + "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 + "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s +diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c +index ea3edeb..625089b 100644 +--- a/drivers/clk/sunxi/clk-sunxi.c ++++ b/drivers/clk/sunxi/clk-sunxi.c +@@ -249,7 +249,32 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, + *n = DIV_ROUND_UP(div, (*k+1)); + } + ++/** ++ * sun5i_get_ahb_factors() - calculates p factor for AHB ++ * AHB rate is calculated as follows ++ * rate = parent_rate >> p ++ */ + ++static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate, ++ u8 *n, u8 *k, u8 *m, u8 *p) ++{ ++ u8 div; ++ ++ /* This clock can only divide, so we will never achieve a higher ++ * rate than the parent's */ ++ if (*freq > parent_rate) ++ *freq = parent_rate; ++ ++ /* Normalize value to a parent multiple */ ++ div = *freq / parent_rate; ++ *freq = parent_rate * div; ++ ++ /* we were called to round the frequency, we can now return */ ++ if (n == NULL) ++ return; ++ ++ *p = div; ++} + + /** + * sun4i_get_apb1_factors() - calculates m, p factors for APB1 +@@ -375,6 +400,11 @@ struct factors_data { + .kwidth = 2, + }; + ++static struct clk_factors_config sun5i_a13_ahb_config = { ++ .pshift = 4, ++ .pwidth = 2, ++}; ++ + static struct clk_factors_config sun4i_apb1_config = { + .mshift = 0, + .mwidth = 5, +@@ -408,6 +438,12 @@ struct factors_data { + .getter = sun4i_get_pll5_factors, + }; + ++static const struct factors_data sun5i_a13_ahb_data __initconst = { ++ .mux = 6, ++ .table = &sun5i_a13_ahb_config, ++ .getter = sun5i_a13_get_ahb_factors, ++}; ++ + static const struct factors_data sun4i_apb1_data __initconst = { + .mux = 24, + .table = &sun4i_apb1_config, +@@ -913,6 +949,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, + static const struct of_device_id clk_factors_match[] __initconst = { + {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, + {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, ++ {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,}, + {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, + {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,}, + {} +-- +1.8.5.1 + |