diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch | 146 |
1 files changed, 0 insertions, 146 deletions
diff --git a/target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch b/target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch deleted file mode 100644 index bcfedc004c..0000000000 --- a/target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch +++ /dev/null @@ -1,146 +0,0 @@ -From d7904e075e3378bec09333b6a3247b3146b3dd91 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar> -Date: Mon, 23 Dec 2013 00:32:43 -0300 -Subject: [PATCH] ARM: sun7i: dt: mod0 clocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This commit adds all the mod0 clocks available on A20 to its device -tree. This list was created by looking at AW's code release. - -Signed-off-by: Emilio López <emilio@elopez.com.ar> -Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 120 insertions(+) - ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -170,6 +170,126 @@ - "apb1_uart2", "apb1_uart3", "apb1_uart4", - "apb1_uart5", "apb1_uart6", "apb1_uart7"; - }; -+ -+ nand_clk: clk@01c20080 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20080 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "nand"; -+ }; -+ -+ ms_clk: clk@01c20084 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20084 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "ms"; -+ }; -+ -+ mmc0_clk: clk@01c20088 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20088 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "mmc0"; -+ }; -+ -+ mmc1_clk: clk@01c2008c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c2008c 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "mmc1"; -+ }; -+ -+ mmc2_clk: clk@01c20090 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20090 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "mmc2"; -+ }; -+ -+ mmc3_clk: clk@01c20094 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20094 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "mmc3"; -+ }; -+ -+ ts_clk: clk@01c20098 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c20098 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "ts"; -+ }; -+ -+ ss_clk: clk@01c2009c { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c2009c 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "ss"; -+ }; -+ -+ spi0_clk: clk@01c200a0 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a0 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "spi0"; -+ }; -+ -+ spi1_clk: clk@01c200a4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "spi1"; -+ }; -+ -+ spi2_clk: clk@01c200a8 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200a8 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "spi2"; -+ }; -+ -+ pata_clk: clk@01c200ac { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200ac 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "pata"; -+ }; -+ -+ ir0_clk: clk@01c200b0 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200b0 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "ir0"; -+ }; -+ -+ ir1_clk: clk@01c200b4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200b4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "ir1"; -+ }; -+ -+ spi3_clk: clk@01c200d4 { -+ #clock-cells = <0>; -+ compatible = "allwinner,sun4i-mod0-clk"; -+ reg = <0x01c200d4 0x4>; -+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; -+ clock-output-names = "spi3"; -+ }; - }; - - soc@01c00000 { |