diff options
Diffstat (limited to 'target/linux/mvebu')
| -rw-r--r-- | target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch | 92 |
1 files changed, 0 insertions, 92 deletions
diff --git a/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch b/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch deleted file mode 100644 index a841f5eadd..0000000000 --- a/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <maxime.ripard@free-electrons.com> -Date: Fri, 23 Jan 2015 15:18:27 +0100 -Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining - -The NDDB register holds the data that are needed by the read and write -commands. - -However, during a read PIO access, the datasheet specifies that after each 32 -bits read in that register, when BCH is enabled, we have to make sure that the -RDDREQ bit is set in the NDSR register. - -This fixes an issue that was seen on the Armada 385, and presumably other mvebu -SoCs, when a read on a newly erased page would end up in the driver reporting a -timeout from the NAND. - -Cc: <stable@vger.kernel.org> # v3.14 -Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> ---- - drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------ - 1 file changed, 39 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -23,6 +23,7 @@ - #include <linux/mtd/partitions.h> - #include <linux/io.h> - #include <linux/irq.h> -+#include <linux/jiffies.h> - #include <linux/slab.h> - #include <linux/of.h> - #include <linux/of_device.h> -@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_na - nand_writel(info, NDCR, ndcr | int_mask); - } - -+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) -+{ -+ u32 *dst = (u32 *)data; -+ -+ if (info->ecc_bch) { -+ while (len--) { -+ u32 timeout; -+ -+ *dst++ = nand_readl(info, NDDB); -+ -+ /* -+ * According to the datasheet, when reading -+ * from NDDB with BCH enabled, after each 32 -+ * bits reads, we have to make sure that the -+ * NDSR.RDDREQ bit is set -+ */ -+ timeout = jiffies + msecs_to_jiffies(5); -+ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { -+ if (!time_before(jiffies, timeout)) { -+ dev_err(&info->pdev->dev, -+ "Timeout on RDDREQ while draining the FIFO\n"); -+ return; -+ } -+ -+ cpu_relax(); -+ } -+ } -+ } else { -+ __raw_readsl(info->mmio_base + NDDB, data, len); -+ } -+} -+ - static void handle_data_pio(struct pxa3xx_nand_info *info) - { - unsigned int do_bytes = min(info->data_size, info->chunk_size); -@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3x - DIV_ROUND_UP(info->oob_size, 4)); - break; - case STATE_PIO_READING: -- __raw_readsl(info->mmio_base + NDDB, -- info->data_buff + info->data_buff_pos, -- DIV_ROUND_UP(do_bytes, 4)); -+ drain_fifo(info, -+ info->data_buff + info->data_buff_pos, -+ DIV_ROUND_UP(do_bytes, 4)); - - if (info->oob_size > 0) -- __raw_readsl(info->mmio_base + NDDB, -- info->oob_buff + info->oob_buff_pos, -- DIV_ROUND_UP(info->oob_size, 4)); -+ drain_fifo(info, -+ info->oob_buff + info->oob_buff_pos, -+ DIV_ROUND_UP(info->oob_size, 4)); - break; - default: - dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |