diff options
Diffstat (limited to 'target/linux/mediatek/patches/0071-clk.patch')
| -rw-r--r-- | target/linux/mediatek/patches/0071-clk.patch | 35 |
1 files changed, 15 insertions, 20 deletions
diff --git a/target/linux/mediatek/patches/0071-clk.patch b/target/linux/mediatek/patches/0071-clk.patch index f920dcee43..9bbd78d360 100644 --- a/target/linux/mediatek/patches/0071-clk.patch +++ b/target/linux/mediatek/patches/0071-clk.patch @@ -7,8 +7,6 @@ Subject: [PATCH 71/76] clk drivers/clk/mediatek/clk-mt7623.c | 194 ++++++++++++++++--------------------- 1 file changed, 83 insertions(+), 111 deletions(-) -diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c -index 07843bb..d46b2ad 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -20,6 +20,7 @@ @@ -19,7 +17,7 @@ index 07843bb..d46b2ad 100644 static DEFINE_SPINLOCK(mt7623_clk_lock); -@@ -37,18 +38,11 @@ static void mtk_clk_enable_critical(void) +@@ -37,18 +38,11 @@ static void mtk_clk_enable_critical(void clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]); } @@ -42,7 +40,7 @@ index 07843bb..d46b2ad 100644 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), -@@ -61,13 +55,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { +@@ -61,13 +55,6 @@ static const struct mtk_fixed_factor top FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16), FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24), @@ -56,7 +54,7 @@ index 07843bb..d46b2ad 100644 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2), -@@ -85,9 +72,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { +@@ -85,9 +72,6 @@ static const struct mtk_fixed_factor top FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1), FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1), @@ -66,7 +64,7 @@ index 07843bb..d46b2ad 100644 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), -@@ -110,9 +94,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { +@@ -110,9 +94,6 @@ static const struct mtk_fixed_factor top FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), @@ -76,7 +74,7 @@ index 07843bb..d46b2ad 100644 }; static const char * const axi_parents[] __initconst = { -@@ -155,18 +136,6 @@ static const char * const pwm_parents[] __initconst = { +@@ -155,18 +136,6 @@ static const char * const pwm_parents[] "univpll1_d4", }; @@ -95,7 +93,7 @@ index 07843bb..d46b2ad 100644 static const char * const mfg_parents[] __initconst = { "clk26m", "mmpll_ck", -@@ -178,17 +147,6 @@ static const char * const mfg_parents[] __initconst = { +@@ -178,17 +147,6 @@ static const char * const mfg_parents[] "univpll1_d2", }; @@ -113,7 +111,7 @@ index 07843bb..d46b2ad 100644 static const char * const uart_parents[] __initconst = { "clk26m", "univpll2_d8", -@@ -277,35 +235,6 @@ static const char * const scp_parents[] __initconst = { +@@ -277,35 +235,6 @@ static const char * const scp_parents[] "dmpll_d4", }; @@ -149,7 +147,7 @@ index 07843bb..d46b2ad 100644 static const char * const apll_parents[] __initconst = { "clk26m", "audpll", -@@ -317,17 +246,6 @@ static const char * const apll_parents[] __initconst = { +@@ -317,17 +246,6 @@ static const char * const apll_parents[] "clk26m", }; @@ -167,7 +165,7 @@ index 07843bb..d46b2ad 100644 static const char * const rtc_parents[] __initconst = { "clk32k", "external_32k", -@@ -367,9 +285,7 @@ static const struct mtk_composite top_muxes[] __initconst = { +@@ -367,9 +285,7 @@ static const struct mtk_composite top_mu 0x0140, 24, 3, INVALID_MUX_GATE_BIT), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), @@ -177,7 +175,7 @@ index 07843bb..d46b2ad 100644 /* CLK_CFG_2 */ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7), MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15), -@@ -384,12 +300,8 @@ static const struct mtk_composite top_muxes[] __initconst = { +@@ -384,12 +300,8 @@ static const struct mtk_composite top_mu /* CLK_CFG_4 */ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7), MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15), @@ -190,7 +188,7 @@ index 07843bb..d46b2ad 100644 /* CLK_CFG_6 */ MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7), MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15), -@@ -428,6 +340,17 @@ static const struct mtk_gate infra_clks[] __initconst = { +@@ -428,6 +340,17 @@ static const struct mtk_gate infra_clks[ GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), }; @@ -208,7 +206,7 @@ index 07843bb..d46b2ad 100644 static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x0008, .clr_ofs = 0x0010, -@@ -499,6 +422,29 @@ static const struct mtk_gate peri_gates[] __initconst = { +@@ -499,6 +422,29 @@ static const struct mtk_gate peri_gates[ GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2), }; @@ -238,7 +236,7 @@ index 07843bb..d46b2ad 100644 static const char * const uart_ck_sel_parents[] __initconst = { "clk26m", "uart_sel", -@@ -525,10 +471,9 @@ static void __init mtk_topckgen_init(struct device_node *node) +@@ -525,10 +471,9 @@ static void __init mtk_topckgen_init(str mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); @@ -250,7 +248,7 @@ index 07843bb..d46b2ad 100644 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) -@@ -547,7 +492,10 @@ static void __init mtk_infrasys_init(struct device_node *node) +@@ -547,7 +492,10 @@ static void __init mtk_infrasys_init(str clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), @@ -262,7 +260,7 @@ index 07843bb..d46b2ad 100644 clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); -@@ -588,35 +536,59 @@ static void __init mtk_pericfg_init(struct device_node *node) +@@ -588,35 +536,59 @@ static void __init mtk_pericfg_init(stru } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init); @@ -337,6 +335,3 @@ index 07843bb..d46b2ad 100644 }; static void __init mtk_apmixedsys_init(struct device_node *node) --- -1.7.10.4 - |