diff options
Diffstat (limited to 'target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch')
| -rw-r--r-- | target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch | 217 |
1 files changed, 217 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch b/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch new file mode 100644 index 0000000000..7cdb4168bd --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch @@ -0,0 +1,217 @@ +From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001 +From: Sean Wang <sean.wang@mediatek.com> +Date: Thu, 5 Oct 2017 11:50:22 +0800 +Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings + for MediaTek MT7622 SoC + +This patch adds the binding documentation for apmixedsys, ethsys, hifsys, +infracfg, pericfg, topckgen and audsys for MT7622. + +Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> +Signed-off-by: Sean Wang <sean.wang@mediatek.com> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +--- + .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,audsys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,hifsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,pciesys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + + 10 files changed, 94 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt + +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +index 19fc116346d6..b404d592ce58 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +@@ -9,6 +9,7 @@ Required Properties: + - "mediatek,mt2701-apmixedsys" + - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6797-apmixedsys" ++ - "mediatek,mt7622-apmixedsys" + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8173-apmixedsys" + - #clock-cells: Must be 1 +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +new file mode 100644 +index 000000000000..9b8f578d5e19 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +@@ -0,0 +1,22 @@ ++MediaTek AUDSYS controller ++============================ ++ ++The MediaTek AUDSYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be one of: ++ - "mediatek,mt7622-audsys", "syscon" ++- #clock-cells: Must be 1 ++ ++The AUDSYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++audsys: audsys@11220000 { ++ compatible = "mediatek,mt7622-audsys", "syscon"; ++ reg = <0 0x11220000 0 0x1000>; ++ #clock-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +index 768f3a5bc055..7aa3fa167668 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be: + - "mediatek,mt2701-ethsys", "syscon" ++ - "mediatek,mt7622-ethsys", "syscon" + - #clock-cells: Must be 1 + + The ethsys controller uses the common clk binding from +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +index beed7b594cea..f5629d64cef2 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +@@ -8,6 +8,7 @@ Required Properties: + + - compatible: Should be: + - "mediatek,mt2701-hifsys", "syscon" ++ - "mediatek,mt7622-hifsys", "syscon" + - #clock-cells: Must be 1 + + The hifsys controller uses the common clk binding from +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +index a3430cd96d0f..566f153f9f83 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +@@ -10,6 +10,7 @@ Required Properties: + - "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6797-infracfg", "syscon" ++ - "mediatek,mt7622-infracfg", "syscon" + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" + - #clock-cells: Must be 1 +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +new file mode 100644 +index 000000000000..d5d5f1227665 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +@@ -0,0 +1,22 @@ ++MediaTek PCIESYS controller ++============================ ++ ++The MediaTek PCIESYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-pciesys", "syscon" ++- #clock-cells: Must be 1 ++ ++The PCIESYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++pciesys: pciesys@1a100800 { ++ compatible = "mediatek,mt7622-pciesys", "syscon"; ++ reg = <0 0x1a100800 0 0x1000>; ++ #clock-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +index d9f092eb3550..fb58ca8c2770 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +@@ -9,6 +9,7 @@ Required Properties: + - compatible: Should be one of: + - "mediatek,mt2701-pericfg", "syscon" + - "mediatek,mt2712-pericfg", "syscon" ++ - "mediatek,mt7622-pericfg", "syscon" + - "mediatek,mt8135-pericfg", "syscon" + - "mediatek,mt8173-pericfg", "syscon" + - #clock-cells: Must be 1 +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +new file mode 100644 +index 000000000000..d113b8e741f3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +@@ -0,0 +1,22 @@ ++MediaTek SGMIISYS controller ++============================ ++ ++The MediaTek SGMIISYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-sgmiisys", "syscon" ++- #clock-cells: Must be 1 ++ ++The SGMIISYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++sgmiisys: sgmiisys@1b128000 { ++ compatible = "mediatek,mt7622-sgmiisys", "syscon"; ++ reg = <0 0x1b128000 0 0x1000>; ++ #clock-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +new file mode 100644 +index 000000000000..00760019da00 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +@@ -0,0 +1,22 @@ ++MediaTek SSUSBSYS controller ++============================ ++ ++The MediaTek SSUSBSYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-ssusbsys", "syscon" ++- #clock-cells: Must be 1 ++ ++The SSUSBSYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++ssusbsys: ssusbsys@1a000000 { ++ compatible = "mediatek,mt7622-ssusbsys", "syscon"; ++ reg = <0 0x1a000000 0 0x1000>; ++ #clock-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +index 2024fc909d69..24014a7e2332 100644 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +@@ -9,6 +9,7 @@ Required Properties: + - "mediatek,mt2701-topckgen" + - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6797-topckgen" ++ - "mediatek,mt7622-topckgen" + - "mediatek,mt8135-topckgen" + - "mediatek,mt8173-topckgen" + - #clock-cells: Must be 1 +-- +2.11.0 + |