diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch | 38 |
1 files changed, 27 insertions, 11 deletions
diff --git a/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch b/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch index 2f7d6f8478..0d05dc78ab 100644 --- a/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch +++ b/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch @@ -1,17 +1,17 @@ -From bd3df6d053a28d5aa630524c9087c21def30e764 Mon Sep 17 00:00:00 2001 +From 82a391a067491f4c46b75d0dfe2bf9e5a11aca8e Mon Sep 17 00:00:00 2001 From: Yangbo Lu <yangbo.lu@nxp.com> -Date: Mon, 25 Sep 2017 12:09:35 +0800 -Subject: [PATCH] clk: support layerscape +Date: Wed, 17 Jan 2018 15:15:44 +0800 +Subject: [PATCH 14/30] clk: support layerscape -This is a integrated patch for layerscape clock support. +This is an integrated patch for layerscape clock support. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- - drivers/clk/clk-qoriq.c | 170 ++++++++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 156 insertions(+), 14 deletions(-) + drivers/clk/clk-qoriq.c | 179 ++++++++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 164 insertions(+), 15 deletions(-) --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -23,6 +23,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> #include <linux/fsl/guts.h> #include <linux/io.h> #include <linux/kernel.h> +@@ -40,7 +41,7 @@ struct clockgen_pll_div { + }; + + struct clockgen_pll { +- struct clockgen_pll_div div[4]; ++ struct clockgen_pll_div div[8]; + }; + + #define CLKSEL_VALID 1 @@ -87,7 +88,7 @@ struct clockgen { struct device_node *node; void __iomem *regs; @@ -244,11 +253,18 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> if (cg->info.flags & CG_VER3) { switch (idx) { case PLATFORM_PLL: -@@ -1000,12 +1125,13 @@ static void __init create_one_pll(struct +@@ -1000,12 +1125,20 @@ static void __init create_one_pll(struct for (i = 0; i < ARRAY_SIZE(pll->div); i++) { struct clk *clk; + int ret; ++ ++ /* ++ * For platform PLL, there are 8 divider clocks. ++ * For core PLL, there are 4 divider clocks at most. ++ */ ++ if (idx != 0 && i >= 4) ++ break; snprintf(pll->div[i].name, sizeof(pll->div[i].name), "cg-pll%d-div%d", idx, i + 1); @@ -259,7 +275,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> if (IS_ERR(clk)) { pr_err("%s: %s: register failed %ld\n", __func__, pll->div[i].name, PTR_ERR(clk)); -@@ -1013,6 +1139,11 @@ static void __init create_one_pll(struct +@@ -1013,6 +1146,11 @@ static void __init create_one_pll(struct } pll->div[i].clk = clk; @@ -271,7 +287,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> } } -@@ -1142,6 +1273,13 @@ static struct clk *clockgen_clk_get(stru +@@ -1142,6 +1280,13 @@ static struct clk *clockgen_clk_get(stru goto bad_args; clk = pll->div[idx].clk; break; @@ -285,7 +301,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> default: goto bad_args; } -@@ -1253,6 +1391,7 @@ static void __init clockgen_init(struct +@@ -1253,6 +1398,7 @@ static void __init clockgen_init(struct clockgen.info.flags |= CG_CMUX_GE_PLAT; clockgen.sysclk = create_sysclk("cg-sysclk"); @@ -293,7 +309,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> create_plls(&clockgen); create_muxes(&clockgen); -@@ -1273,8 +1412,11 @@ err: +@@ -1273,8 +1419,11 @@ err: CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); |