diff options
Diffstat (limited to 'target/linux/lantiq/patches-3.7/0005-MIPS-lantiq-adds-code-for-booting-GPHY.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.7/0005-MIPS-lantiq-adds-code-for-booting-GPHY.patch | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/target/linux/lantiq/patches-3.7/0005-MIPS-lantiq-adds-code-for-booting-GPHY.patch b/target/linux/lantiq/patches-3.7/0005-MIPS-lantiq-adds-code-for-booting-GPHY.patch deleted file mode 100644 index deb5016aa6..0000000000 --- a/target/linux/lantiq/patches-3.7/0005-MIPS-lantiq-adds-code-for-booting-GPHY.patch +++ /dev/null @@ -1,82 +0,0 @@ -From af14a456c58c153c6d761e6c0af48157692b52ad Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 9 Nov 2012 13:43:30 +0100 -Subject: [PATCH 5/6] MIPS: lantiq: adds code for booting GPHY - -The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to -boot them up. - -Signed-off-by: John Crispin <blogic@openwrt.org> -Patchwork: http://patchwork.linux-mips.org/patch/4522 ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 ++ - arch/mips/lantiq/xway/reset.c | 36 ++++++++++++++++++++ - 2 files changed, 39 insertions(+) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase; - #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) - #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) - -+/* allow booting xrx200 phys */ -+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr); -+ - /* request a non-gpio and set the PIO config */ - #define PMU_PPE BIT(13) - extern void ltq_pmu_enable(unsigned int module); ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -28,9 +28,15 @@ - #define RCU_RST_REQ 0x0010 - /* reset status register */ - #define RCU_RST_STAT 0x0014 -+/* vr9 gphy registers */ -+#define RCU_GFS_ADD0_XRX200 0x0020 -+#define RCU_GFS_ADD1_XRX200 0x0068 - - /* reboot bit */ -+#define RCU_RD_GPHY0_XRX200 BIT(31) - #define RCU_RD_SRST BIT(30) -+#define RCU_RD_GPHY1_XRX200 BIT(29) -+ - /* reset cause */ - #define RCU_STAT_SHIFT 26 - /* boot selection */ -@@ -60,6 +66,36 @@ unsigned char ltq_boot_select(void) - return RCU_BOOT_SEL(val); - } - -+/* reset / boot a gphy */ -+static struct ltq_xrx200_gphy_reset { -+ u32 rd; -+ u32 addr; -+} xrx200_gphy[] = { -+ {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200}, -+ {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200}, -+}; -+ -+/* reset and boot a gphy. these phys only exist on xrx200 SoC */ -+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) -+{ -+ if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) { -+ dev_err(dev, "this SoC has no GPHY\n"); -+ return -EINVAL; -+ } -+ if (id > 1) { -+ dev_err(dev, "%u is an invalid gphy id\n", id); -+ return -EINVAL; -+ } -+ dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr); -+ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | xrx200_gphy[id].rd, -+ RCU_RST_REQ); -+ ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~xrx200_gphy[id].rd, -+ RCU_RST_REQ); -+ return 0; -+} -+ - /* reset a io domain for u micro seconds */ - void ltq_reset_once(unsigned int module, ulong u) - { |