diff options
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0072-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch')
-rw-r--r-- | target/linux/ipq807x/patches-5.15/0072-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0072-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch b/target/linux/ipq807x/patches-5.15/0072-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch new file mode 100644 index 0000000000..fddc82ed35 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0072-v6.0-phy-qcom-qmp-pcie-make-pipe-clock-rate-configurable.patch @@ -0,0 +1,47 @@ +From 2b0fe9137aa32d7fc367bf3a1cef4fa97ece6d58 Mon Sep 17 00:00:00 2001 +From: Robert Marko <robimarko@gmail.com> +Date: Tue, 23 Aug 2022 22:43:51 +0200 +Subject: [PATCH] phy: qcom-qmp-pcie: make pipe clock rate configurable + +IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz +like every other PCIe QMP PHY does, so make it configurable as part of the +qmp_phy_cfg. + +Signed-off-by: Robert Marko <robimarko@gmail.com> +Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> +Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com +Signed-off-by: Vinod Koul <vkoul@kernel.org> +--- + drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/phy/qualcomm/phy-qcom-qmp.c ++++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg { + /* true, if PHY has secondary tx/rx lanes to be configured */ + bool is_dual_lane_phy; + ++ /* QMP PHY pipe clock interface rate */ ++ unsigned long pipe_clock_rate; ++ + /* true, if PCS block has no separate SW_RESET register */ + bool no_pcs_sw_reset; + }; +@@ -5138,8 +5141,15 @@ static int phy_pipe_clk_register(struct + + init.ops = &clk_fixed_rate_ops; + +- /* controllers using QMP phys use 125MHz pipe clock interface */ +- fixed->fixed_rate = 125000000; ++ /* ++ * Controllers using QMP PHY-s use 125MHz pipe clock interface ++ * unless other frequency is specified in the PHY config. ++ */ ++ if (qmp->phys[0]->cfg->pipe_clock_rate) ++ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; ++ else ++ fixed->fixed_rate = 125000000; ++ + fixed->hw.init = &init; + + ret = devm_clk_hw_register(qmp->dev, &fixed->hw); |