diff options
Diffstat (limited to 'target/linux/ipq40xx/patches-4.14')
15 files changed, 496 insertions, 282 deletions
diff --git a/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch b/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch index b7e375dfb2..1e1a83220e 100644 --- a/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch +++ b/target/linux/ipq40xx/patches-4.14/070-qcom-spm-fix-probe-order.patch @@ -1,10 +1,22 @@ -Check for SCM availability before attempting to use SPM +From 341844c7e06afccd64261719fa388339a589b0a4 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau <nbd@nbd.name> +Date: Sun, 22 Jul 2018 12:53:04 +0200 +Subject: [PATCH] soc: qcom: spm: add SCM probe dependency + +Check for SCM availability before attempting to use SPM. SPM probe will +fail otherwise. Signed-off-by: Felix Fietkau <nbd@nbd.name> +Signed-off-by: John Crispin <john@phrozen.org> +--- + drivers/soc/qcom/spm.c | 3 +++ + 1 file changed, 3 insertions(+) +diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c +index f9d7a85b2822..53807e839664 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c -@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(stru +@@ -219,6 +219,9 @@ static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu) cpumask_t mask; bool use_scm_power_down = false; @@ -14,3 +26,6 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name> for (i = 0; ; i++) { state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); if (!state_node) +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq40xx/patches-4.14/071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch index ed44359e5f..f79e99f66f 100644 --- a/target/linux/ipq40xx/patches-4.14/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch +++ b/target/linux/ipq40xx/patches-4.14/071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch @@ -1,23 +1,23 @@ -From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001 +From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001 From: Matthew McClintock <mmcclint@codeaurora.org> -Date: Fri, 8 Apr 2016 15:26:10 -0500 -Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism +Date: Mon, 23 Jul 2018 08:41:02 +0200 +Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism v1 was the incorrect choice here and sometimes the board would not come up properly. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> --- -Changes: - - moved L2-Cache to be a subnode of cpu0 ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++-------- - 1 file changed, 24 insertions(+), 8 deletions(-) + arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++-------- + 1 file changed, 17 insertions(+), 8 deletions(-) +diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi +index 93647db5d90b..06434fd02d40 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -36,19 +36,27 @@ +@@ -52,7 +52,8 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -27,17 +27,7 @@ Changes: qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; - clocks = <&gcc GCC_APPS_CLK_SRC>; - clock-frequency = <0>; - operating-points-v2 = <&cpu0_opp_table>; -+ -+ L2: l2-cache { -+ compatible = "qcom,arch-cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ }; - }; - +@@ -71,7 +72,8 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -47,7 +37,7 @@ Changes: qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; -@@ -60,7 +68,8 @@ +@@ -82,7 +84,8 @@ cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -57,7 +47,7 @@ Changes: qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; -@@ -72,7 +81,8 @@ +@@ -93,13 +96,19 @@ cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -67,43 +57,44 @@ Changes: qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; -@@ -265,22 +275,22 @@ + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + }; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; ++ }; + }; + + pmu { +@@ -268,22 +277,22 @@ }; acc0: clock-controller@b088000 { - compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; ++ compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; acc1: clock-controller@b098000 { - compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; ++ compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; acc2: clock-controller@b0a8000 { - compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; ++ compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; acc3: clock-controller@b0b8000 { - compatible = "qcom,kpss-acc-v1"; -+ compatible = "qcom,kpss-acc-v2"; ++ compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; -@@ -308,6 +318,12 @@ - regulator; - }; - -+ saw_l2: regulator@b012000 { -+ compatible = "qcom,saw2"; -+ reg = <0xb012000 0x1000>; -+ regulator; -+ }; -+ - serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch b/target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch index 03e9021a42..5596e30852 100644 --- a/target/linux/ipq40xx/patches-4.14/017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch +++ b/target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch @@ -1,19 +1,22 @@ -From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001 +From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001 From: Matthew McClintock <mmcclint@codeaurora.org> -Date: Thu, 17 Mar 2016 15:01:09 -0500 -Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq +Date: Mon, 23 Jul 2018 09:10:35 +0200 +Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq support This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> +Signed-off-by: John Crispin <john@phrozen.org> --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -40,14 +40,7 @@ +Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi +=================================================================== +--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -41,14 +41,7 @@ reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; @@ -29,7 +32,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> }; cpu@1 { -@@ -59,6 +52,7 @@ +@@ -61,6 +54,7 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; @@ -37,7 +40,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> }; cpu@2 { -@@ -70,6 +64,7 @@ +@@ -73,6 +67,7 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; @@ -45,7 +48,7 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> }; cpu@3 { -@@ -81,6 +76,29 @@ +@@ -85,6 +80,29 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; @@ -73,5 +76,5 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> + opp-hz = /bits/ 64 <716000000>; + clock-latency-ns = <256000>; }; - }; + L2: l2-cache { diff --git a/target/linux/ipq40xx/patches-4.14/073-qcom-ipq4019-fix-cpu0-s-qcom-saw2-reg-value.patch b/target/linux/ipq40xx/patches-4.14/073-qcom-ipq4019-fix-cpu0-s-qcom-saw2-reg-value.patch new file mode 100644 index 0000000000..e92ead5ee2 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/073-qcom-ipq4019-fix-cpu0-s-qcom-saw2-reg-value.patch @@ -0,0 +1,38 @@ +From d60e006ec0e425877aacc61c7ece3da0434a8fce Mon Sep 17 00:00:00 2001 +From: Christian Lamparter <chunkeey@gmail.com> +Date: Mon, 23 Jul 2018 16:34:54 +0200 +Subject: [PATCH 7/8] qcom: ipq4019: fix cpu0's qcom,saw2 reg value + +while compiling an ipq4019 target, dtc will complain: +regulator@b089000 unit address format error, expected "2089000" + +The saw0 regulator reg value seems to be +copied and pasted from qcom-ipq8064.dtsi. + +This patch fixes the reg value to match that of the +unit address which in turn silences the warning. +(There is no driver for qcom,saw2 right now. +So this went unnoticed) + +Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> +--- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi +index 98b9850ed2a0..3289b3a6c10e 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -316,7 +316,7 @@ + + saw0: regulator@b089000 { + compatible = "qcom,saw2"; +- reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; ++ reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq40xx/patches-4.14/074-ARM-qcom-Add-IPQ4019-SoC-support.patch index 1dc1c97c72..cdecd14293 100644 --- a/target/linux/ipq40xx/patches-4.14/307-ARM-qcom-Add-IPQ4019-SoC-support.patch +++ b/target/linux/ipq40xx/patches-4.14/074-ARM-qcom-Add-IPQ4019-SoC-support.patch @@ -1,28 +1,33 @@ -From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001 +From 89b43d59ec8c9cda588555eb1f2754dd19ef5144 Mon Sep 17 00:00:00 2001 From: Christian Lamparter <chunkeey@gmail.com> -Date: Sat, 19 Nov 2016 00:58:18 +0100 -Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support +Date: Sun, 22 Jul 2018 12:07:57 +0200 +Subject: [PATCH 8/8] ARM: qcom: Add IPQ4019 SoC support Add support for the Qualcomm Atheros IPQ4019 SoC. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> --- arch/arm/Makefile | 1 + arch/arm/mach-qcom/Kconfig | 5 +++++ 2 files changed, 6 insertions(+) ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000 - endif +Index: linux-4.14.54/arch/arm/Makefile +=================================================================== +--- linux-4.14.54.orig/arch/arm/Makefile ++++ linux-4.14.54/arch/arm/Makefile +@@ -150,6 +150,7 @@ endif textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 -+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 ++textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 # Machine directory name. This list is sorted alphanumerically ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig + # by CONFIG_* macro name. +Index: linux-4.14.54/arch/arm/mach-qcom/Kconfig +=================================================================== +--- linux-4.14.54.orig/arch/arm/mach-qcom/Kconfig ++++ linux-4.14.54/arch/arm/mach-qcom/Kconfig @@ -27,4 +27,9 @@ config ARCH_MDM9615 bool "Enable support for MDM9615" select CLKSRC_QCOM diff --git a/target/linux/ipq40xx/patches-4.14/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch b/target/linux/ipq40xx/patches-4.14/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch new file mode 100644 index 0000000000..6710caf657 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/075-dt-bindings-phy-qcom-ipq4019-usb-add-binding-documen.patch @@ -0,0 +1,44 @@ +From 5f01733dc755dfadfa51b7b3c6c160e632fc6002 Mon Sep 17 00:00:00 2001 +From: John Crispin <john@phrozen.org> +Date: Tue, 24 Jul 2018 15:09:36 +0200 +Subject: [PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document + +This patch adds the binding documentation for the HS/SS USB PHY found +inside Qualcom Dakota SoCs. + +Signed-off-by: John Crispin <john@phrozen.org> +--- + .../bindings/phy/phy-qcom-ipq4019-usb.txt | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt + +diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt +new file mode 100644 +index 000000000000..362877fcafed +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt +@@ -0,0 +1,21 @@ ++Qualcom Dakota HS/SS USB PHY ++ ++Required properties: ++ - compatible: "qcom,usb-ss-ipq4019-phy", ++ "qcom,usb-hs-ipq4019-phy" ++ - reg: offset and length of the registers ++ - #phy-cells: should be 0 ++ - resets: the reset controllers as listed below ++ - reset-names: the names of the reset controllers ++ "por_rst" - the POR reset line for SS and HS phys ++ "srif_rst" - the SRIF reset line for HS phys ++Example: ++ ++hsphy@a8000 { ++ compatible = "qcom,usb-hs-ipq4019-phy"; ++ phy-cells = <0>; ++ reg = <0xa8000 0x40>; ++ resets = <&gcc USB2_HSPHY_POR_ARES>, ++ <&gcc USB2_HSPHY_S_ARES>; ++ reset-names = "por_rst", "srif_rst"; ++}; +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq40xx/patches-4.14/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch index ee2beaa64d..4cab66b677 100644 --- a/target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch +++ b/target/linux/ipq40xx/patches-4.14/076-phy-qcom-ipq4019-usb-add-driver-for-QCOM-IPQ4019.patch @@ -1,138 +1,24 @@ -From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001 -From: Matthew McClintock <mmcclint@codeaurora.org> -Date: Thu, 17 Mar 2016 16:22:28 -0500 -Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree +From 633f0e08498aebfdb932bd71319b4cb136709499 Mon Sep 17 00:00:00 2001 +From: John Crispin <john@phrozen.org> +Date: Tue, 24 Jul 2018 14:45:49 +0200 +Subject: [PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019 -This adds the SoC nodes to the ipq4019 device tree and -enable it for the DK01.1 board. +Add a driver to setup the USB phy on Qualcom Dakota SoCs. +The driver sets up HS and SS phys. In case of HS some magic values need to +be written to magic offsets. These were taken from the SDK driver. -Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> -Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> --- -Changes: - - replaced space with tab - - added sleep and mock_utmi clocks - - added registers for usb2 and usb3 parent node - - changed compatible to qca,ipa4019-dwc3 - - updated usb2 and usb3 names - (included the reg - in case they become necessary later) ---- - arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++ - arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++ - 2 files changed, 91 insertions(+) + drivers/phy/qualcomm/Kconfig | 7 ++ + drivers/phy/qualcomm/Makefile | 1 + + drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 188 ++++++++++++++++++++++++++++ + 3 files changed, 196 insertions(+) + create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -101,5 +101,25 @@ - wifi@a800000 { - status = "ok"; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ status = "ok"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ status = "ok"; -+ }; -+ -+ usb3: usb3@8af8800 { -+ status = "ok"; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ status = "ok"; -+ }; -+ -+ usb2: usb2@60f8800 { -+ status = "ok"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -539,5 +539,79 @@ - "legacy"; - status = "disabled"; - }; -+ -+ usb3_ss_phy: ssphy@9a000 { -+ compatible = "qcom,usb-ss-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0x9a000 0x800>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_UNIPHY_PHY_ARES>; -+ reset-names = "por_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3_hs_phy: hsphy@a6000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa6000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb3@8af8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x8af8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB3_MASTER_CLK>, -+ <&gcc GCC_USB3_SLEEP_CLK>, -+ <&gcc GCC_USB3_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x8a00000 0xf8000>; -+ interrupts = <0 132 0>; -+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ dr_mode = "host"; -+ }; -+ }; -+ -+ usb2_hs_phy: hsphy@a8000 { -+ compatible = "qcom,usb-hs-ipq4019-phy"; -+ #phy-cells = <0>; -+ reg = <0xa8000 0x40>; -+ reg-names = "phy_base"; -+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; -+ reset-names = "por_rst", "srif_rst"; -+ status = "disabled"; -+ }; -+ -+ usb2@60f8800 { -+ compatible = "qcom,dwc3"; -+ reg = <0x60f8800 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&gcc GCC_USB2_MASTER_CLK>, -+ <&gcc GCC_USB2_SLEEP_CLK>, -+ <&gcc GCC_USB2_MOCK_UTMI_CLK>; -+ clock-names = "master", "sleep", "mock_utmi"; -+ ranges; -+ status = "disabled"; -+ -+ dwc3@6000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x6000000 0xf8000>; -+ interrupts = <0 136 0>; -+ phys = <&usb2_hs_phy>; -+ phy-names = "usb2-phy"; -+ dr_mode = "host"; -+ }; -+ }; - }; - }; ---- a/drivers/phy/qualcomm/Kconfig -+++ b/drivers/phy/qualcomm/Kconfig +Index: linux-4.14.54/drivers/phy/qualcomm/Kconfig +=================================================================== +--- linux-4.14.54.orig/drivers/phy/qualcomm/Kconfig ++++ linux-4.14.54/drivers/phy/qualcomm/Kconfig @@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA depends on OF select GENERIC_PHY @@ -147,17 +33,10 @@ Changes: config PHY_QCOM_IPQ806X_SATA tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" depends on ARCH_QCOM ---- a/drivers/phy/qualcomm/Makefile -+++ b/drivers/phy/qualcomm/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o -+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o - obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o - obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o - obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +Index: linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c +=================================================================== --- /dev/null -+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c ++++ linux-4.14.54/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2018 John Crispin <john@phrozen.org> @@ -347,3 +226,14 @@ Changes: +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver"); +MODULE_AUTHOR("John Crispin <john@phrozen.org>"); +MODULE_LICENSE("GPL v2"); +Index: linux-4.14.54/drivers/phy/qualcomm/Makefile +=================================================================== +--- linux-4.14.54.orig/drivers/phy/qualcomm/Makefile ++++ linux-4.14.54/drivers/phy/qualcomm/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o ++obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o + obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o + obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o + obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o diff --git a/target/linux/ipq40xx/patches-4.14/077-qcom-ipq4019-add-USB-devicetree-nodes.patch b/target/linux/ipq40xx/patches-4.14/077-qcom-ipq4019-add-USB-devicetree-nodes.patch new file mode 100644 index 0000000000..7cc7d9d5f4 --- /dev/null +++ b/target/linux/ipq40xx/patches-4.14/077-qcom-ipq4019-add-USB-devicetree-nodes.patch @@ -0,0 +1,130 @@ +From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001 +From: John Crispin <john@phrozen.org> +Date: Tue, 24 Jul 2018 14:47:55 +0200 +Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes + +This patch makes USB work on the Dakota EVB. + +Signed-off-by: John Crispin <john@phrozen.org> +--- + arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++ + arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++ + 2 files changed, 94 insertions(+) + +diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +index 418f9a022336..2ee5f05d5a43 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +@@ -109,5 +109,25 @@ + wifi@a800000 { + status = "ok"; + }; ++ ++ usb3_ss_phy: ssphy@9a000 { ++ status = "ok"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ status = "ok"; ++ }; ++ ++ usb3: usb3@8af8800 { ++ status = "ok"; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ status = "ok"; ++ }; ++ ++ usb2: usb2@60f8800 { ++ status = "ok"; ++ }; + }; + }; +diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi +index e5e52adbd5a3..e6b12129f0e4 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi +@@ -553,5 +553,79 @@ + "legacy"; + status = "disabled"; + }; ++ ++ usb3_ss_phy: ssphy@9a000 { ++ compatible = "qcom,usb-ss-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0x9a000 0x800>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB3_UNIPHY_PHY_ARES>; ++ reset-names = "por_rst"; ++ status = "disabled"; ++ }; ++ ++ usb3_hs_phy: hsphy@a6000 { ++ compatible = "qcom,usb-hs-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0xa6000 0x40>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; ++ reset-names = "por_rst", "srif_rst"; ++ status = "disabled"; ++ }; ++ ++ usb3@8af8800 { ++ compatible = "qcom,dwc3"; ++ reg = <0x8af8800 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc GCC_USB3_MASTER_CLK>, ++ <&gcc GCC_USB3_SLEEP_CLK>, ++ <&gcc GCC_USB3_MOCK_UTMI_CLK>; ++ clock-names = "master", "sleep", "mock_utmi"; ++ ranges; ++ status = "disabled"; ++ ++ dwc3@8a00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x8a00000 0xf8000>; ++ interrupts = <0 132 0>; ++ phys = <&usb3_hs_phy>, <&usb3_ss_phy>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ dr_mode = "host"; ++ }; ++ }; ++ ++ usb2_hs_phy: hsphy@a8000 { ++ compatible = "qcom,usb-hs-ipq4019-phy"; ++ #phy-cells = <0>; ++ reg = <0xa8000 0x40>; ++ reg-names = "phy_base"; ++ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; ++ reset-names = "por_rst", "srif_rst"; ++ status = "disabled"; ++ }; ++ ++ usb2@60f8800 { ++ compatible = "qcom,dwc3"; ++ reg = <0x60f8800 0x100>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc GCC_USB2_MASTER_CLK>, ++ <&gcc GCC_USB2_SLEEP_CLK>, ++ <&gcc GCC_USB2_MOCK_UTMI_CLK>; ++ clock-names = "master", "sleep", "mock_utmi"; ++ ranges; ++ status = "disabled"; ++ ++ dwc3@6000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x6000000 0xf8000>; ++ interrupts = <0 136 0>; ++ phys = <&usb2_hs_phy>; ++ phy-names = "usb2-phy"; ++ dr_mode = "host"; ++ }; ++ }; + }; + }; +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch index 0f039f206b..6f522ffcad 100644 --- a/target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch +++ b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch @@ -1,42 +1,89 @@ -From patchwork Mon Jan 29 05:11:16 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes +From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001 From: Sricharan R <sricharan@codeaurora.org> -X-Patchwork-Id: 10189263 -Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org> -To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com, - linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org, - catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org, - bjorn.andersson@linaro.org, devicetree@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org -Cc: sricharan@codeaurora.org -Date: Mon, 29 Jan 2018 10:41:16 +0530 +Date: Fri, 25 May 2018 11:41:12 +0530 +Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes Now with the driver updates for some peripherals being there, add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available peripheral support. +Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> +Signed-off-by: Andy Gross <andy.gross@linaro.org> --- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 134 insertions(+) + arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +- + arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++-- + 2 files changed, 146 insertions(+), 12 deletions(-) +diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +index ef8d8c88ed7b..418f9a022336 100644 +--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +@@ -69,7 +69,7 @@ + status = "ok"; + }; + +- spi_0: spi@78b5000 { ++ spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; +diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi +index 2efc8a2d41a7..737097e9fb4f 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -25,7 +25,9 @@ +@@ -40,8 +40,10 @@ + }; aliases { - spi0 = &spi_0; -+ spi1 = &spi_1; - i2c0 = &i2c_0; -+ i2c1 = &i2c_1; +- spi0 = &spi_0; +- i2c0 = &i2c_0; ++ spi0 = &blsp1_spi1; ++ spi1 = &blsp1_spi2; ++ i2c0 = &blsp1_i2c3; ++ i2c1 = &blsp1_i2c4; }; cpus { -@@ -190,6 +192,22 @@ +@@ -120,6 +122,12 @@ + }; + }; + ++ firmware { ++ scm { ++ compatible = "qcom,scm-ipq4019"; ++ }; ++ }; ++ + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, +@@ -165,13 +173,13 @@ + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +- interrupts = <0 208 0>; ++ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + }; + + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; +- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; ++ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; +@@ -179,7 +187,7 @@ + status = "disabled"; + }; + +- spi_0: spi@78b5000 { ++ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; +@@ -188,10 +196,26 @@ clock-names = "core", "iface"; #address-cells = <1>; #size-cells = <0>; @@ -45,7 +92,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> + status = "disabled"; + }; + -+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */ ++ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b6000 0x600>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -59,7 +106,12 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> status = "disabled"; }; -@@ -202,9 +220,24 @@ +- i2c_0: i2c@78b7000 { ++ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; +@@ -200,14 +224,29 @@ clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <0>; @@ -68,7 +120,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> status = "disabled"; }; -+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */ ++ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b8000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -84,7 +136,31 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> cryptobam: dma@8e04000 { compatible = "qcom,bam-v1.7.0"; -@@ -311,6 +344,101 @@ + reg = <0x08e04000 0x20000>; +- interrupts = <GIC_SPI 207 0>; ++ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; +@@ -275,7 +314,7 @@ + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; +- interrupts = <0 107 0>; ++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; +@@ -287,7 +326,7 @@ + serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; +- interrupts = <0 108 0>; ++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; +@@ -309,6 +348,101 @@ reg = <0x4ab000 0x4>; }; @@ -105,7 +181,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>; + -+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>; ++ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; @@ -186,3 +262,24 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org> wifi0: wifi@a000000 { compatible = "qcom,ipq4019-wifi"; reg = <0xa000000 0x200000>; +@@ -342,7 +476,7 @@ + <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, +- <GIC_SPI 168 IRQ_TYPE_NONE>; ++ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", +@@ -384,7 +518,7 @@ + <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, +- <GIC_SPI 169 IRQ_TYPE_NONE>; ++ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch b/target/linux/ipq40xx/patches-4.14/079-ARM-dts-ipq4019-fix-PCI-range.patch index eaccb00bb0..eaccb00bb0 100644 --- a/target/linux/ipq40xx/patches-4.14/102-ARM-dts-ipq4019-fix-PCI-range.patch +++ b/target/linux/ipq40xx/patches-4.14/079-ARM-dts-ipq4019-fix-PCI-range.patch diff --git a/target/linux/ipq40xx/patches-4.14/105-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch b/target/linux/ipq40xx/patches-4.14/080-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch index 57ed940fd1..57ed940fd1 100644 --- a/target/linux/ipq40xx/patches-4.14/105-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch +++ b/target/linux/ipq40xx/patches-4.14/080-pinctrl-msm-fix-gpio-hog-related-boot-issues.patch diff --git a/target/linux/ipq40xx/patches-4.14/900-clk-fix.patch b/target/linux/ipq40xx/patches-4.14/081-clk-fix-apss-cpu-overclocking.patch index 1c6b8c831d..dcf17874b3 100644 --- a/target/linux/ipq40xx/patches-4.14/900-clk-fix.patch +++ b/target/linux/ipq40xx/patches-4.14/081-clk-fix-apss-cpu-overclocking.patch @@ -1,7 +1,7 @@ -From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001 +From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001 From: Christian Lamparter <chunkeey@googlemail.com> -Date: Thu, 11 Mar 2018 14:41:31 +0100 -Subject: [PATCH] clk: fix apss cpu overclocking +Date: Sun, 11 Mar 2018 14:41:31 +0100 +Subject: [PATCH 2/2] clk: fix apss cpu overclocking There's an interaction issue between the clk changes:" clk: qcom: ipq4019: Add the apss cpu pll divider clock node @@ -37,10 +37,16 @@ try to overclock to 761 MHz. Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node") Signed-off-by: Christian Lamparter <chunkeey@gmail.com> +Signed-off-by: John Crispin <john@phrozen.org> --- + drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++--- + 1 file changed, 31 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c +index 46cb256b4aa2..4ec43f7d2e52 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fe +@@ -1253,6 +1253,29 @@ static const struct clk_fepll_vco gcc_fepll_vco = { .reg = 0x2f020, }; @@ -70,7 +76,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com> /* * Round rate function for APSS CPU PLL Clock divider. * It looks up the frequency table and returns the next higher frequency -@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struc +@@ -1265,7 +1288,7 @@ static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate, struct clk_hw *p_hw; const struct freq_tbl *f; @@ -79,7 +85,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com> if (!f) return -EINVAL; -@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct c +@@ -1288,7 +1311,7 @@ static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate, u32 mask; int ret; @@ -96,7 +102,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com> struct clk_fepll *pll = to_clk_fepll(hw); u32 cdiv, pre_div; u64 rate; -@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h +@@ -1335,7 +1359,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *hw, rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; do_div(rate, pre_div); @@ -109,3 +115,6 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com> }; static const struct clk_ops clk_regmap_cpu_div_ops = { +-- +2.11.0 + diff --git a/target/linux/ipq40xx/patches-4.14/865-ARM-dts-ipq4019-Add-TZ-and-SMEM-reserved-regions.patch b/target/linux/ipq40xx/patches-4.14/082-ARM-dts-ipq4019-Add-TZ-and-SMEM-reserved-regions.patch index 56ae66b089..56ae66b089 100644 --- a/target/linux/ipq40xx/patches-4.14/865-ARM-dts-ipq4019-Add-TZ-and-SMEM-reserved-regions.patch +++ b/target/linux/ipq40xx/patches-4.14/082-ARM-dts-ipq4019-Add-TZ-and-SMEM-reserved-regions.patch diff --git a/target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch b/target/linux/ipq40xx/patches-4.14/083-mtd-nand-add-Winbond-manufacturer-and-chip.patch index 295bc163b3..295bc163b3 100644 --- a/target/linux/ipq40xx/patches-4.14/104-mtd-nand-add-Winbond-manufacturer-and-chip.patch +++ b/target/linux/ipq40xx/patches-4.14/083-mtd-nand-add-Winbond-manufacturer-and-chip.patch diff --git a/target/linux/ipq40xx/patches-4.14/900-dts-ipq4019-ap-dk01.1.patch b/target/linux/ipq40xx/patches-4.14/900-dts-ipq4019-ap-dk01.1.patch index 9079a06df8..b24d85ba13 100644 --- a/target/linux/ipq40xx/patches-4.14/900-dts-ipq4019-ap-dk01.1.patch +++ b/target/linux/ipq40xx/patches-4.14/900-dts-ipq4019-ap-dk01.1.patch @@ -1,5 +1,7 @@ ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +=================================================================== +--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi ++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -15,12 +15,39 @@ */ @@ -40,9 +42,7 @@ rng@22000 { status = "ok"; }; ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -93,14 +93,6 @@ +@@ -66,14 +93,6 @@ pinctrl-names = "default"; status = "ok"; cs-gpios = <&tlmm 54 0>; @@ -57,11 +57,38 @@ }; serial@78af000 { ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -@@ -19,4 +19,71 @@ +@@ -102,6 +121,22 @@ + status = "ok"; + }; + ++ mdio@90000 { ++ status = "okay"; ++ }; ++ ++ ess-switch@c000000 { ++ status = "okay"; ++ }; ++ ++ ess-psgmii@98000 { ++ status = "okay"; ++ }; ++ ++ edma@c080000 { ++ status = "okay"; ++ }; ++ + usb3_ss_phy: ssphy@9a000 { + status = "ok"; + }; +Index: linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +=================================================================== +--- linux-4.14.54.orig/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts ++++ linux-4.14.54/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts +@@ -18,5 +18,73 @@ + / { model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; ++ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019"; + memory { + device_type = "memory"; @@ -69,7 +96,7 @@ + }; +}; + -+&spi_0 { ++&blsp1_spi1 { + mx25l25635f@0 { + compatible = "mx25l25635f", "jedec,spi-nor"; + #address-cells = <1>; @@ -131,38 +158,3 @@ + }; + }; }; ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts -@@ -18,6 +18,7 @@ - - / { - model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; -+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019"; - - memory { - device_type = "memory"; ---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi -@@ -121,6 +121,22 @@ - status = "ok"; - }; - -+ mdio@90000 { -+ status = "okay"; -+ }; -+ -+ ess-switch@c000000 { -+ status = "okay"; -+ }; -+ -+ ess-psgmii@98000 { -+ status = "okay"; -+ }; -+ -+ edma@c080000 { -+ status = "okay"; -+ }; -+ - usb3_ss_phy: ssphy@9a000 { - status = "ok"; - }; |