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Diffstat (limited to 'target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch')
-rw-r--r--target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch285
1 files changed, 285 insertions, 0 deletions
diff --git a/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
new file mode 100644
index 0000000000..6f522ffcad
--- /dev/null
+++ b/target/linux/ipq40xx/patches-4.14/078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
@@ -0,0 +1,285 @@
+From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
+From: Sricharan R <sricharan@codeaurora.org>
+Date: Fri, 25 May 2018 11:41:12 +0530
+Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
+
+Now with the driver updates for some peripherals being there,
+add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
+peripheral support.
+
+Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
+Signed-off-by: Sricharan R <sricharan@codeaurora.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
+ 2 files changed, 146 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+index ef8d8c88ed7b..418f9a022336 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+@@ -69,7 +69,7 @@
+ status = "ok";
+ };
+
+- spi_0: spi@78b5000 {
++ spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+index 2efc8a2d41a7..737097e9fb4f 100644
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -40,8 +40,10 @@
+ };
+
+ aliases {
+- spi0 = &spi_0;
+- i2c0 = &i2c_0;
++ spi0 = &blsp1_spi1;
++ spi1 = &blsp1_spi2;
++ i2c0 = &blsp1_i2c3;
++ i2c1 = &blsp1_i2c4;
+ };
+
+ cpus {
+@@ -120,6 +122,12 @@
+ };
+ };
+
++ firmware {
++ scm {
++ compatible = "qcom,scm-ipq4019";
++ };
++ };
++
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 2 0xf08>,
+@@ -165,13 +173,13 @@
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+- interrupts = <0 208 0>;
++ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ blsp_dma: dma@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x23000>;
+- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
++ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+@@ -179,7 +187,7 @@
+ status = "disabled";
+ };
+
+- spi_0: spi@78b5000 {
++ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+@@ -188,10 +196,26 @@
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
++ compatible = "qcom,spi-qup-v2.2.1";
++ reg = <0x78b6000 0x600>;
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
++ <&gcc GCC_BLSP1_AHB_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- i2c_0: i2c@78b7000 {
++ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+@@ -200,14 +224,29 @@
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
++ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
++ compatible = "qcom,i2c-qup-v2.2.1";
++ reg = <0x78b8000 0x600>;
++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
++ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
++ clock-names = "iface", "core";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
+
+ cryptobam: dma@8e04000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x08e04000 0x20000>;
+- interrupts = <GIC_SPI 207 0>;
++ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+@@ -275,7 +314,7 @@
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+- interrupts = <0 107 0>;
++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+@@ -287,7 +326,7 @@
+ serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b0000 0x200>;
+- interrupts = <0 108 0>;
++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+@@ -309,6 +348,101 @@
+ reg = <0x4ab000 0x4>;
+ };
+
++ pcie0: pci@40000000 {
++ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
++ reg = <0x40000000 0xf1d
++ 0x40000f20 0xa8
++ 0x80000 0x2000
++ 0x40100000 0x1000>;
++ reg-names = "dbi", "elbi", "parf", "config";
++ device_type = "pci";
++ linux,pci-domain = <0>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
++ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
++
++ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++ clocks = <&gcc GCC_PCIE_AHB_CLK>,
++ <&gcc GCC_PCIE_AXI_M_CLK>,
++ <&gcc GCC_PCIE_AXI_S_CLK>;
++ clock-names = "aux",
++ "master_bus",
++ "slave_bus";
++
++ resets = <&gcc PCIE_AXI_M_ARES>,
++ <&gcc PCIE_AXI_S_ARES>,
++ <&gcc PCIE_PIPE_ARES>,
++ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
++ <&gcc PCIE_AXI_S_XPU_ARES>,
++ <&gcc PCIE_PARF_XPU_ARES>,
++ <&gcc PCIE_PHY_ARES>,
++ <&gcc PCIE_AXI_M_STICKY_ARES>,
++ <&gcc PCIE_PIPE_STICKY_ARES>,
++ <&gcc PCIE_PWR_ARES>,
++ <&gcc PCIE_AHB_ARES>,
++ <&gcc PCIE_PHY_AHB_ARES>;
++ reset-names = "axi_m",
++ "axi_s",
++ "pipe",
++ "axi_m_vmid",
++ "axi_s_xpu",
++ "parf",
++ "phy",
++ "axi_m_sticky",
++ "pipe_sticky",
++ "pwr",
++ "ahb",
++ "phy_ahb";
++
++ status = "disabled";
++ };
++
++ qpic_bam: dma@7984000 {
++ compatible = "qcom,bam-v1.7.0";
++ reg = <0x7984000 0x1a000>;
++ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GCC_QPIC_CLK>;
++ clock-names = "bam_clk";
++ #dma-cells = <1>;
++ qcom,ee = <0>;
++ status = "disabled";
++ };
++
++ nand: qpic-nand@79b0000 {
++ compatible = "qcom,ipq4019-nand";
++ reg = <0x79b0000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&gcc GCC_QPIC_CLK>,
++ <&gcc GCC_QPIC_AHB_CLK>;
++ clock-names = "core", "aon";
++
++ dmas = <&qpic_bam 0>,
++ <&qpic_bam 1>,
++ <&qpic_bam 2>;
++ dma-names = "tx", "rx", "cmd";
++ status = "disabled";
++
++ nand@0 {
++ reg = <0>;
++
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ nand-bus-width = <8>;
++ };
++ };
++
+ wifi0: wifi@a000000 {
+ compatible = "qcom,ipq4019-wifi";
+ reg = <0xa000000 0x200000>;
+@@ -342,7 +476,7 @@
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+- <GIC_SPI 168 IRQ_TYPE_NONE>;
++ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+@@ -384,7 +518,7 @@
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+- <GIC_SPI 169 IRQ_TYPE_NONE>;
++ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7",
+ "msi8", "msi9", "msi10", "msi11",
+--
+2.11.0
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 12:48:45 +0000