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-rw-r--r--target/linux/imx6/patches-3.10/020-marvell-sky2-macdt.patch57
-rw-r--r--target/linux/imx6/patches-3.10/110-gw5400-a.patch190
-rw-r--r--target/linux/imx6/patches-3.10/200-imx6_pcie.patch91
3 files changed, 338 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.10/020-marvell-sky2-macdt.patch b/target/linux/imx6/patches-3.10/020-marvell-sky2-macdt.patch
new file mode 100644
index 0000000000..e1639d6223
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/020-marvell-sky2-macdt.patch
@@ -0,0 +1,57 @@
+--- a/drivers/net/ethernet/marvell/sky2.c
++++ b/drivers/net/ethernet/marvell/sky2.c
+@@ -44,6 +44,8 @@
+ #include <linux/prefetch.h>
+ #include <linux/debugfs.h>
+ #include <linux/mii.h>
++#include <linux/of_device.h>
++#include <linux/of_net.h>
+
+ #include <asm/irq.h>
+
+@@ -4748,6 +4750,7 @@ static struct net_device *sky2_init_netd
+ {
+ struct sky2_port *sky2;
+ struct net_device *dev = alloc_etherdev(sizeof(*sky2));
++ unsigned char *iap, tmpaddr[ETH_ALEN];
+
+ if (!dev)
+ return NULL;
+@@ -4802,8 +4805,36 @@ static struct net_device *sky2_init_netd
+
+ dev->features |= dev->hw_features;
+
++ /*
++ * try to get mac address in the following order:
++ * 1) from device tree data
++ * 2) from internal registers set by bootloader
++ */
++ iap = NULL;
++#ifdef CONFIG_OF
++ struct device_node *np;
++ np = of_find_node_by_path("/aliases");
++ if (np) {
++ const char *path = of_get_property(np, "sky2", NULL);
++ if (path)
++ np = of_find_node_by_path(path);
++ if (np)
++ path = of_get_mac_address(np);
++ if (path)
++ iap = (unsigned char *) path;
++ }
++#endif
++
++ /*
++ * 2) mac registers set by bootloader
++ */
++ if (!iap || !is_valid_ether_addr(iap)) {
++ memcpy_fromio(&tmpaddr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
++ iap = &tmpaddr[0];
++ }
++
+ /* read the mac address */
+- memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
++ memcpy(dev->dev_addr, iap, ETH_ALEN);
+
+ return dev;
+ }
diff --git a/target/linux/imx6/patches-3.10/110-gw5400-a.patch b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
new file mode 100644
index 0000000000..3f7f1fc7f3
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
@@ -0,0 +1,190 @@
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
+ imx6dl-sabresd.dtb \
+ imx6dl-wandboard.dtb \
+ imx6q-arm2.dtb \
++ imx6q-gw5400-a.dtb \
+ imx6q-sabreauto.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb \
+--- a/arch/arm/boot/dts/imx6q.dtsi
++++ b/arch/arm/boot/dts/imx6q.dtsi
+@@ -94,6 +94,14 @@
+ MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+ >;
+ };
++
++ pinctrl_audmux_3: audmux-3 {
++ fsl,pins = <
++ MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
++ MX6Q_PAD_EIM_D25__AUD5_RXC 0x80000000
++ MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
++ >;
++ };
+ };
+
+ ecspi1 {
+@@ -201,6 +209,12 @@
+ MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
++ pinctrl_i2c2_2: i2c2grp-2 {
++ fsl,pins = <
++ MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
+ };
+
+ i2c3 {
+@@ -210,6 +224,12 @@
+ MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
++ pinctrl_i2c3_2: i2c3grp-2 {
++ fsl,pins = <
++ MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
+ };
+
+ uart1 {
+@@ -219,6 +239,12 @@
+ MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
++ pinctrl_uart1_2: uart1grp-2 {
++ fsl,pins = <
++ MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
++ MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
++ >;
++ };
+ };
+
+ uart2 {
+@@ -228,6 +254,21 @@
+ MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
++ pinctrl_uart2_2: uart2grp-2 {
++ fsl,pins = <
++ MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ uart3 {
++ pinctrl_uart3_1: uart3grp-1 {
++ fsl,pins = <
++ MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
++ MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
++ >;
++ };
+ };
+
+ uart4 {
+@@ -238,6 +279,15 @@
+ >;
+ };
+ };
++
++ uart5 {
++ pinctrl_uart5_1: uart5grp-1 {
++ fsl,pins = <
++ MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++ };
+
+ usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+--- a/arch/arm/mach-imx/mach-imx6q.c
++++ b/arch/arm/mach-imx/mach-imx6q.c
+@@ -25,6 +25,7 @@
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
+ #include <linux/opp.h>
++#include <linux/pci.h>
+ #include <linux/phy.h>
+ #include <linux/regmap.h>
+ #include <linux/micrel_phy.h>
+@@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
+ imx6q_sabrelite_cko1_setup();
+ }
+
++/*
++ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
++ * as they are used for slots1-7 PERST#
++ */
++static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
++{
++ u32 dw;
++
++ if (!of_machine_is_compatible("gw,ventana"))
++ return;
++
++ if (dev->devfn != 0)
++ return;
++
++ pci_read_config_dword(dev, 0x62c, &dw);
++ dw |= 0xaaa8; // GPIO1-7 outputs
++ pci_write_config_dword(dev, 0x62c, dw);
++
++ pci_read_config_dword(dev, 0x644, &dw);
++ dw |= 0xfe; // GPIO1-7 output high
++ pci_write_config_dword(dev, 0x644, dw);
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
++ mx6_ventana_pciesw_early_fixup);
++
++/*
++ * configure PCIe core clock and PCIe ref clock
++ *
++ * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
++ */
++static void __init imx6q_ventana_pcie_setup(void)
++{
++ struct clk *axi_sel, *axi, *ref;
++
++ axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
++ axi = clk_get_sys(NULL, "axi");
++ ref = clk_get_sys(NULL, "pcie_ref_125m");
++ if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
++ pr_err("pcie setup failed - can't get clocks\n");
++ goto put_clk;
++ }
++ clk_set_parent(axi_sel, axi);
++ clk_prepare_enable(ref);
++
++put_clk:
++ if (!IS_ERR(axi_sel))
++ clk_put(axi_sel);
++ if (!IS_ERR(axi))
++ clk_put(axi);
++ if (!IS_ERR(ref))
++ clk_put(ref);
++}
++
++static void __init imx6q_ventana_init(void)
++{
++ imx6q_ventana_pcie_setup();
++ imx6q_sabrelite_cko1_setup();
++}
++
+ static void __init imx6q_1588_init(void)
+ {
+ struct regmap *gpr;
+@@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
+
+ static void __init imx6q_init_machine(void)
+ {
++ if (of_machine_is_compatible("gw,ventana"))
++ imx6q_ventana_init();
++
+ if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+ imx6q_sabrelite_init();
+
diff --git a/target/linux/imx6/patches-3.10/200-imx6_pcie.patch b/target/linux/imx6/patches-3.10/200-imx6_pcie.patch
new file mode 100644
index 0000000000..1f84d5eb72
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/200-imx6_pcie.patch
@@ -0,0 +1,91 @@
+--- a/arch/arm/boot/dts/imx6q.dtsi
++++ b/arch/arm/boot/dts/imx6q.dtsi
+@@ -328,6 +328,15 @@
+ };
+ };
+
++ pcie: pcie@01ffc000 {
++ #crtc-cells = <1>;
++ compatible = "fsl,imx6q-pcie", "fsl,pcie";
++ reg = <0x01ffc000 0x4000>;
++ clocks = <&clks 144>, <&clks 189>;
++ clock-names = "pcie_axi", "pcie_ref_125m";
++ status = "disabled";
++ };
++
+ ipu2: ipu@02800000 {
+ #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+--- a/arch/arm/mach-imx/Kconfig
++++ b/arch/arm/mach-imx/Kconfig
+@@ -790,6 +790,8 @@ config SOC_IMX6Q
+ bool "i.MX6 Quad/DualLite support"
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_OPP
++ select ARCH_HAS_IMX_PCIE
++ select ARCH_SUPPORTS_MSI
+ select ARM_CPU_SUSPEND if PM
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369 if SMP
+@@ -816,6 +818,10 @@ config SOC_IMX6Q
+ help
+ This enables support for Freescale i.MX6 Quad processor.
+
++config IMX_PCIE
++ bool "PCI Express support"
++ select PCI
++
+ endif
+
+ source "arch/arm/mach-imx/devices/Kconfig"
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -98,6 +98,8 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
++obj-$(CONFIG_IMX_PCIE) += pcie.o
++obj-$(CONFIG_PCI_MSI) += msi.o
+
+ ifeq ($(CONFIG_PM),y)
+ obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -547,6 +547,12 @@ int __init mx6q_clocks_init(void)
+ clk_register_clkdev(clk[ahb], "ahb", NULL);
+ clk_register_clkdev(clk[cko1], "cko1", NULL);
+ clk_register_clkdev(clk[arm], NULL, "cpu0");
++ clk_register_clkdev(clk[pcie_axi_sel], "pcie_axi_sel", NULL);
++ clk_register_clkdev(clk[axi], "axi", NULL);
++ clk_register_clkdev(clk[pll6_enet], "pll6_enet", NULL);
++ clk_register_clkdev(clk[pcie_ref], "pcie_ref", NULL);
++ clk_register_clkdev(clk[pcie_ref_125m], "pcie_ref_125m", NULL);
++ clk_register_clkdev(clk[pcie_axi], "pcie_axi", NULL);
+
+ if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+ clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+--- a/arch/arm/mach-imx/mxc.h
++++ b/arch/arm/mach-imx/mxc.h
+@@ -151,6 +151,10 @@ extern unsigned int __mxc_cpu_type;
+ # define cpu_is_mx53() (0)
+ #endif
+
++#ifdef CONFIG_SOC_IMX6Q
++# define mxc_cpu_type __mxc_cpu_type
++#endif
++
+ #ifndef __ASSEMBLY__
+ static inline bool cpu_is_imx6dl(void)
+ {
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -178,6 +178,9 @@ extern int pci_ioremap_io(unsigned int o
+ */
+ #ifdef CONFIG_NEED_MACH_IO_H
+ #include <mach/io.h>
++#elif defined(CONFIG_SOC_IMX6Q) && defined(CONFIG_IMX_PCIE)
++#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
++#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
+ #elif defined(CONFIG_PCI)
+ #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
+ #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 12:22:05 +0000