diff options
Diffstat (limited to 'target/linux/bcm53xx/patches-4.4/033-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch')
| -rw-r--r-- | target/linux/bcm53xx/patches-4.4/033-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-4.4/033-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.4/033-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch new file mode 100644 index 0000000000..ad560261d3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.4/033-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch @@ -0,0 +1,70 @@ +From fa20071c74be69a1d84df85e5d1e72a40a156b89 Mon Sep 17 00:00:00 2001 +From: Kapil Hali <kapilh@broadcom.com> +Date: Tue, 1 Dec 2015 11:24:05 -0500 +Subject: [PATCH] dt-bindings: add SMP enable-method for Broadcom NSP + +Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's +Northstar Plus CPU to the 32-bit ARM CPU device tree binding +documentation file and create a new binding documentation for +Northstar Plus CPU. + +Signed-off-by: Kapil Hali <kapilh@broadcom.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++ + Documentation/devicetree/bindings/arm/cpus.txt | 1 + + 2 files changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt +@@ -0,0 +1,39 @@ ++Broadcom Northstar Plus SoC CPU Enable Method ++--------------------------------------------- ++This binding defines the enable method used for starting secondary ++CPUs in the following Broadcom SoCs: ++ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 ++ ++The enable method is specified by defining the following required ++properties in the "cpus" device tree node: ++ - enable-method = "brcm,bcm-nsp-smp"; ++ - secondary-boot-reg = <...>; ++ ++The secondary-boot-reg property is a u32 value that specifies the ++physical address of the register which should hold the common ++entry point for a secondary CPU. This entry is cpu node specific ++and should be added per cpu. E.g., in case of NSP (BCM58625) which ++is a dual core CPU SoC, this entry should be added to cpu1 node. ++ ++ ++Example: ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "brcm,bcm-nsp-smp"; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ next-level-cache = <&L2>; ++ reg = <0>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ next-level-cache = <&L2>; ++ reg = <1>; ++ secondary-boot-reg = <0xffff042c>; ++ }; ++ }; +--- a/Documentation/devicetree/bindings/arm/cpus.txt ++++ b/Documentation/devicetree/bindings/arm/cpus.txt +@@ -190,6 +190,7 @@ nodes to be present and contain the properties described below. + "allwinner,sun6i-a31" + "allwinner,sun8i-a23" + "arm,psci" ++ "brcm,bcm-nsp-smp" + "brcm,brahma-b15" + "marvell,armada-375-smp" + "marvell,armada-380-smp" |