diff options
Diffstat (limited to 'target/linux/bcm53xx/patches-3.10')
6 files changed, 0 insertions, 1121 deletions
diff --git a/target/linux/bcm53xx/patches-3.10/001-clocksource-arm_global_timer-Add-ARM-global-timer-su.patch b/target/linux/bcm53xx/patches-3.10/001-clocksource-arm_global_timer-Add-ARM-global-timer-su.patch deleted file mode 100644 index 3182b9c596..0000000000 --- a/target/linux/bcm53xx/patches-3.10/001-clocksource-arm_global_timer-Add-ARM-global-timer-su.patch +++ /dev/null @@ -1,421 +0,0 @@ -From 5afd20a1eeef4db1d694d58931519f65e2003503 Mon Sep 17 00:00:00 2001 -From: Stuart Menefy <stuart.menefy@st.com> -Date: Wed, 26 Jun 2013 12:48:38 +0100 -Subject: [PATCH 01/18] clocksource: arm_global_timer: Add ARM global timer - support - -This is a simple driver for the global timer module found in the Cortex -A9-MP cores from revision r1p0 onwards. This should be able to perform -the functions of the system timer and the local timer in an SMP system. - -The global timer has the following features: - The global timer is a 64-bit incrementing counter with an -auto-incrementing feature. It continues incrementing after sending -interrupts. The global timer is memory mapped in the private memory -region. - The global timer is accessible to all Cortex-A9 processors in the -cluster. Each Cortex-A9 processor has a private 64-bit comparator that -is used to assert a private interrupt when the global timer has reached -the comparator value. All the Cortex-A9 processors in a design use the -banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt -Controller as a Private Peripheral Interrupt. The global timer is -clocked by PERIPHCLK. - -Signed-off-by: Stuart Menefy <stuart.menefy@st.com> -Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> -CC: Arnd Bergmann <arnd@arndb.de> -CC: Rob Herring <robherring2@gmail.com> -CC: Linus Walleij <linus.walleij@linaro.org> -CC: Will Deacon <will.deacon@arm.com> -CC: Thomas Gleixner <tglx@linutronix.de> -Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> ---- - .../devicetree/bindings/arm/global_timer.txt | 24 ++ - drivers/clocksource/Kconfig | 13 + - drivers/clocksource/Makefile | 1 + - drivers/clocksource/arm_global_timer.c | 321 ++++++++++++++++++++ - 4 files changed, 359 insertions(+) - create mode 100644 Documentation/devicetree/bindings/arm/global_timer.txt - create mode 100644 drivers/clocksource/arm_global_timer.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/arm/global_timer.txt -@@ -0,0 +1,24 @@ -+ -+* ARM Global Timer -+ Cortex-A9 are often associated with a per-core Global timer. -+ -+** Timer node required properties: -+ -+- compatible : Should be "arm,cortex-a9-global-timer" -+ Driver supports versions r2p0 and above. -+ -+- interrupts : One interrupt to each core -+ -+- reg : Specify the base address and the size of the GT timer -+ register window. -+ -+- clocks : Should be phandle to a clock. -+ -+Example: -+ -+ timer@2c000600 { -+ compatible = "arm,cortex-a9-global-timer"; -+ reg = <0x2c000600 0x20>; -+ interrupts = <1 13 0xf01>; -+ clocks = <&arm_periph_clk>; -+ }; ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -67,6 +67,19 @@ config ARM_ARCH_TIMER - bool - select CLKSRC_OF if OF - -+config ARM_GLOBAL_TIMER -+ bool -+ select CLKSRC_OF if OF -+ help -+ This options enables support for the ARM global timer unit -+ -+config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK -+ bool -+ depends on ARM_GLOBAL_TIMER -+ default y -+ help -+ Use ARM global timer clock source as sched_clock -+ - config CLKSRC_METAG_GENERIC - def_bool y if METAG - help ---- a/drivers/clocksource/Makefile -+++ b/drivers/clocksource/Makefile -@@ -28,4 +28,5 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno - obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o - - obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o -+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o - obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o ---- /dev/null -+++ b/drivers/clocksource/arm_global_timer.c -@@ -0,0 +1,321 @@ -+/* -+ * drivers/clocksource/arm_global_timer.c -+ * -+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited. -+ * Author: Stuart Menefy <stuart.menefy@st.com> -+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include <linux/init.h> -+#include <linux/interrupt.h> -+#include <linux/clocksource.h> -+#include <linux/clockchips.h> -+#include <linux/cpu.h> -+#include <linux/clk.h> -+#include <linux/err.h> -+#include <linux/io.h> -+#include <linux/of.h> -+#include <linux/of_irq.h> -+#include <linux/of_address.h> -+#include <asm/sched_clock.h> -+ -+#include <asm/cputype.h> -+ -+#define GT_COUNTER0 0x00 -+#define GT_COUNTER1 0x04 -+ -+#define GT_CONTROL 0x08 -+#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ -+#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ -+#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ -+#define GT_CONTROL_AUTO_INC BIT(3) /* banked */ -+ -+#define GT_INT_STATUS 0x0c -+#define GT_INT_STATUS_EVENT_FLAG BIT(0) -+ -+#define GT_COMP0 0x10 -+#define GT_COMP1 0x14 -+#define GT_AUTO_INC 0x18 -+ -+/* -+ * We are expecting to be clocked by the ARM peripheral clock. -+ * -+ * Note: it is assumed we are using a prescaler value of zero, so this is -+ * the units for all operations. -+ */ -+static void __iomem *gt_base; -+static unsigned long gt_clk_rate; -+static int gt_ppi; -+static struct clock_event_device __percpu *gt_evt; -+ -+/* -+ * To get the value from the Global Timer Counter register proceed as follows: -+ * 1. Read the upper 32-bit timer counter register -+ * 2. Read the lower 32-bit timer counter register -+ * 3. Read the upper 32-bit timer counter register again. If the value is -+ * different to the 32-bit upper value read previously, go back to step 2. -+ * Otherwise the 64-bit timer counter value is correct. -+ */ -+static u64 gt_counter_read(void) -+{ -+ u64 counter; -+ u32 lower; -+ u32 upper, old_upper; -+ -+ upper = readl_relaxed(gt_base + GT_COUNTER1); -+ do { -+ old_upper = upper; -+ lower = readl_relaxed(gt_base + GT_COUNTER0); -+ upper = readl_relaxed(gt_base + GT_COUNTER1); -+ } while (upper != old_upper); -+ -+ counter = upper; -+ counter <<= 32; -+ counter |= lower; -+ return counter; -+} -+ -+/** -+ * To ensure that updates to comparator value register do not set the -+ * Interrupt Status Register proceed as follows: -+ * 1. Clear the Comp Enable bit in the Timer Control Register. -+ * 2. Write the lower 32-bit Comparator Value Register. -+ * 3. Write the upper 32-bit Comparator Value Register. -+ * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. -+ */ -+static void gt_compare_set(unsigned long delta, int periodic) -+{ -+ u64 counter = gt_counter_read(); -+ unsigned long ctrl; -+ -+ counter += delta; -+ ctrl = GT_CONTROL_TIMER_ENABLE; -+ writel(ctrl, gt_base + GT_CONTROL); -+ writel(lower_32_bits(counter), gt_base + GT_COMP0); -+ writel(upper_32_bits(counter), gt_base + GT_COMP1); -+ -+ if (periodic) { -+ writel(delta, gt_base + GT_AUTO_INC); -+ ctrl |= GT_CONTROL_AUTO_INC; -+ } -+ -+ ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE; -+ writel(ctrl, gt_base + GT_CONTROL); -+} -+ -+static void gt_clockevent_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ unsigned long ctrl; -+ -+ switch (mode) { -+ case CLOCK_EVT_MODE_PERIODIC: -+ gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1); -+ break; -+ case CLOCK_EVT_MODE_ONESHOT: -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ ctrl = readl(gt_base + GT_CONTROL); -+ ctrl &= ~(GT_CONTROL_COMP_ENABLE | -+ GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC); -+ writel(ctrl, gt_base + GT_CONTROL); -+ break; -+ default: -+ break; -+ } -+} -+ -+static int gt_clockevent_set_next_event(unsigned long evt, -+ struct clock_event_device *unused) -+{ -+ gt_compare_set(evt, 0); -+ return 0; -+} -+ -+static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = dev_id; -+ -+ if (!(readl_relaxed(gt_base + GT_INT_STATUS) & -+ GT_INT_STATUS_EVENT_FLAG)) -+ return IRQ_NONE; -+ -+ /** -+ * ERRATA 740657( Global Timer can send 2 interrupts for -+ * the same event in single-shot mode) -+ * Workaround: -+ * Either disable single-shot mode. -+ * Or -+ * Modify the Interrupt Handler to avoid the -+ * offending sequence. This is achieved by clearing -+ * the Global Timer flag _after_ having incremented -+ * the Comparator register value to a higher value. -+ */ -+ if (evt->mode == CLOCK_EVT_MODE_ONESHOT) -+ gt_compare_set(ULONG_MAX, 0); -+ -+ writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS); -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static int __cpuinit gt_clockevents_init(struct clock_event_device *clk) -+{ -+ int cpu = smp_processor_id(); -+ -+ clk->name = "arm_global_timer"; -+ clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; -+ clk->set_mode = gt_clockevent_set_mode; -+ clk->set_next_event = gt_clockevent_set_next_event; -+ clk->cpumask = cpumask_of(cpu); -+ clk->rating = 300; -+ clk->irq = gt_ppi; -+ clockevents_config_and_register(clk, gt_clk_rate, -+ 1, 0xffffffff); -+ enable_percpu_irq(clk->irq, IRQ_TYPE_NONE); -+ return 0; -+} -+ -+static void gt_clockevents_stop(struct clock_event_device *clk) -+{ -+ gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk); -+ disable_percpu_irq(clk->irq); -+} -+ -+static cycle_t gt_clocksource_read(struct clocksource *cs) -+{ -+ return gt_counter_read(); -+} -+ -+static struct clocksource gt_clocksource = { -+ .name = "arm_global_timer", -+ .rating = 300, -+ .read = gt_clocksource_read, -+ .mask = CLOCKSOURCE_MASK(64), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK -+static u32 notrace gt_sched_clock_read(void) -+{ -+ return gt_counter_read(); -+} -+#endif -+ -+static void __init gt_clocksource_init(void) -+{ -+ writel(0, gt_base + GT_CONTROL); -+ writel(0, gt_base + GT_COUNTER0); -+ writel(0, gt_base + GT_COUNTER1); -+ /* enables timer on all the cores */ -+ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); -+ -+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK -+ setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate); -+#endif -+ clocksource_register_hz(>_clocksource, gt_clk_rate); -+} -+ -+static int __cpuinit gt_cpu_notify(struct notifier_block *self, -+ unsigned long action, void *hcpu) -+{ -+ switch (action & ~CPU_TASKS_FROZEN) { -+ case CPU_STARTING: -+ gt_clockevents_init(this_cpu_ptr(gt_evt)); -+ break; -+ case CPU_DYING: -+ gt_clockevents_stop(this_cpu_ptr(gt_evt)); -+ break; -+ } -+ -+ return NOTIFY_OK; -+} -+static struct notifier_block gt_cpu_nb __cpuinitdata = { -+ .notifier_call = gt_cpu_notify, -+}; -+ -+static void __init global_timer_of_register(struct device_node *np) -+{ -+ struct clk *gt_clk; -+ int err = 0; -+ -+ /* -+ * In r2p0 the comparators for each processor with the global timer -+ * fire when the timer value is greater than or equal to. In previous -+ * revisions the comparators fired when the timer value was equal to. -+ */ -+ if ((read_cpuid_id() & 0xf0000f) < 0x200000) { -+ pr_warn("global-timer: non support for this cpu version.\n"); -+ return; -+ } -+ -+ gt_ppi = irq_of_parse_and_map(np, 0); -+ if (!gt_ppi) { -+ pr_warn("global-timer: unable to parse irq\n"); -+ return; -+ } -+ -+ gt_base = of_iomap(np, 0); -+ if (!gt_base) { -+ pr_warn("global-timer: invalid base address\n"); -+ return; -+ } -+ -+ gt_clk = of_clk_get(np, 0); -+ if (!IS_ERR(gt_clk)) { -+ err = clk_prepare_enable(gt_clk); -+ if (err) -+ goto out_unmap; -+ } else { -+ pr_warn("global-timer: clk not found\n"); -+ err = -EINVAL; -+ goto out_unmap; -+ } -+ -+ gt_clk_rate = clk_get_rate(gt_clk); -+ gt_evt = alloc_percpu(struct clock_event_device); -+ if (!gt_evt) { -+ pr_warn("global-timer: can't allocate memory\n"); -+ err = -ENOMEM; -+ goto out_clk; -+ } -+ -+ err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt, -+ "gt", gt_evt); -+ if (err) { -+ pr_warn("global-timer: can't register interrupt %d (%d)\n", -+ gt_ppi, err); -+ goto out_free; -+ } -+ -+ err = register_cpu_notifier(>_cpu_nb); -+ if (err) { -+ pr_warn("global-timer: unable to register cpu notifier.\n"); -+ goto out_irq; -+ } -+ -+ /* Immediately configure the timer on the boot CPU */ -+ gt_clocksource_init(); -+ gt_clockevents_init(this_cpu_ptr(gt_evt)); -+ -+ return; -+ -+out_irq: -+ free_percpu_irq(gt_ppi, gt_evt); -+out_free: -+ free_percpu(gt_evt); -+out_clk: -+ clk_disable_unprepare(gt_clk); -+out_unmap: -+ iounmap(gt_base); -+ WARN(err, "ARM Global timer register failed (%d)\n", err); -+} -+ -+/* Only tested on r2p2 and r3p0 */ -+CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer", -+ global_timer_of_register); diff --git a/target/linux/bcm53xx/patches-3.10/051-bcm53xx-initial-support-for-the-BCM5301-BCM470X-SoC-.patch b/target/linux/bcm53xx/patches-3.10/051-bcm53xx-initial-support-for-the-BCM5301-BCM470X-SoC-.patch deleted file mode 100644 index 812183120d..0000000000 --- a/target/linux/bcm53xx/patches-3.10/051-bcm53xx-initial-support-for-the-BCM5301-BCM470X-SoC-.patch +++ /dev/null @@ -1,379 +0,0 @@ -bcm53xx: initial support for the BCM5301/BCM470X SoC - with ARM CPU - -This patch adds support for the BCM5301/BCM470X SoCs with an ARM CPU. -Currently just booting to a shell is working and nothing else, no -Ethernet, wifi, flash, ... - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - arch/arm/Kconfig | 2 + - arch/arm/Kconfig.debug | 5 ++ - arch/arm/Makefile | 1 + - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/bcm5301-netgear-r6250.dts | 20 +++++++ - arch/arm/boot/dts/bcm5301.dtsi | 83 +++++++++++++++++++++++++++ - arch/arm/include/debug/bcm53xx.S | 19 ++++++ - arch/arm/mach-bcm53xx/Kconfig | 15 +++++ - arch/arm/mach-bcm53xx/Makefile | 1 + - arch/arm/mach-bcm53xx/bcm53xx.c | 69 ++++++++++++++++++++++ - 10 files changed, 216 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm5301-netgear-r6250.dts - create mode 100644 arch/arm/boot/dts/bcm5301.dtsi - create mode 100644 arch/arm/include/debug/bcm53xx.S - create mode 100644 arch/arm/mach-bcm53xx/Kconfig - create mode 100644 arch/arm/mach-bcm53xx/Makefile - create mode 100644 arch/arm/mach-bcm53xx/bcm53xx.c - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -922,6 +922,8 @@ source "arch/arm/mach-bcm/Kconfig" - - source "arch/arm/mach-bcm2835/Kconfig" - -+source "arch/arm/mach-bcm53xx/Kconfig" -+ - source "arch/arm/mach-clps711x/Kconfig" - - source "arch/arm/mach-cns3xxx/Kconfig" ---- a/arch/arm/Kconfig.debug -+++ b/arch/arm/Kconfig.debug -@@ -93,6 +93,10 @@ choice - bool "Kernel low-level debugging on BCM2835 PL011 UART" - depends on ARCH_BCM2835 - -+ config DEBUG_BCM_5301X -+ bool "Kernel low-level debugging on BCM53XX UART1" -+ depends on ARCH_BCM_5301X -+ - config DEBUG_CLPS711X_UART1 - bool "Kernel low-level debugging messages via UART1" - depends on ARCH_CLPS711X -@@ -620,6 +624,7 @@ endchoice - config DEBUG_LL_INCLUDE - string - default "debug/bcm2835.S" if DEBUG_BCM2835 -+ default "debug/bcm53xx.S" if DEBUG_BCM_5301X - default "debug/cns3xxx.S" if DEBUG_CNS3XXX - default "debug/exynos.S" if DEBUG_EXYNOS_UART - default "debug/highbank.S" if DEBUG_HIGHBANK_UART ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -145,6 +145,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020 - machine-$(CONFIG_ARCH_AT91) += at91 - machine-$(CONFIG_ARCH_BCM) += bcm - machine-$(CONFIG_ARCH_BCM2835) += bcm2835 -+machine-$(CONFIG_ARCH_BCM_5301X) += bcm53xx - machine-$(CONFIG_ARCH_CLPS711X) += clps711x - machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx - machine-$(CONFIG_ARCH_DAVINCI) += davinci ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -209,6 +209,7 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07 - wm8650-mid.dtb \ - wm8850-w70v2.dtb - dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb -+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb - - targets += dtbs - targets += $(dtb-y) ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -0,0 +1,35 @@ -+/* -+ * Broadcom BCM470X / BCM5301X arm platform code. -+ * DTS for Netgear R6250 V1 -+ * -+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+ -+/ { -+ compatible = "netgear,r6250v1", "brcm,bcm4708"; -+ model = "Netgear R6250 V1 (BCM4708)"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000>; -+ }; -+ -+ chipcommonA { -+ uart0: serial@0300 { -+ status = "okay"; -+ }; -+ -+ uart1: serial@0400 { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708.dtsi -@@ -0,0 +1,34 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * DTS for BCM4708 SoC. -+ * -+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+#include "bcm5301x.dtsi" -+ -+/ { -+ compatible = "brcm,bcm4708"; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a9"; -+ next-level-cache = <&L2>; -+ reg = <0x0>; -+ }; -+ -+ cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a9"; -+ next-level-cache = <&L2>; -+ reg = <0x1>; -+ }; -+ }; -+ -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -0,0 +1,95 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, -+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs -+ * -+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+#include <dt-bindings/interrupt-controller/irq.h> -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+#include "skeleton.dtsi" -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ chipcommonA { -+ compatible = "simple-bus"; -+ ranges = <0x00000000 0x18000000 0x00001000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ uart0: serial@0300 { -+ compatible = "ns16550"; -+ reg = <0x0300 0x100>; -+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; -+ clock-frequency = <100000000>; -+ status = "disabled"; -+ }; -+ -+ uart1: serial@0400 { -+ compatible = "ns16550"; -+ reg = <0x0400 0x100>; -+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; -+ clock-frequency = <100000000>; -+ status = "disabled"; -+ }; -+ }; -+ -+ mpcore { -+ compatible = "simple-bus"; -+ ranges = <0x00000000 0x19020000 0x00003000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ scu@0000 { -+ compatible = "arm,cortex-a9-scu"; -+ reg = <0x0000 0x100>; -+ }; -+ -+ timer@0200 { -+ compatible = "arm,cortex-a9-global-timer"; -+ reg = <0x0200 0x100>; -+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_periph>; -+ }; -+ -+ local-timer@0600 { -+ compatible = "arm,cortex-a9-twd-timer"; -+ reg = <0x0600 0x100>; -+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_periph>; -+ }; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,cortex-a9-gic"; -+ #interrupt-cells = <3>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, -+ <0x0100 0x100>; -+ }; -+ -+ L2: cache-controller@2000 { -+ compatible = "arm,pl310-cache"; -+ reg = <0x2000 0x1000>; -+ cache-unified; -+ cache-level = <2>; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* As long as we do not have a real clock driver us this -+ * fixed clock */ -+ clk_periph: periph { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/include/debug/bcm53xx.S -@@ -0,0 +1,19 @@ -+/* -+ * Macros used for EARLY_PRINTK, in low-level UART debug console -+ * -+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+#define BCM53XX_UART1_PHYS 0x18000300 -+#define BCM53XX_UART1_VIRT 0xf1000300 -+#define BCM53XX_UART1_SH 0 -+ -+ .macro addruart, rp, rv, tmp -+ ldr \rp, =BCM53XX_UART1_PHYS @ MMU off, Physical -+ ldr \rv, =BCM53XX_UART1_VIRT @ MMU on, Virtual -+ .endm -+ -+#define UART_SHIFT BCM53XX_UART1_SH -+#include <asm/hardware/debug-8250.S> ---- /dev/null -+++ b/arch/arm/mach-bcm53xx/Kconfig -@@ -0,0 +1,25 @@ -+config ARCH_BCM_5301X -+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 -+ depends on MMU -+ select ARM_GIC -+ select CACHE_L2X0 -+ select HAVE_ARM_SCU if SMP -+ select HAVE_ARM_TWD if SMP -+ select HAVE_SMP -+ select COMMON_CLK -+ select GENERIC_CLOCKEVENTS -+ select ARM_GLOBAL_TIMER -+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK -+ select MIGHT_HAVE_PCI -+ help -+ Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. -+ -+ This is a network SoC line mostly used in home routers and -+ wifi access points. -+ This inclused the following SoC: BCM53010, BCM53011, BCM53012, -+ BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707, -+ BCM4708 and BCM4709. -+ -+ Do not confuse this with the BCM4760 which is a totally -+ different SoC or with the older BCM47XX and BCM53XX based -+ network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx ---- /dev/null -+++ b/arch/arm/mach-bcm53xx/Makefile -@@ -0,0 +1 @@ -+obj-y += bcm53xx.o ---- /dev/null -+++ b/arch/arm/mach-bcm53xx/bcm53xx.c -@@ -0,0 +1,70 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * -+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+#include <linux/of_platform.h> -+#include <linux/clocksource.h> -+#include <linux/clk-provider.h> -+#include <asm/hardware/cache-l2x0.h> -+ -+#include <asm/mach/arch.h> -+#include <asm/siginfo.h> -+#include <asm/signal.h> -+ -+ -+static bool first_fault = true; -+ -+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, -+ struct pt_regs *regs) -+{ -+ if (fsr == 0x1c06 && first_fault) { -+ first_fault = false; -+ -+ /* -+ * These faults with code 0x1c06 happens for no good reason, -+ * possibly left over from the CFE boot loader. -+ */ -+ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", -+ addr, fsr); -+ -+ /* Returning non-zero causes fault display and panic */ -+ return 0; -+ } -+ -+ /* Others should cause a fault */ -+ return 1; -+} -+ -+static void __init bcm5301x_init_early(void) -+{ -+ /* Install our hook */ -+ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, -+ "imprecise external abort"); -+} -+ -+static void __init bcm5301x_timer_init(void) -+{ -+ of_clk_init(NULL); -+ clocksource_of_init(); -+} -+ -+static void __init bcm5301x_dt_init(void) -+{ -+ l2x0_of_init(0, ~0UL); -+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -+} -+ -+static const char __initconst *bcm5301x_dt_compat[] = { -+ "brcm,bcm4708", -+ NULL, -+}; -+ -+DT_MACHINE_START(BCM5301X, "BCM5301X") -+ .init_early = bcm5301x_init_early, -+ .init_time = bcm5301x_timer_init, -+ .init_machine = bcm5301x_dt_init, -+ .dt_compat = bcm5301x_dt_compat, -+MACHINE_END diff --git a/target/linux/bcm53xx/patches-3.10/052-bcm53xx-register-bcma-bus.patch b/target/linux/bcm53xx/patches-3.10/052-bcm53xx-register-bcma-bus.patch deleted file mode 100644 index aa2414df84..0000000000 --- a/target/linux/bcm53xx/patches-3.10/052-bcm53xx-register-bcma-bus.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 22b90bcf616578abe09845c72317ce53312f7faf Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Sat, 25 Jan 2014 17:03:07 +0100 -Subject: [PATCH 8/8] ARM: BCM5301X: register bcma bus - ---- - arch/arm/boot/dts/bcm4708.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/arch/arm/boot/dts/bcm4708.dtsi -+++ b/arch/arm/boot/dts/bcm4708.dtsi -@@ -31,4 +31,47 @@ - }; - }; - -+ aix@18000000 { -+ compatible = "brcm,bus-aix"; -+ reg = <0x18000000 0x1000>; -+ ranges = <0x00000000 0x18000000 0x00100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ usb2@0 { -+ compatible = "brcm,northstar-usb2"; -+ reg = <0x18021000 0x1000>; -+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ usb3@0 { -+ compatible = "brcm,northstar-usb3"; -+ reg = <0x18023000 0x1000>; -+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ gmac@0 { -+ compatible = "brcm,northstar-gmac"; -+ reg = <0x18024000 0x1000>; -+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ gmac@1 { -+ compatible = "brcm,northstar-gmac"; -+ reg = <0x18025000 0x1000>; -+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ gmac@2 { -+ compatible = "brcm,northstar-gmac"; -+ reg = <0x18026000 0x1000>; -+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ gmac@3 { -+ compatible = "brcm,northstar-gmac"; -+ reg = <0x18027000 0x1000>; -+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; - }; diff --git a/target/linux/bcm53xx/patches-3.10/111-bcma-register-bcma-as-device-tree-driver.patch b/target/linux/bcm53xx/patches-3.10/111-bcma-register-bcma-as-device-tree-driver.patch deleted file mode 100644 index b15c012ab5..0000000000 --- a/target/linux/bcm53xx/patches-3.10/111-bcma-register-bcma-as-device-tree-driver.patch +++ /dev/null @@ -1,115 +0,0 @@ -From c046c19fc8f1af7cf253fea5b0253143c159948a Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Mon, 6 Jan 2014 23:29:15 +0100 -Subject: [PATCH 6/8] bcma: register bcma as device tree driver - -This driver is used by the bcm53xx ARM SoC code.Now it is possible to -give the address of the chipcommon core in device tree. - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/bcma/host_soc.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ - include/linux/bcma/bcma.h | 2 ++ - 2 files changed, 72 insertions(+) - ---- a/drivers/bcma/host_soc.c -+++ b/drivers/bcma/host_soc.c -@@ -7,6 +7,9 @@ - - #include "bcma_private.h" - #include "scan.h" -+#include <linux/slab.h> -+#include <linux/module.h> -+#include <linux/of_address.h> - #include <linux/bcma/bcma.h> - #include <linux/bcma/bcma_soc.h> - -@@ -173,6 +176,7 @@ int __init bcma_host_soc_register(struct - /* Host specific */ - bus->hosttype = BCMA_HOSTTYPE_SOC; - bus->ops = &bcma_host_soc_ops; -+ bus->host_pdev = NULL; - - /* Register */ - err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips); -@@ -181,3 +185,69 @@ int __init bcma_host_soc_register(struct - - return err; - } -+ -+#ifdef CONFIG_OF -+static int bcma_host_soc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct bcma_bus *bus; -+ int err; -+ -+ /* Alloc */ -+ bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL); -+ if (!bus) -+ return -ENOMEM; -+ -+ /* Map MMIO */ -+ bus->mmio = of_iomap(np, 0); -+ if (!bus->mmio) -+ return -ENOMEM; -+ -+ /* Host specific */ -+ bus->hosttype = BCMA_HOSTTYPE_SOC; -+ bus->ops = &bcma_host_soc_ops; -+ bus->host_pdev = pdev; -+ -+ /* Register */ -+ err = bcma_bus_register(bus); -+ if (err) -+ goto err_unmap_mmio; -+ -+ platform_set_drvdata(pdev, bus); -+ -+ return err; -+ -+err_unmap_mmio: -+ iounmap(bus->mmio); -+ return err; -+} -+ -+static int bcma_host_soc_remove(struct platform_device *pdev) -+{ -+ struct bcma_bus *bus = platform_get_drvdata(pdev); -+ -+ bcma_bus_unregister(bus); -+ iounmap(bus->mmio); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcma_host_soc_of_match[] = { -+ { .compatible = "brcm,bus-aix", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match); -+ -+static struct platform_driver bcma_host_soc_driver = { -+ .driver = { -+ .name = "bcma-host-soc", -+ .owner = THIS_MODULE, -+ .of_match_table = bcma_host_soc_of_match, -+ }, -+ .probe = bcma_host_soc_probe, -+ .remove = bcma_host_soc_remove, -+}; -+module_platform_driver(bcma_host_soc_driver); -+#endif /* CONFIG_OF */ ---- a/include/linux/bcma/bcma.h -+++ b/include/linux/bcma/bcma.h -@@ -322,6 +322,8 @@ struct bcma_bus { - struct pci_dev *host_pci; - /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */ - struct sdio_func *host_sdio; -+ /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */ -+ struct platform_device *host_pdev; - }; - - struct bcma_chipinfo chipinfo; diff --git a/target/linux/bcm53xx/patches-3.10/112-bcma-get-irqs-from-dt.patch b/target/linux/bcm53xx/patches-3.10/112-bcma-get-irqs-from-dt.patch deleted file mode 100644 index 7c6cbbd364..0000000000 --- a/target/linux/bcm53xx/patches-3.10/112-bcma-get-irqs-from-dt.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 06a21484198df9a4d34fe5062878d3bf4fc14340 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Thu, 9 Jan 2014 19:40:14 +0100 -Subject: [PATCH 7/8] bcma: get irqs from dt - ---- - drivers/bcma/main.c | 42 +++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 41 insertions(+), 1 deletion(-) - ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -10,6 +10,8 @@ - #include <linux/platform_device.h> - #include <linux/bcma/bcma.h> - #include <linux/slab.h> -+#include <linux/of_irq.h> -+#include <linux/of_address.h> - - MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); - MODULE_LICENSE("GPL"); -@@ -111,6 +113,38 @@ static void bcma_release_core_dev(struct - kfree(core); - } - -+static struct device_node *bcma_of_find_child_device(struct platform_device *parent, -+ struct bcma_device *core) -+{ -+ struct device_node *node; -+ u64 size; -+ const __be32 *reg; -+ -+ if (!parent || !parent->dev.of_node) -+ return NULL; -+ -+ for_each_child_of_node(parent->dev.of_node, node) { -+ reg = of_get_address(node, 0, &size, 0); -+ if (!reg) -+ continue; -+ if (be32_to_cpup(reg) == core->addr) -+ return node; -+ } -+ return NULL; -+} -+ -+static void bcma_of_fill_device(struct platform_device *parent, -+ struct bcma_device *core) -+{ -+ struct device_node *node; -+ -+ node = bcma_of_find_child_device(parent, core); -+ if (!node) -+ return; -+ core->dev.of_node = node; -+ core->irq = irq_of_parse_and_map(node, 0); -+} -+ - static int bcma_register_cores(struct bcma_bus *bus) - { - struct bcma_device *core; -@@ -146,7 +180,13 @@ static int bcma_register_cores(struct bc - break; - case BCMA_HOSTTYPE_SOC: - core->dev.dma_mask = &core->dev.coherent_dma_mask; -- core->dma_dev = &core->dev; -+ if (bus->host_pdev) { -+ core->dma_dev = &bus->host_pdev->dev; -+ core->dev.parent = &bus->host_pdev->dev; -+ bcma_of_fill_device(bus->host_pdev, core); -+ } else { -+ core->dma_dev = &core->dev; -+ } - break; - case BCMA_HOSTTYPE_SDIO: - break; diff --git a/target/linux/bcm53xx/patches-3.10/202-bgmac-make-bgmac-work-on-systems-without-nvram.patch b/target/linux/bcm53xx/patches-3.10/202-bgmac-make-bgmac-work-on-systems-without-nvram.patch deleted file mode 100644 index c23e205218..0000000000 --- a/target/linux/bcm53xx/patches-3.10/202-bgmac-make-bgmac-work-on-systems-without-nvram.patch +++ /dev/null @@ -1,73 +0,0 @@ -These are some hackish patches to make the Ethernet driver work somehow -on this arm core. -The flash driver is not working, so we removed the nvram reading, this -should be changed after we have a flash driver. -The mdelay(1) is a ugly workaround for this arm chip, this seams to be a dma problem. - -The PHY says it is not connected by default, just ignore it. - ---- a/drivers/net/ethernet/broadcom/Kconfig -+++ b/drivers/net/ethernet/broadcom/Kconfig -@@ -132,7 +132,7 @@ config BNX2X_SRIOV - - config BGMAC - tristate "BCMA bus GBit core support" -- depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX -+ depends on BCMA_HOST_SOC && HAS_DMA - select PHYLIB - ---help--- - This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus. ---- a/drivers/net/ethernet/broadcom/bgmac.c -+++ b/drivers/net/ethernet/broadcom/bgmac.c -@@ -17,7 +17,11 @@ - #include <linux/interrupt.h> - #include <linux/dma-mapping.h> - #include <linux/platform_data/b53.h> -+#ifdef CONFIG_BCM47XX - #include <bcm47xx_nvram.h> -+#else -+#define bcm47xx_nvram_getenv(a, b, c) -1 -+#endif - - static const struct bcma_device_id bgmac_bcma_tbl[] = { - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), -@@ -1452,7 +1456,7 @@ static int bgmac_probe(struct bcma_devic - int err; - - /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ -- if (core->core_unit > 1) { -+ if (core->core_unit > 0) { - pr_err("Unsupported core_unit %d\n", core->core_unit); - return -ENOTSUPP; - } -@@ -1487,8 +1491,7 @@ static int bgmac_probe(struct bcma_devic - } - bgmac->cmn = core->bus->drv_gmac_cmn.core; - -- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : -- sprom->et0phyaddr; -+ bgmac->phyaddr = BGMAC_PHY_NOREGS; // core->core_unit ? sprom->et1phyaddr : sprom->et0phyaddr; - bgmac->phyaddr &= BGMAC_PHY_MASK; - if (bgmac->phyaddr == BGMAC_PHY_MASK) { - bgmac_err(bgmac, "No PHY found\n"); -@@ -1540,8 +1543,7 @@ static int bgmac_probe(struct bcma_devic - /* TODO: reset the external phy. Specs are needed */ - bgmac_phy_reset(bgmac); - -- bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & -- BGMAC_BFL_ENETROBO); -+ bgmac->has_robosw = 1; - if (bgmac->has_robosw) - bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); - ---- a/drivers/net/phy/phy_device.c -+++ b/drivers/net/phy/phy_device.c -@@ -814,7 +814,7 @@ int genphy_update_link(struct phy_device - return status; - - if ((status & BMSR_LSTATUS) == 0) -- phydev->link = 0; -+ phydev->link = 1; - else - phydev->link = 1; - |