diff options
Diffstat (limited to 'target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch')
| -rw-r--r-- | target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch b/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch new file mode 100644 index 0000000000..deda80985d --- /dev/null +++ b/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch @@ -0,0 +1,56 @@ +From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea <claudiu.beznea@microchip.com> +Date: Mon, 19 Jul 2021 11:03:17 +0300 +Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's + master clock + +Add register definitions for SAMA7G5's master clock. These would be +also used by architecture specific power saving code. + +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> +Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com +--- + include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h +index a4f82e836a7c..ccb3f034bfa9 100644 +--- a/include/linux/clk/at91_pmc.h ++++ b/include/linux/clk/at91_pmc.h +@@ -137,6 +137,32 @@ + #define AT91_PMC_PLLADIV2_ON (1 << 12) + #define AT91_PMC_H32MXDIV BIT(24) + ++#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ ++#define AT91_PMC_MCR_V2_ID_MSK (0xF) ++#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) ++#define AT91_PMC_MCR_V2_CMD (1 << 7) ++#define AT91_PMC_MCR_V2_DIV (7 << 8) ++#define AT91_PMC_MCR_V2_DIV1 (0 << 8) ++#define AT91_PMC_MCR_V2_DIV2 (1 << 8) ++#define AT91_PMC_MCR_V2_DIV4 (2 << 8) ++#define AT91_PMC_MCR_V2_DIV8 (3 << 8) ++#define AT91_PMC_MCR_V2_DIV16 (4 << 8) ++#define AT91_PMC_MCR_V2_DIV32 (5 << 8) ++#define AT91_PMC_MCR_V2_DIV64 (6 << 8) ++#define AT91_PMC_MCR_V2_DIV3 (7 << 8) ++#define AT91_PMC_MCR_V2_CSS (0x1F << 16) ++#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) ++#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) ++#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) ++#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) ++#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) ++#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) ++#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) ++#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) ++#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) ++#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) ++#define AT91_PMC_MCR_V2_EN (1 << 28) ++ + #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ + + #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ +-- +2.32.0 + |