diff options
Diffstat (limited to 'package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch')
| -rw-r--r-- | package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch b/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch new file mode 100644 index 0000000000..102363066c --- /dev/null +++ b/package/mac80211/patches/586-ath9k-fix-PLL-initialization-for-AR9550.patch @@ -0,0 +1,75 @@ +From d211df2956ae9d696bb0cab985426e0d236544b8 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos <juhosg@openwrt.org> +Date: Mon, 2 Jul 2012 17:16:00 +0200 +Subject: [PATCH 17/20] ath9k: fix PLL initialization for AR9550 + +Signed-off-by: Gabor Juhos <juhosg@openwrt.org> +Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> +--- + drivers/net/wireless/ath/ath9k/hw.c | 27 +++++++++++++++++++-------- + 1 files changed, 19 insertions(+), 8 deletions(-) + +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -861,7 +861,7 @@ static void ath9k_hw_init_pll(struct ath + /* program BB PLL phase_shift */ + REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, + AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); +- } else if (AR_SREV_9340(ah)) { ++ } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { + u32 regval, pll2_divint, pll2_divfrac, refdiv; + + REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); +@@ -875,9 +875,15 @@ static void ath9k_hw_init_pll(struct ath + pll2_divfrac = 0x1eb85; + refdiv = 3; + } else { +- pll2_divint = 88; +- pll2_divfrac = 0; +- refdiv = 5; ++ if (AR_SREV_9340(ah)) { ++ pll2_divint = 88; ++ pll2_divfrac = 0; ++ refdiv = 5; ++ } else { ++ pll2_divint = 0x11; ++ pll2_divfrac = 0x26666; ++ refdiv = 1; ++ } + } + + regval = REG_READ(ah, AR_PHY_PLL_MODE); +@@ -890,8 +896,12 @@ static void ath9k_hw_init_pll(struct ath + udelay(100); + + regval = REG_READ(ah, AR_PHY_PLL_MODE); +- regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | +- (0x4 << 26) | (0x18 << 19); ++ if (AR_SREV_9340(ah)) ++ regval = (regval & 0x80071fff) | (0x1 << 30) | ++ (0x1 << 13) | (0x4 << 26) | (0x18 << 19); ++ else ++ regval = (regval & 0x80071fff) | (0x3 << 30) | ++ (0x1 << 13) | (0x4 << 26) | (0x60 << 19); + REG_WRITE(ah, AR_PHY_PLL_MODE, regval); + REG_WRITE(ah, AR_PHY_PLL_MODE, + REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); +@@ -902,7 +912,8 @@ static void ath9k_hw_init_pll(struct ath + + REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); + +- if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) ++ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || ++ AR_SREV_9550(ah)) + udelay(1000); + + /* Switch the core clock for ar9271 to 117Mhz */ +@@ -915,7 +926,7 @@ static void ath9k_hw_init_pll(struct ath + + REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); + +- if (AR_SREV_9340(ah)) { ++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { + if (ah->is_clk_25mhz) { + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); |