diff options
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/devices.c | 8 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c | 13 |
2 files changed, 19 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c index 05ce97765b..088d27a346 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c @@ -558,8 +558,10 @@ void __init ar71xx_add_device_eth(unsigned int id) break; case AR71XX_SOC_AR7242: - ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; - ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; + ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO | + RESET_MODULE_GE0_PHY; + ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO | + RESET_MODULE_GE1_PHY; pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 : ar724x_ddr_flush_ge0; pdata->set_pll = id ? ar724x_set_pll_ge1 @@ -580,6 +582,8 @@ void __init ar71xx_add_device_eth(unsigned int id) ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; /* fall through */ case AR71XX_SOC_AR7240: + ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY; + ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY; pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 : ar724x_ddr_flush_ge0; pdata->set_pll = id ? ar724x_set_pll_ge1 diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c index c1143161af..ce2af538cb 100644 --- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c +++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c @@ -433,9 +433,22 @@ static void ag71xx_hw_stop(struct ag71xx *ag) static void ag71xx_hw_init(struct ag71xx *ag) { struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 reset_mask = pdata->reset_bit; ag71xx_hw_stop(ag); + if (pdata->is_ar724x) { + u32 reset_phy = reset_mask; + + reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY; + reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY); + + ar71xx_device_stop(reset_phy); + mdelay(50); + ar71xx_device_start(reset_phy); + mdelay(200); + } + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); udelay(20); |