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authorAnsuel Smith <ansuelsmth@gmail.com>2021-07-06 01:21:46 +0200
committerHauke Mehrtens <hauke@hauke-m.de>2021-07-17 19:12:11 +0200
commit0f499372c05cd42fd6fd85c061a39ad49bccdbda (patch)
treecbe13b574bdebbd3c92883b703e5731e4a7f9ee8 /toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch
parentb71767d8e047b06668ca8b7b7922f6df238ab659 (diff)
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toolchain: add gcc 11 version
Add gcc 11 version. Same patches of gcc 10. Build tested on: ipq806x ipq807x Run tested on: ipq806x ipq807x Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [refresh patches] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch')
-rw-r--r--toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch20
1 files changed, 20 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch
new file mode 100644
index 0000000000..82ac013d30
--- /dev/null
+++ b/toolchain/gcc/patches/11.1.0/110-Fix-MIPS-PR-84790.patch
@@ -0,0 +1,20 @@
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.c
++++ b/gcc/config/mips/mips.c
+@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)