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| author | Nick Hainke <vincent@systemli.org> | 2022-04-18 15:04:25 +0200 |
|---|---|---|
| committer | David Bauer <mail@david-bauer.net> | 2022-04-30 16:31:32 +0200 |
| commit | e9431a8335658fd8bcb1c01b3c7e59bf0401196d (patch) | |
| tree | af09dc6c3f82d0ebe21eba17826434560537612a /target | |
| parent | dd58c12f0f404580785789c144d8548d1a945fe1 (diff) | |
| download | upstream-e9431a8335658fd8bcb1c01b3c7e59bf0401196d.tar.gz upstream-e9431a8335658fd8bcb1c01b3c7e59bf0401196d.tar.bz2 upstream-e9431a8335658fd8bcb1c01b3c7e59bf0401196d.zip | |
ipq40xx: fix ar40xx driver
This commit is completely based on the work of adron-s:
https://github.com/openwrt/openwrt/pull/4721#issuecomment-1101108651
The commit fixes the data corruption on TX packets. Packets are
transmitted, but their contents are replaced with zeros. This error is
caused by the lack of guard (50 ms) intervals between calibration phases.
This error is treated by adding mdelay(50) to the calibration function
code. In the original qca-ssda code [0], these mdelays were existing, but
in the ar41xx.c they are gone.
Tested on:
- Fritz!Box 4040
- Fritz!Box 7530
- Mikrotik SXTsq 5AC
- ZyXEL NBG6617
- [0] https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk/-/blob/NHSS.QSDK.11.4/src/init/ssdk_init.c#L2072
Suggested-by: Serhii Serhieiev <adron@mstnt.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Nick Hainke <vincent@systemli.org>
(cherry picked from commit ab7e53e5cce703c7a62efbe1d41fb94c2228a178)
[Deleted 5.10 from commit title]
Signed-off-by: Nick Hainke <vincent@systemli.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c b/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c index ca7f0ca350..545e3985ae 100644 --- a/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c +++ b/target/linux/ipq40xx/files/drivers/net/phy/ar40xx.c @@ -935,6 +935,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) */ mdelay(2); } + mdelay(50); /*check malibu psgmii calibration done end..*/ @@ -953,6 +954,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) /* Polling interval to check PSGMII PLL in ESS is ready */ mdelay(2); } + mdelay(50); /* check dakota psgmii calibration done end..*/ @@ -960,6 +962,7 @@ ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv) mdiobus_write(bus, 5, 0x1a, 0x3230); /* release phy psgmii RX 20bit */ mdiobus_write(bus, 5, 0x0, 0x005f); + mdelay(200); } static void |