bcm53xx: backport BCM5301X patches for SRAB

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>

5 files changed, 170 insertions, 1 deletions

diff --git a/target/linux/bcm53xx/patches-4.4/037-ARM-BCM5301X-Add-DT-entry-for-SPI-controller-and-NOR.patch b/target/linux/bcm53xx/patches-4.4/037-0001-ARM-BCM5301X-Add-DT-entry-for-SPI-controller-and-NOR.patch
index 4549396d2b..4549396d2b 100644
--- a/target/linux/bcm53xx/patches-4.4/037-ARM-BCM5301X-Add-DT-entry-for-SPI-controller-and-NOR.patch
+++ b/target/linux/bcm53xx/patches-4.4/037-0001-ARM-BCM5301X-Add-DT-entry-for-SPI-controller-and-NOR.patch
diff --git a/target/linux/bcm53xx/patches-4.4/130-ARM-BCM5301X-Enable-SPI-NOR-on-dual-flash-devices.patch b/target/linux/bcm53xx/patches-4.4/037-0002-ARM-BCM5301X-Enable-SPI-NOR-on-dual-flash-devices.patch
index c9bb9af479..f15cfb79c4 100644
--- a/target/linux/bcm53xx/patches-4.4/130-ARM-BCM5301X-Enable-SPI-NOR-on-dual-flash-devices.patch
+++ b/target/linux/bcm53xx/patches-4.4/037-0002-ARM-BCM5301X-Enable-SPI-NOR-on-dual-flash-devices.patch
@@ -1,5 +1,6 @@
+From 5f79985dcfec73d7a09ed99c40c28b64552518fe Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
-Date: Wed, 27 Apr 2016 08:58:01 +0200
+Date: Wed, 27 Apr 2016 09:05:03 +0200
 Subject: [PATCH] ARM: BCM5301X: Enable SPI-NOR on dual flash devices
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
@@ -13,7 +14,14 @@ However there are also devices with two flash memories:
 On such devices we still need SPI-NOR e.g. to access NVRAM data.
 
 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
 ---
+ arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ++++
+ arch/arm/boot/dts/bcm4708-netgear-r6250.dts       | 4 ++++
+ arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts    | 4 ++++
+ arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 4 ++++
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts     | 4 ++++
+ 5 files changed, 20 insertions(+)
 
 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
 +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
diff --git a/target/linux/bcm53xx/patches-4.4/038-0001-ARM-dts-Enable-SRAB-switch-and-GMACs-on-5301x-DTS.patch b/target/linux/bcm53xx/patches-4.4/038-0001-ARM-dts-Enable-SRAB-switch-and-GMACs-on-5301x-DTS.patch
new file mode 100644
index 0000000000..0210f7e2aa
--- /dev/null
+++ b/target/linux/bcm53xx/patches-4.4/038-0001-ARM-dts-Enable-SRAB-switch-and-GMACs-on-5301x-DTS.patch
@@ -0,0 +1,63 @@
+From 59f0ce1a3ebb9288fc8c1400aa503e923621161e Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Mon, 23 May 2016 16:38:00 -0700
+Subject: [PATCH 1/3] ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
+
+Add the Switch Register Access Block which is a special piece of
+hardware allowing us to perform indirect read/writes towards the
+integrated BCM5301X Ethernet switch.
+
+We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi
+bus node to get proper binding between the BCMA instantiated core and
+the Device Tree nodes. We will need that to be able to reference
+Ethernet Device Tree nodes in a future patch adding the switch ports
+layout.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -239,6 +239,22 @@
+ 				status = "disabled";
+ 			};
+ 		};
++
++		gmac0: ethernet@24000 {
++			reg = <0x24000 0x800>;
++		};
++
++		gmac1: ethernet@25000 {
++			reg = <0x25000 0x800>;
++		};
++
++		gmac2: ethernet@26000 {
++			reg = <0x26000 0x800>;
++		};
++
++		gmac3: ethernet@27000 {
++			reg = <0x27000 0x800>;
++		};
+ 	};
+ 
+ 	lcpll0: lcpll0@1800c100 {
+@@ -260,6 +276,17 @@
+ 				     "sata2";
+ 	};
+ 
++	srab: srab@18007000 {
++		compatible = "brcm,bcm5301x-srab";
++		reg = <0x18007000 0x1000>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		status = "disabled";
++
++		/* ports are defined in board DTS */
++	};
++
+ 	nand: nand@18028000 {
+ 		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+ 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
diff --git a/target/linux/bcm53xx/patches-4.4/038-0002-ARM-dts-BCM5301X-Add-SRAB-interrupts.patch b/target/linux/bcm53xx/patches-4.4/038-0002-ARM-dts-BCM5301X-Add-SRAB-interrupts.patch
new file mode 100644
index 0000000000..95375fc338
--- /dev/null
+++ b/target/linux/bcm53xx/patches-4.4/038-0002-ARM-dts-BCM5301X-Add-SRAB-interrupts.patch
@@ -0,0 +1,38 @@
+From 2cd0c0202f138fa95b3fbb027e87b191ad0b1884 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Tue, 24 May 2016 11:41:58 -0700
+Subject: [PATCH 2/3] ARM: dts: BCM5301X: Add SRAB interrupts
+
+Add interrupt mapping for the Switch Register Access Block. Only 12
+interrupts are usable at the moment even though up to 32 are dedicated
+to the SRAB.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -153,6 +153,21 @@
+ 			/* ChipCommon */
+ 			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ 
++			/* Switch Register Access Block */
++			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
++			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++
+ 			/* PCIe Controller 0 */
+ 			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ 			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/target/linux/bcm53xx/patches-4.4/038-0003-ARM-dts-BCM5310x-Enable-switch-ports-on-SmartRG-SR40.patch b/target/linux/bcm53xx/patches-4.4/038-0003-ARM-dts-BCM5310x-Enable-switch-ports-on-SmartRG-SR40.patch
new file mode 100644
index 0000000000..7ddb99bb33
--- /dev/null
+++ b/target/linux/bcm53xx/patches-4.4/038-0003-ARM-dts-BCM5310x-Enable-switch-ports-on-SmartRG-SR40.patch
@@ -0,0 +1,60 @@
+From 2df1808dc0e2b5358e13beb95192b15200017776 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Wed, 25 May 2016 16:55:35 -0700
+Subject: [PATCH 3/3] ARM: dts: BCM5310x: Enable switch ports on SmartRG
+ SR400AC
+
+Define the port mapping for the SmartRG SR400ACE device.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 40 +++++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+@@ -126,3 +126,43 @@
+ &spi_nor {
+ 	status = "okay";
+ };
++
++&srab {
++	status = "okay";
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			reg = <0>;
++			label = "lan4";
++		};
++
++		port@1 {
++			reg = <1>;
++			label = "lan3";
++		};
++
++		port@2 {
++			reg = <2>;
++			label = "lan2";
++		};
++
++		port@3 {
++			reg = <3>;
++			label = "lan1";
++		};
++
++		port@4 {
++			reg = <4>;
++			label = "wan";
++		};
++
++		port@5 {
++			reg = <5>;
++			label = "cpu";
++			ethernet = <&gmac0>;
++		};
++	};
++};