diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2014-05-04 23:26:20 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2014-05-04 23:26:20 +0000 |
| commit | b4d93a52cfdc75fde4e56979f6749977197effca (patch) | |
| tree | 574ce417054170112392e0b4524d2a56ac81c9a4 /target/linux | |
| parent | 32a806cf8aed07d0f04e06a1d2f57d70eff7d0e8 (diff) | |
| download | upstream-b4d93a52cfdc75fde4e56979f6749977197effca.tar.gz upstream-b4d93a52cfdc75fde4e56979f6749977197effca.tar.bz2 upstream-b4d93a52cfdc75fde4e56979f6749977197effca.zip | |
ar71xx/ath9k: fix reading the WMAC revision on AR953x (fixes #15581)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 40695
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 05ef22bdb5..00458d2843 100644 --- a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -168,7 +168,25 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. platform_device_register(&ath79_uart_device); --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c -@@ -149,6 +149,24 @@ static void ar934x_wmac_setup(void) +@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void) + return -ETIMEDOUT; + } + +-static int ar933x_r1_get_wmac_revision(void) ++static int ar93xx_get_soc_revision(void) + { + return ath79_soc_rev; + } +@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi + ath79_wmac_data.is_clk_25mhz = true; + + if (ath79_soc_rev == 1) +- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + + ath79_wmac_data.external_reset = ar933x_wmac_reset; + } +@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void) ath79_wmac_data.is_clk_25mhz = true; } @@ -188,12 +206,14 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; ++ ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; +} + static void qca955x_wmac_setup(void) { u32 t; -@@ -366,6 +384,8 @@ void __init ath79_register_wmac(u8 *cal_ +@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_ ar933x_wmac_setup(); else if (soc_is_ar934x()) ar934x_wmac_setup(); |