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| author | Daniel González Cabanelas <dgcbueu@gmail.com> | 2021-04-04 23:06:46 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2021-04-18 12:04:33 +0200 |
| commit | d530ff37bf3343ed40d02d88122f2f3ca44a9d8c (patch) | |
| tree | a957332cc4d8b5c104dc3eb7a4d9fbe78fa0e5fd /target/linux | |
| parent | f965235bb5b74bbfc9f048223716c123669688e3 (diff) | |
| download | upstream-d530ff37bf3343ed40d02d88122f2f3ca44a9d8c.tar.gz upstream-d530ff37bf3343ed40d02d88122f2f3ca44a9d8c.tar.bz2 upstream-d530ff37bf3343ed40d02d88122f2f3ca44a9d8c.zip | |
mvebu: armada 370: dts: fix the crypto engine
The crypto engine in Armada 370 SoCs is currently broken. It can be
checked installing the required packages for testing openssl with hw
acceleration:
opkg install openssl-util
opkg install kmod-cryptodev
opkg install libopenssl-devcrypto
After configuring /etc/ssl/openssl.cnf to let openssl use the crypto
engine for digest operations, and performing some checksums..
md5sum 10M-file.bin
openssl md5 10M-file.bin
...we can see they don't match.
There might be an alignment or size constraint issue caused by the
idle-sram area.
Use the whole crypto sram and disable the idle-sram area to fix it. Also
disable the idle support by adding the broken-idle property to prevent
accessing the disabled idle-sram.
We don't care about disabling the idle support since it is already broken
in Armada 370 causing a huge performance loss because it disables
permanently the L2 cache. This was reported in the Openwrt forum and
elsewhere by Debian users with different board models.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
(cherry picked from commit 2e1ebe96c61424d0829bb1c8b5ec44aaa8bea8af)
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch | 29 | ||||
| -rw-r--r-- | target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch | 29 |
2 files changed, 58 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch new file mode 100644 index 0000000000..19378870ef --- /dev/null +++ b/target/linux/mvebu/patches-5.10/317-armada-370-dts-fix-crypto-engine.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -234,7 +234,7 @@ + clocks = <&gateclk 23>; + clock-names = "cesa0"; + marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x7e0>; ++ marvell,crypto-sram-size = <0x800>; + }; + }; + +@@ -255,12 +255,17 @@ + * cpuidle workaround. + */ + idle-sram@0 { ++ status = "disabled"; + reg = <0x0 0x20>; + }; + }; + }; + }; + ++&coherencyfab { ++ broken-idle; ++}; ++ + /* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. diff --git a/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch new file mode 100644 index 0000000000..19378870ef --- /dev/null +++ b/target/linux/mvebu/patches-5.4/320-armada-370-dts-fix-crypto-engine.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -234,7 +234,7 @@ + clocks = <&gateclk 23>; + clock-names = "cesa0"; + marvell,crypto-srams = <&crypto_sram>; +- marvell,crypto-sram-size = <0x7e0>; ++ marvell,crypto-sram-size = <0x800>; + }; + }; + +@@ -255,12 +255,17 @@ + * cpuidle workaround. + */ + idle-sram@0 { ++ status = "disabled"; + reg = <0x0 0x20>; + }; + }; + }; + }; + ++&coherencyfab { ++ broken-idle; ++}; ++ + /* + * Default UART pinctrl setting without RTS/CTS, can be overwritten on + * board level if a different configuration is used. |