diff options
| author | John Crispin <john@openwrt.org> | 2014-11-24 19:12:35 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2014-11-24 19:12:35 +0000 |
| commit | 41f9765acd83ab4d021408b872e1a541f80378ba (patch) | |
| tree | fdf04b12c86e3635215f397efa4c3c1902fa4d08 /target/linux | |
| parent | 5f51cfcf55e2c8de3d75daeefe8be5b75eb839ae (diff) | |
| download | upstream-41f9765acd83ab4d021408b872e1a541f80378ba.tar.gz upstream-41f9765acd83ab4d021408b872e1a541f80378ba.tar.bz2 upstream-41f9765acd83ab4d021408b872e1a541f80378ba.zip | |
ralink: add proper reset of pci core
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 43370
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/ramips/patches-3.14/999-pci-reset.patch | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.14/999-pci-reset.patch b/target/linux/ramips/patches-3.14/999-pci-reset.patch new file mode 100644 index 0000000000..8e8589015b --- /dev/null +++ b/target/linux/ramips/patches-3.14/999-pci-reset.patch @@ -0,0 +1,29 @@ +Index: linux-3.14.18/arch/mips/ralink/reset.c +=================================================================== +--- linux-3.14.18.orig/arch/mips/ralink/reset.c 2014-11-23 00:32:23.268612766 +0100 ++++ linux-3.14.18/arch/mips/ralink/reset.c 2014-11-23 01:13:46.850117349 +0100 +@@ -18,8 +18,10 @@ + #include <asm/mach-ralink/ralink_regs.h> + + /* Reset Control */ +-#define SYSC_REG_RESET_CTRL 0x034 +-#define RSTCTL_RESET_SYSTEM BIT(0) ++#define SYSC_REG_RESET_CTRL 0x034 ++ ++#define RSTCTL_RESET_PCI BIT(26) ++#define RSTCTL_RESET_SYSTEM BIT(0) + + static int ralink_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +@@ -83,6 +85,11 @@ + + static void ralink_restart(char *command) + { ++ if (IS_ENABLED(CONFIG_PCI)) { ++ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL); ++ mdelay(50); ++ } ++ + local_irq_disable(); + rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); + unreachable(); |