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| author | Zoltan Herpai <wigyori@uid0.hu> | 2014-02-05 08:42:28 +0000 |
|---|---|---|
| committer | Zoltan Herpai <wigyori@uid0.hu> | 2014-02-05 08:42:28 +0000 |
| commit | c957af0a0f6a2c45b9b3c84f45f4a3aa44d293c6 (patch) | |
| tree | f8e3bda571dab7f80fdd240541ed8bd1d39b179e /target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch | |
| parent | 66543935db1d7eab23fc43b381e56dbd4424b499 (diff) | |
| download | upstream-c957af0a0f6a2c45b9b3c84f45f4a3aa44d293c6.tar.gz upstream-c957af0a0f6a2c45b9b3c84f45f4a3aa44d293c6.tar.bz2 upstream-c957af0a0f6a2c45b9b3c84f45f4a3aa44d293c6.zip | |
sunxi: initial 3.13 support
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
SVN-Revision: 39471
Diffstat (limited to 'target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch b/target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch new file mode 100644 index 0000000000..92f2efafb4 --- /dev/null +++ b/target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch @@ -0,0 +1,95 @@ +From f88dc0623908b574d9dcdae8815ccd0829fc6828 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Tue, 24 Sep 2013 11:10:41 +0300 +Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI + +The A31 has a reset controller IP that maintains a few other IPs in +reset, among which we can find the UARTs, high speed timers or the I2C. +Now that we have support for them, add the reset controllers to the DTSI. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Acked-by: Philipp Zabel <p.zabel@pengutronix.de> +--- + arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index 7f5878c..97966b0 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -212,6 +212,24 @@ + }; + }; + ++ ahb1_rst: reset@01c202c0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-ahb1-reset"; ++ reg = <0x01c202c0 0xc>; ++ }; ++ ++ apb1_rst: reset@01c202d0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ reg = <0x01c202d0 0x4>; ++ }; ++ ++ apb2_rst: reset@01c202d8 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ reg = <0x01c202d8 0x4>; ++ }; ++ + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0xa0>; +@@ -235,6 +253,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 16>; ++ resets = <&apb2_rst 16>; + status = "disabled"; + }; + +@@ -245,6 +264,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 17>; ++ resets = <&apb2_rst 17>; + status = "disabled"; + }; + +@@ -255,6 +275,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 18>; ++ resets = <&apb2_rst 18>; + status = "disabled"; + }; + +@@ -265,6 +286,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 19>; ++ resets = <&apb2_rst 19>; + status = "disabled"; + }; + +@@ -275,6 +297,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 20>; ++ resets = <&apb2_rst 20>; + status = "disabled"; + }; + +@@ -285,6 +308,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 21>; ++ resets = <&apb2_rst 21>; + status = "disabled"; + }; + +-- +1.8.5.1 + |