sunxi: deprecate 3.12 support

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

SVN-Revision: 39780

1 files changed, 0 insertions, 198 deletions

diff --git a/target/linux/sunxi/patches-3.12/107-dt-sun5i-add-mod0-clk.patch b/target/linux/sunxi/patches-3.12/107-dt-sun5i-add-mod0-clk.patch
deleted file mode 100644
index 63fbdd1c70..0000000000
--- a/target/linux/sunxi/patches-3.12/107-dt-sun5i-add-mod0-clk.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From 0ae543fe8ae8b9ea7166c39b00e977506eccdf4b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Wed, 4 Sep 2013 21:21:16 -0300
-Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks available on A10 and A13. The list
-has been constructed by looking at the Allwinner code release for A10S
-and A13.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 77 +++++++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi  | 77 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 154 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 86e06e4..82b5ce6 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -173,6 +173,83 @@
- 				"apb1_i2c2", "apb1_uart0", "apb1_uart1",
- 				"apb1_uart2", "apb1_uart3";
- 		};
-+
-+		nand: nand@01c20080 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20080 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ms: ms@01c20084 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20084 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc0: mmc0@01c20088 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20088 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc1: mmc1@01c2008c {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c2008c 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc2: mmc2@01c20090 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20090 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ts: ts@01c20098 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20098 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ss: ss@01c2009c {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c2009c 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi0: spi0@01c200a0 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a0 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi1: spi1@01c200a4 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a4 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi2: spi2@01c200a8 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a8 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ir0: ir0@01c200b0 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200b0 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
- 	};
- 
- 	soc@01c00000 {
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index cded3c7..938e6d3 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -170,6 +170,83 @@
- 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
- 				"apb1_i2c2", "apb1_uart1", "apb1_uart3";
- 		};
-+
-+		nand: nand@01c20080 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20080 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ms: ms@01c20084 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20084 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc0: mmc0@01c20088 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20088 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc1: mmc1@01c2008c {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c2008c 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		mmc2: mmc2@01c20090 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20090 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ts: ts@01c20098 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c20098 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ss: ss@01c2009c {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c2009c 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi0: spi0@01c200a0 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a0 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi1: spi1@01c200a4 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a4 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		spi2: spi2@01c200a8 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a8 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
-+
-+		ir0: ir0@01c200b0 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200b0 0x4>;
-+			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+		};
- 	};
- 
- 	soc@01c00000 {
--- 
-1.8.5.1
-