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| author | Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> | 2021-02-27 15:12:21 -0800 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2021-03-05 23:55:51 +0000 |
| commit | b4aad29a1d7ad77d67073c1c54b28c429c64ed9b (patch) | |
| tree | 54d0b355b70f9dc5c7486940954d75f3d5cb3fa0 /target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch | |
| parent | 38ba1f9b4ca4d263489a50cf078fd3c374bc4042 (diff) | |
| download | upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.tar.gz upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.tar.bz2 upstream-b4aad29a1d7ad77d67073c1c54b28c429c64ed9b.zip | |
ramips: add support for kernel 5.10
Enable testing kernel.
Delete upstreamed patches:
0098-disable_cm.patch can be dropped, upstream fixed CM handling.
Fix compile errors by using new kernel APIs.
Fix fuzz by manually editing patches to ensure the code goes in the
right place.
For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit
a307593a6 to keep the OpenWrt ralink driver operational.
Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693
and #3952.
Rename patches to follow the 3-digit classification from the OpenWrt
Developer Guide.
Run automatic quilt refresh.
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch')
| -rw-r--r-- | target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch new file mode 100644 index 0000000000..7c00d4c9ae --- /dev/null +++ b/target/linux/ramips/patches-5.10/330-fix-pci-init-mt7620.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/pci/pci-mt7620.c ++++ b/arch/mips/pci/pci-mt7620.c +@@ -32,6 +32,7 @@ + #define PPLL_CFG1 0x9c + + #define PPLL_DRV 0xa0 ++#define PPLL_LD BIT(23) + #define PDRV_SW_SET BIT(31) + #define LC_CKDRVPD BIT(19) + #define LC_CKDRVOHZ BIT(18) +@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); + mdelay(100); + +- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { +- dev_err(&pdev->dev, "MT7620 PPLL unlock\n"); ++ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { ++ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n"); + reset_control_assert(rstpcie0); + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); + return -1; |