ramips/mt7621: drop the timer recalibration patch

We've been carrying this patch for many years [1], in order to fix a timer
calibration issue on MT7621. Turns out, after retesting with a recent kernel
(Linux 5.10), the system works perfectly fine without it (no rcu_sched stalls
or inconsistent BogoMIPS values across CPUs).

Manually refreshed:
322-mt7621-fix-cpu-clk-add-clkdev.patch
323-mt7621-memory-detect.patch

[1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=6f4a903533361a2906a4d94ac6f597cd9c6c47bc

Suggested-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Tested-by: Donald Hoskins <grommish@gmail.com>
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>

1 files changed, 0 insertions, 87 deletions

diff --git a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch
deleted file mode 100644
index 08d5935eb0..0000000000
--- a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch
+++ /dev/null
@@ -1,87 +0,0 @@
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -9,6 +9,7 @@
- #include <linux/init.h>
- #include <linux/slab.h>
- #include <linux/sys_soc.h>
-+#include <linux/jiffies.h>
- 
- #include <asm/mipsregs.h>
- #include <asm/smp-ops.h>
-@@ -16,6 +17,7 @@
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7621.h>
- #include <asm/mips-boards/launch.h>
-+#include <asm/delay.h>
- 
- #include <pinmux.h>
- 
-@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core)
- 	return true;
- }
- 
-+#define LPS_PREC 8
-+/*
-+*  Re-calibration lpj(loop-per-jiffy).
-+*  (derived from kernel/calibrate.c)
-+*/
-+static int udelay_recal(void)
-+{
-+	unsigned int i, lpj = 0;
-+	unsigned long ticks, loopbit;
-+	int lps_precision = LPS_PREC;
-+
-+	lpj = (1<<12);
-+
-+	while ((lpj <<= 1) != 0) {
-+		/* wait for "start of" clock tick */
-+		ticks = jiffies;
-+		while (ticks == jiffies)
-+			/* nothing */;
-+
-+		/* Go .. */
-+		ticks = jiffies;
-+		__delay(lpj);
-+		ticks = jiffies - ticks;
-+		if (ticks)
-+			break;
-+	}
-+
-+	/*
-+	 * Do a binary approximation to get lpj set to
-+	 * equal one clock (up to lps_precision bits)
-+	 */
-+	lpj >>= 1;
-+	loopbit = lpj;
-+	while (lps_precision-- && (loopbit >>= 1)) {
-+		lpj |= loopbit;
-+		ticks = jiffies;
-+		while (ticks == jiffies)
-+			/* nothing */;
-+		ticks = jiffies;
-+		__delay(lpj);
-+		if (jiffies != ticks)   /* longer than 1 tick */
-+			lpj &= ~loopbit;
-+	}
-+	printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
-+
-+	for(i=0; i< NR_CPUS; i++)
-+		cpu_data[i].udelay_val = lpj;
-+
-+	return 0;
-+}
-+device_initcall(udelay_recal);
-+
- void prom_soc_init(struct ralink_soc_info *soc_info)
- {
- 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -62,6 +62,7 @@ choice
- 		select CLKSRC_MIPS_GIC
- 		select HAVE_PCI if PCI_MT7621
- 		select SOC_BUS
-+		select GENERIC_CLOCKEVENTS_BROADCAST
- endchoice
- 
- choice