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| author | Michael Lee <igvtee@gmail.com> | 2017-04-27 09:04:31 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2017-05-18 14:50:16 +0200 |
| commit | eee09bfe01e8cc2db1501f82dde7b9b6bb424faf (patch) | |
| tree | 3bfcf47dfb557addf060bae62cdbfca8fe70ce9f /target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch | |
| parent | 224e5f5efa22b8a0132522367afd3b22f05d53e1 (diff) | |
| download | upstream-eee09bfe01e8cc2db1501f82dde7b9b6bb424faf.tar.gz upstream-eee09bfe01e8cc2db1501f82dde7b9b6bb424faf.tar.bz2 upstream-eee09bfe01e8cc2db1501f82dde7b9b6bb424faf.zip | |
ramips: support jumbo frame on mt7621 up to 2k
Signed-off-by: Michael Lee <igvtee@gmail.com>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch b/target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch index 59972bd42e..397d3bd33f 100644 --- a/target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch +++ b/target/linux/ramips/patches-4.4/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch @@ -274,7 +274,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +MODULE_VERSION(MTK_FE_DRV_VERSION); --- /dev/null +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h -@@ -0,0 +1,117 @@ +@@ -0,0 +1,123 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License @@ -322,6 +322,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org> +#define GSW_REG_ISR 0x700c +#define GSW_REG_GPC1 0x7014 + ++#define GSW_REG_MAC_P0_MCR 0x100 ++#define GSW_REG_MAC_P1_MCR 0x200 ++ ++// Global MAC control register ++#define GSW_REG_GMACCR 0x30E0 ++ +#define SYSC_REG_CHIP_REV_ID 0x0c +#define SYSC_REG_CFG1 0x14 +#define RST_CTRL_MCM BIT(2) |