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| author | John Crispin <blogic@openwrt.org> | 2013-06-23 15:50:49 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-06-23 15:50:49 +0000 |
| commit | 5f6caa26e516e578be547df489d2ae8900da58a5 (patch) | |
| tree | 48ec89a784c8c7ebb382cb8486ed0021a07b6109 /target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | |
| parent | 21ee9d504d834133a99fecfd36f1a65f8df8c096 (diff) | |
| download | upstream-5f6caa26e516e578be547df489d2ae8900da58a5.tar.gz upstream-5f6caa26e516e578be547df489d2ae8900da58a5.tar.bz2 upstream-5f6caa26e516e578be547df489d2ae8900da58a5.zip | |
ralink: update patches
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37016 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch new file mode 100644 index 0000000000..c520b66e45 --- /dev/null +++ b/target/linux/ramips/patches-3.9/0139-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch @@ -0,0 +1,25 @@ +From 17d26ed75f0981cdc497f9062aec5f66d3c44d88 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 23 May 2013 18:46:25 +0200 +Subject: [PATCH 139/164] MIPS: ralink: add spi clock definition to mt7620a + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 69729a5..08c96db6 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -183,6 +183,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("10000100.timer", 40000000); + ralink_clk_add("10000500.uart", 40000000); ++ ralink_clk_add("10000b00.spi", 40000000); + ralink_clk_add("10000c00.uartlite", 40000000); + } + +-- +1.7.10.4 + |