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| author | John Crispin <john@openwrt.org> | 2015-02-09 12:13:55 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-02-09 12:13:55 +0000 |
| commit | 654bc380ec549e3cdcc2c286ef7d67fea9509609 (patch) | |
| tree | f25bfc6c0b5a8a9d50c13d0b9df290f25db9112a /target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch | |
| parent | 826b461427fa2abe634e652a05dfc86fc8a6c609 (diff) | |
| download | upstream-654bc380ec549e3cdcc2c286ef7d67fea9509609.tar.gz upstream-654bc380ec549e3cdcc2c286ef7d67fea9509609.tar.bz2 upstream-654bc380ec549e3cdcc2c286ef7d67fea9509609.zip | |
ralink: add 3.18 support
keep default as 3.14, mt7621 gic need to be ported to 3.18
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44349
Diffstat (limited to 'target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch b/target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch new file mode 100644 index 0000000000..f3dead3859 --- /dev/null +++ b/target/linux/ramips/patches-3.18/0023-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch @@ -0,0 +1,52 @@ +From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 4 Aug 2014 20:43:25 +0200 +Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency + scaling + + If the USB HCD is running and the cpu is scaled too low, then the USB stops + working. Increase the idle speed of the core to fix this if the kernel is + built with USB support. + + The values are taken from the Ralink SDK Kernel. + + Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -36,6 +36,12 @@ + #define PMU1_CFG 0x8C + #define DIG_SW_SEL BIT(25) + ++/* clock scaling */ ++#define CLKCFG_FDIV_MASK 0x1f00 ++#define CLKCFG_FDIV_USB_VAL 0x0300 ++#define CLKCFG_FFRAC_MASK 0x001f ++#define CLKCFG_FFRAC_USB_VAL 0x0003 ++ + /* does the board have sdram or ddram */ + static int dram_type; + +@@ -337,6 +343,19 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000c00.uartlite", periph_rate); + ralink_clk_add("10180000.wmac", xtal_rate); ++ ++ if (IS_ENABLED(CONFIG_USB)) { ++ /* ++ * When the CPU goes into sleep mode, the BUS clock will be too low for ++ * USB to function properly ++ */ ++ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); ++ ++ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); ++ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; ++ ++ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); ++ } + } + + void __init ralink_of_remap(void) |