ralink: refresh patches

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 39949

1 files changed, 88 insertions, 0 deletions

diff --git a/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch b/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch
new file mode 100644
index 0000000000..05d95484da
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch
@@ -0,0 +1,88 @@
+Index: linux-3.10.32/arch/mips/ralink/rt288x.c
+===================================================================
+--- linux-3.10.32.orig/arch/mips/ralink/rt288x.c	2014-02-22 20:41:54.000000000 +0000
++++ linux-3.10.32/arch/mips/ralink/rt288x.c	2014-03-18 11:18:06.689596876 +0000
+@@ -17,46 +17,27 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt288x.h>
++#include <asm/mach-ralink/pinmux.h>
+ 
+ #include "common.h"
+ 
+-static struct ralink_pinmux_grp mode_mux[] = {
+-	{
+-		.name = "i2c",
+-		.mask = RT2880_GPIO_MODE_I2C,
+-		.gpio_first = 1,
+-		.gpio_last = 2,
+-	}, {
+-		.name = "spi",
+-		.mask = RT2880_GPIO_MODE_SPI,
+-		.gpio_first = 3,
+-		.gpio_last = 6,
+-	}, {
+-		.name = "uartlite",
+-		.mask = RT2880_GPIO_MODE_UART0,
+-		.gpio_first = 7,
+-		.gpio_last = 14,
+-	}, {
+-		.name = "jtag",
+-		.mask = RT2880_GPIO_MODE_JTAG,
+-		.gpio_first = 17,
+-		.gpio_last = 21,
+-	}, {
+-		.name = "mdio",
+-		.mask = RT2880_GPIO_MODE_MDIO,
+-		.gpio_first = 22,
+-		.gpio_last = 23,
+-	}, {
+-		.name = "sdram",
+-		.mask = RT2880_GPIO_MODE_SDRAM,
+-		.gpio_first = 24,
+-		.gpio_last = 39,
+-	}, {
+-		.name = "pci",
+-		.mask = RT2880_GPIO_MODE_PCI,
+-		.gpio_first = 40,
+-		.gpio_last = 71,
+-	}, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 6) };
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 14) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 21) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 23) };
++static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 39) };
++static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 71) };
++
++static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
++    GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
++    GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
++    GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
++    GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
++    GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
++    GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
++    GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
++    { 0 }
+ };
+ 
+ static void rt288x_wdt_reset(void)
+@@ -69,11 +50,6 @@
+ 	rt_sysc_w32(t, SYSC_REG_CLKCFG);
+ }
+ 
+-struct ralink_pinmux rt_gpio_pinmux = {
+-	.mode = mode_mux,
+-	.wdt_reset = rt288x_wdt_reset,
+-};
+-
+ void __init ralink_clk_init(void)
+ {
+ 	unsigned long cpu_rate;
+@@ -140,4 +116,6 @@
+ 	soc_info->mem_base = RT2880_SDRAM_BASE;
+ 	soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
+ 	soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
++
++        rt2880_pinmux_data = rt2880_pinmux_data_act;
+ }