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| author | John Crispin <john@openwrt.org> | 2014-03-18 19:21:56 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2014-03-18 19:21:56 +0000 |
| commit | 332b94fbd524b944d2296b8ae0bf3db90a64ac90 (patch) | |
| tree | 4eef4c2285c01b870a57a2f663612a4fe53df534 /target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch | |
| parent | 8a97da18e00ac36bdb5871d903044fc9b0826bfd (diff) | |
| download | upstream-332b94fbd524b944d2296b8ae0bf3db90a64ac90.tar.gz upstream-332b94fbd524b944d2296b8ae0bf3db90a64ac90.tar.bz2 upstream-332b94fbd524b944d2296b8ae0bf3db90a64ac90.zip | |
ralink: refresh patches
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 39949
Diffstat (limited to 'target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch new file mode 100644 index 0000000000..5a7d5f9997 --- /dev/null +++ b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch @@ -0,0 +1,59 @@ +From 5689333e7e4396a827a2cb6fa1242159e9af56de Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 20 May 2013 20:57:09 +0200 +Subject: [PATCH 101/133] MIPS: ralink: add verbose pmu info + +Print the PMU and LDO settings on boot. + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -26,6 +26,22 @@ + #define CLKCFG_FFRAC_MASK 0x001f + #define CLKCFG_FFRAC_USB_VAL 0x0003 + ++/* analog */ ++#define PMU0_CFG 0x88 ++#define PMU_SW_SET BIT(28) ++#define A_DCDC_EN BIT(24) ++#define A_SSC_PERI BIT(19) ++#define A_SSC_GEN BIT(18) ++#define A_SSC_M 0x3 ++#define A_SSC_S 16 ++#define A_DLY_M 0x7 ++#define A_DLY_S 8 ++#define A_VTUNE_M 0xff ++ ++/* digital */ ++#define PMU1_CFG 0x8C ++#define DIG_SW_SEL BIT(25) ++ + /* does the board have sdram or ddram */ + static int dram_type; + +@@ -208,6 +224,8 @@ void prom_soc_init(struct ralink_soc_inf + u32 n1; + u32 rev; + u32 cfg0; ++ u32 pmu0; ++ u32 pmu1; + + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); +@@ -255,4 +273,12 @@ void prom_soc_init(struct ralink_soc_inf + BUG(); + } + soc_info->mem_base = MT7620_DRAM_BASE; ++ ++ pmu0 = __raw_readl(sysc + PMU0_CFG); ++ pmu1 = __raw_readl(sysc + PMU1_CFG); ++ ++ pr_info("Analog PMU set to %s control\n", ++ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); ++ pr_info("Digital PMU set to %s control\n", ++ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); + } |