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authorP.Wassi <p.wassi@gmx.at>2016-07-26 06:44:19 +0200
committerJohn Crispin <john@phrozen.org>2016-07-26 08:39:36 +0200
commitdbf107cd2b83f0017446ac5ae07e44b39ed61bfe (patch)
tree663875692a128ec582186c63041986f01f4d03d3 /target/linux/ramips/dts/ArcherC20i.dts
parentd4abe72cce2abd39e0f0f013a98d8b40025b58f6 (diff)
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ramips: Improve TP-Link Archer C20i support
Improve / finalise TP-Link Archer C20i support. Signed-off-by: P.Wassi <p.wassi@gmx.at>
Diffstat (limited to 'target/linux/ramips/dts/ArcherC20i.dts')
-rw-r--r--target/linux/ramips/dts/ArcherC20i.dts46
1 files changed, 41 insertions, 5 deletions
diff --git a/target/linux/ramips/dts/ArcherC20i.dts b/target/linux/ramips/dts/ArcherC20i.dts
index e7a7b07346..a58fa57ced 100644
--- a/target/linux/ramips/dts/ArcherC20i.dts
+++ b/target/linux/ramips/dts/ArcherC20i.dts
@@ -12,20 +12,57 @@
gpio-leds {
compatible = "gpio-leds";
+ lan {
+ label = "c20i:blue:lan";
+ gpios = <&gpio0 1 1>;
+ };
+ usb {
+ label = "c20i:blue:usb";
+ gpios = <&gpio0 11 1>;
+ };
+ wps {
+ label = "c20i:blue:wps";
+ gpios = <&gpio1 15 1>;
+ };
+ wan {
+ label = "c20i:blue:wan";
+ gpios = <&gpio2 0 1>;
+ };
+ wlan {
+ label = "c20i:blue:wlan";
+ gpios = <&gpio3 0 1>;
+ };
};
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
+ gpio-keys {
+ compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
- poll-interval = <20>;
+ rfkill {
+ label = "rfkill";
+ gpios = <&gpio0 2 1>;
+ linux,code = <0xf7>;
+ };
+ reset_wps {
+ label = "reset_wps";
+ gpios = <&gpio0 13 1>;
+ linux,code = <0x198>;
+ };
};
};
+&gpio1 {
+ status = "okay";
+};
+
&gpio2 {
status = "okay";
};
+&gpio3 {
+ status = "okay";
+};
+
&spi0 {
status = "okay";
@@ -73,7 +110,7 @@
&pinctrl {
state_default: pinctrl0 {
gpio {
- ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd";
+ ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk";
ralink,function = "gpio";
};
};
@@ -81,7 +118,6 @@
&ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&ephy_pins>;
mtd-mac-address = <&rom 0xf100>;
mediatek,portmap = "wllll";
};