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| author | John Crispin <john@openwrt.org> | 2015-08-17 06:03:57 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-08-17 06:03:57 +0000 |
| commit | 7261fde797e1b63f032af4e7b5ac9eebc66c4a31 (patch) | |
| tree | c47b88867fa5c873a7839957200555fab041cd65 /target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch | |
| parent | f32116987f56a4441848e6970beb361b422729e7 (diff) | |
| download | upstream-7261fde797e1b63f032af4e7b5ac9eebc66c4a31.tar.gz upstream-7261fde797e1b63f032af4e7b5ac9eebc66c4a31.tar.bz2 upstream-7261fde797e1b63f032af4e7b5ac9eebc66c4a31.zip | |
oxnas: prepare for kernel 4.1
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 46636
Diffstat (limited to 'target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch')
| -rw-r--r-- | target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch b/target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch new file mode 100644 index 0000000000..d0833eaaf0 --- /dev/null +++ b/target/linux/oxnas/patches-4.1/320-oxnas-irqchip.patch @@ -0,0 +1,34 @@ +--- a/drivers/irqchip/Kconfig ++++ b/drivers/irqchip/Kconfig +@@ -27,6 +27,11 @@ config ARM_GIC_V3_ITS + bool + select PCI_MSI_IRQ_DOMAIN + ++config PLXTECH_RPS ++ def_bool y if ARHC_OXNAS ++ depends on ARCH_OXNAS ++ select IRQ_DOMAIN ++ + config ARM_NVIC + bool + select IRQ_DOMAIN +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc. + obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o + obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o + obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o ++obj-$(CONFIG_PLXTECH_RPS) += irq-rps.o + obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o + obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o + obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o +--- a/drivers/irqchip/irq-gic.c ++++ b/drivers/irqchip/irq-gic.c +@@ -1036,6 +1036,7 @@ IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm, + IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); + IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); + IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); ++IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init); + IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); + IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); + |