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| author | Chuanhong Guo <gch981213@gmail.com> | 2021-08-24 12:04:51 +0800 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2021-08-27 10:26:25 +0800 |
| commit | 01b452fe2dace93343d8b568a57317d5fd53aea2 (patch) | |
| tree | 3dff79b075e9f0986922eb17f7167f73aef3648e /target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch | |
| parent | c6ed31630d6c9a1cb8b83a37bac77e480bc127b7 (diff) | |
| download | upstream-01b452fe2dace93343d8b568a57317d5fd53aea2.tar.gz upstream-01b452fe2dace93343d8b568a57317d5fd53aea2.tar.bz2 upstream-01b452fe2dace93343d8b568a57317d5fd53aea2.zip | |
mediatek: change dts to use the new snand driver
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch')
| -rw-r--r-- | target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch | 48 |
1 files changed, 14 insertions, 34 deletions
diff --git a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch index 8febc65d1b..e7c5d9b167 100644 --- a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch @@ -11,27 +11,21 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,28 @@ +@@ -272,6 +272,22 @@ status = "disabled"; }; -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snfi"; -+ reg = <0x1100d000 0x1000>; ++ snand: snfi@1100d000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ compatible = "mediatek,mt7629-snand"; ++ reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>; ++ reg-names = "nfi", "ecc"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "spi_clk"; -+ ecc-engine = <&bch>; ++ <&pericfg CLK_PERI_SNFI_PD>, ++ <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; @@ -42,27 +36,15 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> "mediatek,mt7622-spi"; --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,52 @@ +@@ -254,6 +254,38 @@ }; }; -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; ++&snand { + status = "okay"; ++ mediatek,quad-spi; + -+ spi_nand@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spi-nand"; -+ spi-max-frequency = <104000000>; -+ reg = <0>; -+ -+ partitions { ++ partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; @@ -87,8 +69,6 @@ Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> + label = "firmware"; + reg = <0x1c0000 0x1000000>; + }; -+ -+ }; + }; +}; + |