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| author | John Crispin <john@openwrt.org> | 2013-06-29 16:33:18 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2013-06-29 16:33:18 +0000 |
| commit | aff84655f5ab9bc38a7c5b0755ea0f209fa64fe9 (patch) | |
| tree | 19b2f80a1b9058164b6556f349680d2d985691bc /target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch | |
| parent | 2d506f46fb68d5290d4cfc4ebb43edeabe1595d6 (diff) | |
| download | upstream-aff84655f5ab9bc38a7c5b0755ea0f209fa64fe9.tar.gz upstream-aff84655f5ab9bc38a7c5b0755ea0f209fa64fe9.tar.bz2 upstream-aff84655f5ab9bc38a7c5b0755ea0f209fa64fe9.zip | |
lantiq: remove 3.7 kernel patches
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 37084
Diffstat (limited to 'target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch b/target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch deleted file mode 100644 index fec136ea30..0000000000 --- a/target/linux/lantiq/patches-3.7/0004-MIPS-lantiq-adds-xrx200-ethernet-clock-definition.patch +++ /dev/null @@ -1,24 +0,0 @@ -From f2bbe41c507b475c6f0ae1fca69c7aac6d31d228 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 9 Nov 2012 13:34:18 +0100 -Subject: [PATCH 4/6] MIPS: lantiq: adds xrx200 ethernet clock definition - -Signed-off-by: John Crispin <blogic@openwrt.org> -Patchwork: http://patchwork.linux-mips.org/patch/4521 ---- - arch/mips/lantiq/xway/sysctrl.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -370,6 +370,10 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); - clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); - clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); -+ clkdev_add_pmu("1e108000.eth", NULL, 0, -+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | -+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | -+ PMU_PPE_QSB | PMU_PPE_TOP); - } else if (of_machine_is_compatible("lantiq,ar9")) { - clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), - ltq_ar9_fpi_hz()); |